* [PATCH v1 1/3] riscv: dts: starfive: Enable axp15060 pmic for cpufreq
2023-04-11 8:32 [PATCH v1 0/3] Add JH7110 cpufreq support Mason Huo
@ 2023-04-11 8:32 ` Mason Huo
2023-04-11 9:13 ` Conor Dooley
2023-04-11 8:32 ` [PATCH v1 2/3] cpufreq: dt-platdev: Add JH7110 SOC to the allowlist Mason Huo
` (2 subsequent siblings)
3 siblings, 1 reply; 14+ messages in thread
From: Mason Huo @ 2023-04-11 8:32 UTC (permalink / raw)
To: Rafael J. Wysocki, Viresh Kumar, Emil Renner Berthing,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Paul Walmsley,
Palmer Dabbelt, Albert Ou
Cc: Shengyu Qu, linux-pm, devicetree, linux-kernel, linux-riscv,
Mason Huo
The VisionFive 2 board has an embedded pmic axp15060,
which supports the cpu DVFS through the dcdc2 regulator.
This patch enables axp15060 pmic and configs the dcdc2.
Signed-off-by: Mason Huo <mason.huo@starfivetech.com>
---
.../starfive/jh7110-starfive-visionfive-2.dtsi | 15 +++++++++++++++
1 file changed, 15 insertions(+)
diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
index 2a6d81609284..df582bddae4b 100644
--- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
@@ -114,6 +114,21 @@ &i2c5 {
pinctrl-names = "default";
pinctrl-0 = <&i2c5_pins>;
status = "okay";
+
+ pmic: axp15060_reg@36 {
+ compatible = "x-powers,axp15060";
+ reg = <0x36>;
+
+ regulators {
+ reg_dcdc2: dcdc2 {
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <1540000>;
+ regulator-name = "vdd-cpu";
+ };
+ };
+ };
};
&i2c6 {
--
2.39.2
^ permalink raw reply related [flat|nested] 14+ messages in thread* Re: [PATCH v1 1/3] riscv: dts: starfive: Enable axp15060 pmic for cpufreq
2023-04-11 8:32 ` [PATCH v1 1/3] riscv: dts: starfive: Enable axp15060 pmic for cpufreq Mason Huo
@ 2023-04-11 9:13 ` Conor Dooley
2023-04-11 14:49 ` Shengyu Qu
2023-04-12 2:36 ` Mason Huo
0 siblings, 2 replies; 14+ messages in thread
From: Conor Dooley @ 2023-04-11 9:13 UTC (permalink / raw)
To: Mason Huo
Cc: Rafael J. Wysocki, Viresh Kumar, Emil Renner Berthing,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Paul Walmsley,
Palmer Dabbelt, Albert Ou, Shengyu Qu, linux-pm, devicetree,
linux-kernel, linux-riscv
[-- Attachment #1: Type: text/plain, Size: 1371 bytes --]
On Tue, Apr 11, 2023 at 04:32:55PM +0800, Mason Huo wrote:
> The VisionFive 2 board has an embedded pmic axp15060,
> which supports the cpu DVFS through the dcdc2 regulator.
> This patch enables axp15060 pmic and configs the dcdc2.
>
> Signed-off-by: Mason Huo <mason.huo@starfivetech.com>
> ---
> .../starfive/jh7110-starfive-visionfive-2.dtsi | 15 +++++++++++++++
> 1 file changed, 15 insertions(+)
>
> diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
> index 2a6d81609284..df582bddae4b 100644
> --- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
> +++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
> @@ -114,6 +114,21 @@ &i2c5 {
> pinctrl-names = "default";
> pinctrl-0 = <&i2c5_pins>;
> status = "okay";
> +
> + pmic: axp15060_reg@36 {
No underscores in node names please & "pmic" is the generic node name
for pmics.
Cheers,
Conor.
> + compatible = "x-powers,axp15060";
> + reg = <0x36>;
> +
> + regulators {
> + reg_dcdc2: dcdc2 {
> + regulator-boot-on;
> + regulator-always-on;
> + regulator-min-microvolt = <500000>;
> + regulator-max-microvolt = <1540000>;
> + regulator-name = "vdd-cpu";
> + };
> + };
> + };
> };
>
> &i2c6 {
> --
> 2.39.2
>
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^ permalink raw reply [flat|nested] 14+ messages in thread* Re: [PATCH v1 1/3] riscv: dts: starfive: Enable axp15060 pmic for cpufreq
2023-04-11 9:13 ` Conor Dooley
@ 2023-04-11 14:49 ` Shengyu Qu
2023-04-12 2:36 ` Mason Huo
2023-04-12 2:36 ` Mason Huo
1 sibling, 1 reply; 14+ messages in thread
From: Shengyu Qu @ 2023-04-11 14:49 UTC (permalink / raw)
To: Conor Dooley, Mason Huo
Cc: Rafael J. Wysocki, Viresh Kumar, Emil Renner Berthing,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Paul Walmsley,
Palmer Dabbelt, Albert Ou, linux-pm, devicetree, linux-kernel,
linux-riscv
[-- Attachment #1.1.1: Type: text/plain, Size: 1677 bytes --]
> On Tue, Apr 11, 2023 at 04:32:55PM +0800, Mason Huo wrote:
>> The VisionFive 2 board has an embedded pmic axp15060,
>> which supports the cpu DVFS through the dcdc2 regulator.
>> This patch enables axp15060 pmic and configs the dcdc2.
>>
>> Signed-off-by: Mason Huo <mason.huo@starfivetech.com>
>> ---
>> .../starfive/jh7110-starfive-visionfive-2.dtsi | 15 +++++++++++++++
>> 1 file changed, 15 insertions(+)
>>
>> diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
>> index 2a6d81609284..df582bddae4b 100644
>> --- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
>> +++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
>> @@ -114,6 +114,21 @@ &i2c5 {
>> pinctrl-names = "default";
>> pinctrl-0 = <&i2c5_pins>;
>> status = "okay";
>> +
>> + pmic: axp15060_reg@36 {
> No underscores in node names please & "pmic" is the generic node name
> for pmics.
>
> Cheers,
> Conor.
>
>> + compatible = "x-powers,axp15060";
>> + reg = <0x36>;
>> +
>> + regulators {
>> + reg_dcdc2: dcdc2 {
reg_dcdc2 seems not a good name, too generic for identification. In most
cases, it's same as regulator-name but using "_" rather than "-".
>> + regulator-boot-on;
It should not be used, in Documentation/devicetree/bindings/regulator
/regulator.yaml, it is described as follows:
"This property is intended to only be used for regulators where software
cannot read the state of the regulator."
In this case, regulator state is completely able to be read by driver.
Best regards,
Shengyu
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^ permalink raw reply [flat|nested] 14+ messages in thread* Re: [PATCH v1 1/3] riscv: dts: starfive: Enable axp15060 pmic for cpufreq
2023-04-11 14:49 ` Shengyu Qu
@ 2023-04-12 2:36 ` Mason Huo
0 siblings, 0 replies; 14+ messages in thread
From: Mason Huo @ 2023-04-12 2:36 UTC (permalink / raw)
To: Shengyu Qu, Conor Dooley
Cc: Rafael J. Wysocki, Viresh Kumar, Emil Renner Berthing,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Paul Walmsley,
Palmer Dabbelt, Albert Ou, linux-pm, devicetree, linux-kernel,
linux-riscv
On 2023/4/11 22:49, Shengyu Qu wrote:
>> On Tue, Apr 11, 2023 at 04:32:55PM +0800, Mason Huo wrote:
>>> The VisionFive 2 board has an embedded pmic axp15060,
>>> which supports the cpu DVFS through the dcdc2 regulator.
>>> This patch enables axp15060 pmic and configs the dcdc2.
>>>
>>> Signed-off-by: Mason Huo <mason.huo@starfivetech.com>
>>> ---
>>> .../starfive/jh7110-starfive-visionfive-2.dtsi | 15 +++++++++++++++
>>> 1 file changed, 15 insertions(+)
>>>
>>> diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
>>> index 2a6d81609284..df582bddae4b 100644
>>> --- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
>>> +++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
>>> @@ -114,6 +114,21 @@ &i2c5 {
>>> pinctrl-names = "default";
>>> pinctrl-0 = <&i2c5_pins>;
>>> status = "okay";
>>> +
>>> + pmic: axp15060_reg@36 {
>> No underscores in node names please & "pmic" is the generic node name
>> for pmics.
>>
>> Cheers,
>> Conor.
>>
>>> + compatible = "x-powers,axp15060";
>>> + reg = <0x36>;
>>> +
>>> + regulators {
>>> + reg_dcdc2: dcdc2 {
>
> reg_dcdc2 seems not a good name, too generic for identification. In most
>
> cases, it's same as regulator-name but using "_" rather than "-".
>
Hi Shengyu,
Thanks for your review.
Will change to "vdd_cpu".
>>> + regulator-boot-on;
>
> It should not be used, in Documentation/devicetree/bindings/regulator
>
> /regulator.yaml, it is described as follows:
>
> "This property is intended to only be used for regulators where software
>
> cannot read the state of the regulator."
>
> In this case, regulator state is completely able to be read by driver.
>
> Best regards,
>
> Shengyu
>Will remove it.
Thanks
Mason
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH v1 1/3] riscv: dts: starfive: Enable axp15060 pmic for cpufreq
2023-04-11 9:13 ` Conor Dooley
2023-04-11 14:49 ` Shengyu Qu
@ 2023-04-12 2:36 ` Mason Huo
1 sibling, 0 replies; 14+ messages in thread
From: Mason Huo @ 2023-04-12 2:36 UTC (permalink / raw)
To: Conor Dooley
Cc: Rafael J. Wysocki, Viresh Kumar, Emil Renner Berthing,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Paul Walmsley,
Palmer Dabbelt, Albert Ou, Shengyu Qu, linux-pm, devicetree,
linux-kernel, linux-riscv
On 2023/4/11 17:13, Conor Dooley wrote:
> On Tue, Apr 11, 2023 at 04:32:55PM +0800, Mason Huo wrote:
>> The VisionFive 2 board has an embedded pmic axp15060,
>> which supports the cpu DVFS through the dcdc2 regulator.
>> This patch enables axp15060 pmic and configs the dcdc2.
>>
>> Signed-off-by: Mason Huo <mason.huo@starfivetech.com>
>> ---
>> .../starfive/jh7110-starfive-visionfive-2.dtsi | 15 +++++++++++++++
>> 1 file changed, 15 insertions(+)
>>
>> diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
>> index 2a6d81609284..df582bddae4b 100644
>> --- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
>> +++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
>> @@ -114,6 +114,21 @@ &i2c5 {
>> pinctrl-names = "default";
>> pinctrl-0 = <&i2c5_pins>;
>> status = "okay";
>> +
>> + pmic: axp15060_reg@36 {
>
> No underscores in node names please & "pmic" is the generic node name
> for pmics.
>
> Cheers,
> Conor.
>
Address it in next version.
Thanks
Mason
>> + compatible = "x-powers,axp15060";
>> + reg = <0x36>;
>> +
>> + regulators {
>> + reg_dcdc2: dcdc2 {
>> + regulator-boot-on;
>> + regulator-always-on;
>> + regulator-min-microvolt = <500000>;
>> + regulator-max-microvolt = <1540000>;
>> + regulator-name = "vdd-cpu";
>> + };
>> + };
>> + };
>> };
>>
>> &i2c6 {
>> --
>> 2.39.2
>>
^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH v1 2/3] cpufreq: dt-platdev: Add JH7110 SOC to the allowlist
2023-04-11 8:32 [PATCH v1 0/3] Add JH7110 cpufreq support Mason Huo
2023-04-11 8:32 ` [PATCH v1 1/3] riscv: dts: starfive: Enable axp15060 pmic for cpufreq Mason Huo
@ 2023-04-11 8:32 ` Mason Huo
2023-04-11 9:20 ` Conor Dooley
2023-04-11 8:32 ` [PATCH v1 3/3] riscv: dts: starfive: Add cpu scaling for JH7110 SoC Mason Huo
2023-04-11 15:58 ` [PATCH v1 0/3] Add JH7110 cpufreq support Rafael J. Wysocki
3 siblings, 1 reply; 14+ messages in thread
From: Mason Huo @ 2023-04-11 8:32 UTC (permalink / raw)
To: Rafael J. Wysocki, Viresh Kumar, Emil Renner Berthing,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Paul Walmsley,
Palmer Dabbelt, Albert Ou
Cc: Shengyu Qu, linux-pm, devicetree, linux-kernel, linux-riscv,
Mason Huo
Add the compatible strings for supporting the generic
cpufreq driver on the StarFive JH7110 SoC.
Signed-off-by: Mason Huo <mason.huo@starfivetech.com>
---
drivers/cpufreq/cpufreq-dt-platdev.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/cpufreq/cpufreq-dt-platdev.c b/drivers/cpufreq/cpufreq-dt-platdev.c
index e85703651098..a1ac955aa7e2 100644
--- a/drivers/cpufreq/cpufreq-dt-platdev.c
+++ b/drivers/cpufreq/cpufreq-dt-platdev.c
@@ -92,6 +92,7 @@ static const struct of_device_id allowlist[] __initconst = {
{ .compatible = "xlnx,zynq-7000", },
{ .compatible = "xlnx,zynqmp", },
+ { .compatible = "starfive,jh7110", },
{ }
};
--
2.39.2
^ permalink raw reply related [flat|nested] 14+ messages in thread* Re: [PATCH v1 2/3] cpufreq: dt-platdev: Add JH7110 SOC to the allowlist
2023-04-11 8:32 ` [PATCH v1 2/3] cpufreq: dt-platdev: Add JH7110 SOC to the allowlist Mason Huo
@ 2023-04-11 9:20 ` Conor Dooley
2023-04-12 2:36 ` Mason Huo
0 siblings, 1 reply; 14+ messages in thread
From: Conor Dooley @ 2023-04-11 9:20 UTC (permalink / raw)
To: Mason Huo
Cc: Rafael J. Wysocki, Viresh Kumar, Emil Renner Berthing,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Paul Walmsley,
Palmer Dabbelt, Albert Ou, Shengyu Qu, linux-pm, devicetree,
linux-kernel, linux-riscv
[-- Attachment #1: Type: text/plain, Size: 840 bytes --]
On Tue, Apr 11, 2023 at 04:32:56PM +0800, Mason Huo wrote:
> Add the compatible strings for supporting the generic
> cpufreq driver on the StarFive JH7110 SoC.
>
> Signed-off-by: Mason Huo <mason.huo@starfivetech.com>
> ---
> drivers/cpufreq/cpufreq-dt-platdev.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/drivers/cpufreq/cpufreq-dt-platdev.c b/drivers/cpufreq/cpufreq-dt-platdev.c
> index e85703651098..a1ac955aa7e2 100644
> --- a/drivers/cpufreq/cpufreq-dt-platdev.c
> +++ b/drivers/cpufreq/cpufreq-dt-platdev.c
> @@ -92,6 +92,7 @@ static const struct of_device_id allowlist[] __initconst = {
>
> { .compatible = "xlnx,zynq-7000", },
> { .compatible = "xlnx,zynqmp", },
> + { .compatible = "starfive,jh7110", },
This struct looks to be in alphabetical order with a blank line between
vendors.
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^ permalink raw reply [flat|nested] 14+ messages in thread* Re: [PATCH v1 2/3] cpufreq: dt-platdev: Add JH7110 SOC to the allowlist
2023-04-11 9:20 ` Conor Dooley
@ 2023-04-12 2:36 ` Mason Huo
0 siblings, 0 replies; 14+ messages in thread
From: Mason Huo @ 2023-04-12 2:36 UTC (permalink / raw)
To: Conor Dooley
Cc: Rafael J. Wysocki, Viresh Kumar, Emil Renner Berthing,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Paul Walmsley,
Palmer Dabbelt, Albert Ou, Shengyu Qu, linux-pm, devicetree,
linux-kernel, linux-riscv
On 2023/4/11 17:20, Conor Dooley wrote:
> On Tue, Apr 11, 2023 at 04:32:56PM +0800, Mason Huo wrote:
>> Add the compatible strings for supporting the generic
>> cpufreq driver on the StarFive JH7110 SoC.
>>
>> Signed-off-by: Mason Huo <mason.huo@starfivetech.com>
>> ---
>> drivers/cpufreq/cpufreq-dt-platdev.c | 1 +
>> 1 file changed, 1 insertion(+)
>>
>> diff --git a/drivers/cpufreq/cpufreq-dt-platdev.c b/drivers/cpufreq/cpufreq-dt-platdev.c
>> index e85703651098..a1ac955aa7e2 100644
>> --- a/drivers/cpufreq/cpufreq-dt-platdev.c
>> +++ b/drivers/cpufreq/cpufreq-dt-platdev.c
>> @@ -92,6 +92,7 @@ static const struct of_device_id allowlist[] __initconst = {
>>
>> { .compatible = "xlnx,zynq-7000", },
>> { .compatible = "xlnx,zynqmp", },
>> + { .compatible = "starfive,jh7110", },
>
> This struct looks to be in alphabetical order with a blank line between
> vendors.
Right. Should place it behind "st-ericsson".
Thanks
Mason
^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH v1 3/3] riscv: dts: starfive: Add cpu scaling for JH7110 SoC
2023-04-11 8:32 [PATCH v1 0/3] Add JH7110 cpufreq support Mason Huo
2023-04-11 8:32 ` [PATCH v1 1/3] riscv: dts: starfive: Enable axp15060 pmic for cpufreq Mason Huo
2023-04-11 8:32 ` [PATCH v1 2/3] cpufreq: dt-platdev: Add JH7110 SOC to the allowlist Mason Huo
@ 2023-04-11 8:32 ` Mason Huo
2023-04-11 9:06 ` Conor Dooley
2023-04-11 15:58 ` [PATCH v1 0/3] Add JH7110 cpufreq support Rafael J. Wysocki
3 siblings, 1 reply; 14+ messages in thread
From: Mason Huo @ 2023-04-11 8:32 UTC (permalink / raw)
To: Rafael J. Wysocki, Viresh Kumar, Emil Renner Berthing,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Paul Walmsley,
Palmer Dabbelt, Albert Ou
Cc: Shengyu Qu, linux-pm, devicetree, linux-kernel, linux-riscv,
Mason Huo
Add the operating-points-v2 to support cpu scaling
on StarFive JH7110 SoC.
It supports up to 4 cpu frequency loads.
Signed-off-by: Mason Huo <mason.huo@starfivetech.com>
---
.../jh7110-starfive-visionfive-2.dtsi | 25 +++++++++++++++++++
arch/riscv/boot/dts/starfive/jh7110.dtsi | 25 +++++++++++++++++++
2 files changed, 50 insertions(+)
diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
index df582bddae4b..ae446b268e78 100644
--- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
@@ -228,3 +228,28 @@ &uart0 {
pinctrl-0 = <&uart0_pins>;
status = "okay";
};
+
+&U74_1 {
+ clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>;
+ clock-names = "cpu";
+ cpu-supply = <®_dcdc2>;
+};
+
+&U74_2 {
+ clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>;
+ clock-names = "cpu";
+ cpu-supply = <®_dcdc2>;
+};
+
+&U74_3 {
+ clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>;
+ clock-names = "cpu";
+ cpu-supply = <®_dcdc2>;
+};
+
+&U74_4 {
+ clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>;
+ clock-names = "cpu";
+ cpu-supply = <®_dcdc2>;
+};
+
diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi
index 4c5fdb905da8..c867f968d054 100644
--- a/arch/riscv/boot/dts/starfive/jh7110.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
@@ -53,6 +53,7 @@ U74_1: cpu@1 {
next-level-cache = <&ccache>;
riscv,isa = "rv64imafdc_zba_zbb";
tlb-split;
+ operating-points-v2 = <&cpu_opp>;
cpu1_intc: interrupt-controller {
compatible = "riscv,cpu-intc";
@@ -79,6 +80,7 @@ U74_2: cpu@2 {
next-level-cache = <&ccache>;
riscv,isa = "rv64imafdc_zba_zbb";
tlb-split;
+ operating-points-v2 = <&cpu_opp>;
cpu2_intc: interrupt-controller {
compatible = "riscv,cpu-intc";
@@ -105,6 +107,7 @@ U74_3: cpu@3 {
next-level-cache = <&ccache>;
riscv,isa = "rv64imafdc_zba_zbb";
tlb-split;
+ operating-points-v2 = <&cpu_opp>;
cpu3_intc: interrupt-controller {
compatible = "riscv,cpu-intc";
@@ -131,6 +134,7 @@ U74_4: cpu@4 {
next-level-cache = <&ccache>;
riscv,isa = "rv64imafdc_zba_zbb";
tlb-split;
+ operating-points-v2 = <&cpu_opp>;
cpu4_intc: interrupt-controller {
compatible = "riscv,cpu-intc";
@@ -164,6 +168,27 @@ core4 {
};
};
+ cpu_opp: opp-table-0 {
+ compatible = "operating-points-v2";
+ opp-shared;
+ opp-375000000 {
+ opp-hz = /bits/ 64 <375000000>;
+ opp-microvolt = <800000>;
+ };
+ opp-500000000 {
+ opp-hz = /bits/ 64 <500000000>;
+ opp-microvolt = <800000>;
+ };
+ opp-750000000 {
+ opp-hz = /bits/ 64 <750000000>;
+ opp-microvolt = <800000>;
+ };
+ opp-1500000000 {
+ opp-hz = /bits/ 64 <1500000000>;
+ opp-microvolt = <1040000>;
+ };
+ };
+
gmac0_rgmii_rxin: gmac0-rgmii-rxin-clock {
compatible = "fixed-clock";
clock-output-names = "gmac0_rgmii_rxin";
--
2.39.2
^ permalink raw reply related [flat|nested] 14+ messages in thread* Re: [PATCH v1 3/3] riscv: dts: starfive: Add cpu scaling for JH7110 SoC
2023-04-11 8:32 ` [PATCH v1 3/3] riscv: dts: starfive: Add cpu scaling for JH7110 SoC Mason Huo
@ 2023-04-11 9:06 ` Conor Dooley
2023-04-12 2:35 ` Mason Huo
0 siblings, 1 reply; 14+ messages in thread
From: Conor Dooley @ 2023-04-11 9:06 UTC (permalink / raw)
To: Mason Huo
Cc: Rafael J. Wysocki, Viresh Kumar, Emil Renner Berthing,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Paul Walmsley,
Palmer Dabbelt, Albert Ou, Shengyu Qu, linux-pm, devicetree,
linux-kernel, linux-riscv
[-- Attachment #1: Type: text/plain, Size: 1695 bytes --]
Hey Mason,
On Tue, Apr 11, 2023 at 04:32:57PM +0800, Mason Huo wrote:
> Add the operating-points-v2 to support cpu scaling
> on StarFive JH7110 SoC.
(btw, there's no need to wrap commit messages at 52 columns, you have
72 to work with)
> It supports up to 4 cpu frequency loads.
>
> Signed-off-by: Mason Huo <mason.huo@starfivetech.com>
> ---
> .../jh7110-starfive-visionfive-2.dtsi | 25 +++++++++++++++++++
> arch/riscv/boot/dts/starfive/jh7110.dtsi | 25 +++++++++++++++++++
> 2 files changed, 50 insertions(+)
>
> diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
> index df582bddae4b..ae446b268e78 100644
> --- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
> +++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
> @@ -228,3 +228,28 @@ &uart0 {
> pinctrl-0 = <&uart0_pins>;
> status = "okay";
> };
> +
> +&U74_1 {
> + clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>;
> + clock-names = "cpu";
> + cpu-supply = <®_dcdc2>;
> +};
> +
> +&U74_2 {
> + clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>;
> + clock-names = "cpu";
> + cpu-supply = <®_dcdc2>;
> +};
> +
> +&U74_3 {
> + clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>;
> + clock-names = "cpu";
> + cpu-supply = <®_dcdc2>;
> +};
> +
> +&U74_4 {
> + clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>;
^^
There's a double space in each of these.
> + clock-names = "cpu";
> + cpu-supply = <®_dcdc2>;
> +};
How come these two clock properties are being added in <board>.dtsi?
Should they not be in <soc>.dtsi?
Thanks,
Conor.
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^ permalink raw reply [flat|nested] 14+ messages in thread* Re: [PATCH v1 3/3] riscv: dts: starfive: Add cpu scaling for JH7110 SoC
2023-04-11 9:06 ` Conor Dooley
@ 2023-04-12 2:35 ` Mason Huo
0 siblings, 0 replies; 14+ messages in thread
From: Mason Huo @ 2023-04-12 2:35 UTC (permalink / raw)
To: Conor Dooley
Cc: Rafael J. Wysocki, Viresh Kumar, Emil Renner Berthing,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Paul Walmsley,
Palmer Dabbelt, Albert Ou, Shengyu Qu, linux-pm, devicetree,
linux-kernel, linux-riscv
On 2023/4/11 17:06, Conor Dooley wrote:
> Hey Mason,
>
> On Tue, Apr 11, 2023 at 04:32:57PM +0800, Mason Huo wrote:
>> Add the operating-points-v2 to support cpu scaling
>> on StarFive JH7110 SoC.
>
> (btw, there's no need to wrap commit messages at 52 columns, you have
> 72 to work with)
>
Hi Conor,
Thanks for your review.
Will place it in the same line.
>> It supports up to 4 cpu frequency loads.
>>
>> Signed-off-by: Mason Huo <mason.huo@starfivetech.com>
>> ---
>> .../jh7110-starfive-visionfive-2.dtsi | 25 +++++++++++++++++++
>> arch/riscv/boot/dts/starfive/jh7110.dtsi | 25 +++++++++++++++++++
>> 2 files changed, 50 insertions(+)
>>
>> diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
>> index df582bddae4b..ae446b268e78 100644
>> --- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
>> +++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
>> @@ -228,3 +228,28 @@ &uart0 {
>> pinctrl-0 = <&uart0_pins>;
>> status = "okay";
>> };
>> +
>> +&U74_1 {
>> + clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>;
>> + clock-names = "cpu";
>> + cpu-supply = <®_dcdc2>;
>> +};
>> +
>> +&U74_2 {
>> + clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>;
>> + clock-names = "cpu";
>> + cpu-supply = <®_dcdc2>;
>> +};
>> +
>> +&U74_3 {
>> + clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>;
>> + clock-names = "cpu";
>> + cpu-supply = <®_dcdc2>;
>> +};
>> +
>> +&U74_4 {
>> + clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>;
> ^^
> There's a double space in each of these.
>
>> + clock-names = "cpu";
>> + cpu-supply = <®_dcdc2>;
>> +};
>
> How come these two clock properties are being added in <board>.dtsi?
> Should they not be in <soc>.dtsi?
>> Thanks,
> Conor.
Yes, will move them to <soc>.dtsi
Thanks
Mason
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH v1 0/3] Add JH7110 cpufreq support
2023-04-11 8:32 [PATCH v1 0/3] Add JH7110 cpufreq support Mason Huo
` (2 preceding siblings ...)
2023-04-11 8:32 ` [PATCH v1 3/3] riscv: dts: starfive: Add cpu scaling for JH7110 SoC Mason Huo
@ 2023-04-11 15:58 ` Rafael J. Wysocki
2023-04-21 7:47 ` Viresh Kumar
3 siblings, 1 reply; 14+ messages in thread
From: Rafael J. Wysocki @ 2023-04-11 15:58 UTC (permalink / raw)
To: Mason Huo, Viresh Kumar
Cc: Emil Renner Berthing, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Paul Walmsley, Palmer Dabbelt, Albert Ou,
Shengyu Qu, linux-pm, devicetree, linux-kernel, linux-riscv
On Tue, Apr 11, 2023 at 10:33 AM Mason Huo <mason.huo@starfivetech.com> wrote:
>
> The StarFive JH7110 SoC has four RISC-V cores,
> and it supports up to 4 cpu frequency loads.
>
> This patchset adds the compatible strings into the allowlist
> for supporting the generic cpufreq driver on JH7110 SoC.
> Also, it enables the axp15060 pmic for the cpu power source.
>
> The series has been tested on the VisionFive 2 boards which
> are equipped with JH7110 SoC and axp15060 pmic.
>
>
> This patchset is based on v6.3-rc4 with these patches applied:
> [1] ("Basic clock, reset & device tree support for StarFive JH7110 RISC-V SoC")
> https://lore.kernel.org/all/20230401111934.130844-1-hal.feng@starfivetech.com/
> [2] ("Add X-Powers AXP15060 PMIC support")
> https://lore.kernel.org/all/TY3P286MB2611A814E580C96DC6F187B798969@TY3P286MB2611.JPNP286.PROD.OUTLOOK.COM/
>
> Mason Huo (3):
> riscv: dts: starfive: Enable axp15060 pmic for cpufreq
> cpufreq: dt-platdev: Add JH7110 SOC to the allowlist
> riscv: dts: starfive: Add cpu scaling for JH7110 SoC
>
> .../jh7110-starfive-visionfive-2.dtsi | 40 +++++++++++++++++++
> arch/riscv/boot/dts/starfive/jh7110.dtsi | 25 ++++++++++++
> drivers/cpufreq/cpufreq-dt-platdev.c | 1 +
> 3 files changed, 66 insertions(+)
Viresh, can you have a look at this, please?
It is very similar to the ARM thing AFAICS.
^ permalink raw reply [flat|nested] 14+ messages in thread* Re: [PATCH v1 0/3] Add JH7110 cpufreq support
2023-04-11 15:58 ` [PATCH v1 0/3] Add JH7110 cpufreq support Rafael J. Wysocki
@ 2023-04-21 7:47 ` Viresh Kumar
0 siblings, 0 replies; 14+ messages in thread
From: Viresh Kumar @ 2023-04-21 7:47 UTC (permalink / raw)
To: Rafael J. Wysocki
Cc: Mason Huo, Emil Renner Berthing, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Paul Walmsley, Palmer Dabbelt, Albert Ou,
Shengyu Qu, linux-pm, devicetree, linux-kernel, linux-riscv
On 11-04-23, 17:58, Rafael J. Wysocki wrote:
> Viresh, can you have a look at this, please?
>
> It is very similar to the ARM thing AFAICS.
Sorry, I missed your email earlier. I have already applied the cpufreq
specific patch now.
--
viresh
^ permalink raw reply [flat|nested] 14+ messages in thread