From: Conor Dooley <conor@kernel.org>
To: "Lad, Prabhakar" <prabhakar.csengg@gmail.com>
Cc: Conor Dooley <conor.dooley@microchip.com>,
Arnd Bergmann <arnd@arndb.de>,
Geert Uytterhoeven <geert+renesas@glider.be>,
Heiko Stuebner <heiko@sntech.de>, Guo Ren <guoren@kernel.org>,
Andrew Jones <ajones@ventanamicro.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Samuel Holland <samuel@sholland.org>,
linux-riscv@lists.infradead.org, Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-renesas-soc@vger.kernel.org,
Biju Das <biju.das.jz@bp.renesas.com>,
Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Subject: Re: [PATCH v8 5/7] cache: Add L2 cache management for Andes AX45MP RISC-V core
Date: Thu, 13 Apr 2023 19:46:47 +0100 [thread overview]
Message-ID: <20230413-staunch-superman-e71fd3303176@spud> (raw)
In-Reply-To: <CA+V-a8uksWMihUadYc_dCoef7vaC5ncOicX0oGpSP9HRnHgScw@mail.gmail.com>
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On Thu, Apr 13, 2023 at 07:26:02PM +0100, Lad, Prabhakar wrote:
> > The simplest solution may to just be making the erratum depend on 64BIT?
> >
> I dont think this will work, as pmem.c is compiled unconditionally.
That'll teach me to write things like this first thing in the morning.
I somehow got it in my head that the alternative would be removed by the
preprocessor if it was not enabled. After testing it, that's not what
happened.
My excuse is being tired from the gym and insufficiently caffeinated,
sorry!
> Is
> dma-noncoherent.c also valid for RISCV-32? If not then we can make
> pmem.c compile conditionally if DMA non-coherenet is enabled and we
> make DMA non-coherent depend on 64bit.
Could you drop the {s,l}d in exchange for {s,l}w instead, or am I
progressing even further into braino territory?
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next prev parent reply other threads:[~2023-04-13 18:47 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-04-12 11:08 [PATCH v8 0/7] Add non-coherent DMA support for AX45MP Prabhakar
2023-04-12 11:08 ` [PATCH v8 1/7] riscv: asm: alternative-macros: Introduce ALTERNATIVE_3() macro Prabhakar
2023-04-12 11:08 ` [PATCH v8 2/7] riscv: asm: vendorid_list: Add Andes Technology to the vendors list Prabhakar
2023-04-17 8:52 ` Geert Uytterhoeven
2023-04-12 11:08 ` [PATCH v8 3/7] riscv: errata: Add Andes alternative ports Prabhakar
2023-04-12 11:08 ` [PATCH v8 4/7] dt-bindings: cache: andestech,ax45mp-cache: Add DT binding documentation for L2 cache controller Prabhakar
2023-04-12 11:08 ` [PATCH v8 5/7] cache: Add L2 cache management for Andes AX45MP RISC-V core Prabhakar
2023-04-12 20:25 ` Conor Dooley
2023-04-13 7:06 ` Conor Dooley
2023-04-13 18:26 ` Lad, Prabhakar
2023-04-13 18:46 ` Conor Dooley [this message]
2023-04-13 21:06 ` Lad, Prabhakar
2023-04-14 18:59 ` Lad, Prabhakar
2023-04-12 11:08 ` [PATCH v8 6/7] riscv: errata: Hookup the Andes AX45MP non-coherent handling Prabhakar
2023-04-12 20:29 ` Conor Dooley
2023-04-12 11:09 ` [PATCH v8 7/7] soc: renesas: Kconfig: Select the required configs for RZ/Five SoC Prabhakar
2023-04-12 20:32 ` [PATCH v8 0/7] Add non-coherent DMA support for AX45MP Conor Dooley
2023-04-17 6:53 ` Christoph Hellwig
2023-04-19 15:59 ` Palmer Dabbelt
2023-04-20 6:09 ` Christoph Hellwig
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