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From: Marc Kleine-Budde <mkl@pengutronix.de>
To: Oliver Hartkopp <socketcan@hartkopp.net>
Cc: Judith Mendez <jm@ti.com>,
	Chandrasekar Ramakrishnan <rcsekar@samsung.com>,
	Nishanth Menon <nm@ti.com>, Vignesh Raghavendra <vigneshr@ti.com>,
	Andrew Davis <afd@ti.com>,
	Wolfgang Grandegger <wg@grandegger.com>,
	Rob Herring <robh+dt@kernel.org>,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
	linux-can@vger.kernel.org, linux-kernel@vger.kernel.org,
	devicetree@vger.kernel.org, netdev@vger.kernel.org,
	Schuyler Patton <spatton@ti.com>
Subject: Re: [RFC PATCH 5/5] can: m_can: Add hrtimer to generate software interrupt
Date: Sun, 16 Apr 2023 17:35:33 +0200	[thread overview]
Message-ID: <20230416-failing-washbasin-e4fa5caea267-mkl@pengutronix.de> (raw)
In-Reply-To: <4a6c66eb-2ccf-fc42-a6fc-9f411861fcef@hartkopp.net>

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On 16.04.2023 14:33:11, Oliver Hartkopp wrote:
> 
> 
> On 4/14/23 20:20, Marc Kleine-Budde wrote:
> > On 13.04.2023 17:30:51, Judith Mendez wrote:
> > > Add a hrtimer to MCAN struct. Each MCAN will have its own
> > > hrtimer instantiated if there is no hardware interrupt found.
> > > 
> > > The hrtimer will generate a software interrupt every 1 ms. In
> > 
> > Are you sure about the 1ms?

I had the 5ms that are actually used in the code in mind. But this is a
good calculation.

> The "shortest" 11 bit CAN ID CAN frame is a Classical CAN frame with DLC = 0
> and 1 Mbit/s (arbitration) bitrate. This should be 48 bits @1Mbit => ~50
> usecs
> 
> So it should be something about
> 
>     50 usecs * (FIFO queue len - 2)

Where does the "2" come from?

> if there is some FIFO involved, right?

Yes, the mcan core has a FIFO. In the current driver the FIFO
configuration is done via device tree and fixed after that. And I don't
know the size of the available RAM in the mcan IP core on that TI SoC.

Marc

-- 
Pengutronix e.K.                 | Marc Kleine-Budde          |
Embedded Linux                   | https://www.pengutronix.de |
Vertretung Nürnberg              | Phone: +49-5121-206917-129 |
Amtsgericht Hildesheim, HRA 2686 | Fax:   +49-5121-206917-9   |

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  reply	other threads:[~2023-04-16 15:35 UTC|newest]

Thread overview: 31+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-04-13 22:30 [RFC PATCH 0/5] Enable multiple MCAN on AM62x Judith Mendez
2023-04-13 22:30 ` [RFC PATCH 1/5] arm64: dts: ti: Add AM62x MCAN MAIN domain transceiver overlay Judith Mendez
2023-04-13 22:30 ` [RFC PATCH 2/5] arm64: defconfig: Enable MCAN driver Judith Mendez
2023-04-13 22:30 ` [RFC PATCH 3/5] dt-binding: can: m_can: Remove required interrupt attributes Judith Mendez
2023-04-14  8:00   ` Krzysztof Kozlowski
2023-04-13 22:30 ` [RFC PATCH 4/5] arm64: dts: ti: Enable multiple MCAN for AM62x in MCU MCAN overlay Judith Mendez
2023-04-14  8:01   ` Krzysztof Kozlowski
2023-04-14 18:29     ` Nishanth Menon
2023-04-14 20:44       ` Krzysztof Kozlowski
2023-04-14 22:11         ` Nishanth Menon
2023-04-19 15:54           ` Mendez, Judith
2023-04-13 22:30 ` [RFC PATCH 5/5] can: m_can: Add hrtimer to generate software interrupt Judith Mendez
2023-04-14 18:20   ` Marc Kleine-Budde
2023-04-16 12:33     ` Oliver Hartkopp
2023-04-16 15:35       ` Marc Kleine-Budde [this message]
2023-04-16 19:46         ` Oliver Hartkopp
2023-04-17  7:26           ` Marc Kleine-Budde
2023-04-17 17:34             ` Oliver Hartkopp
2023-04-17 19:26               ` Marc Kleine-Budde
2023-04-18 20:59                 ` Mendez, Judith
2023-04-19  6:13                   ` Marc Kleine-Budde
2023-04-19 14:38                     ` Mendez, Judith
2023-04-19 19:06     ` Mendez, Judith
2023-04-14  6:12 ` [RFC PATCH 0/5] Enable multiple MCAN on AM62x Vignesh Raghavendra
2023-04-19 15:12   ` Mendez, Judith
2023-04-14 17:49 ` Marc Kleine-Budde
2023-04-18 16:15   ` Mendez, Judith
2023-04-19  6:10     ` Marc Kleine-Budde
2023-04-19 20:40       ` Mendez, Judith
2023-04-20  9:36         ` Marc Kleine-Budde
2023-04-20 15:17           ` Mendez, Judith

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