From: David Yang <mmyangfl@gmail.com>
To: linux-clk@vger.kernel.org
Cc: devicetree@vger.kernel.org, David Yang <mmyangfl@gmail.com>,
Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>,
Philipp Zabel <p.zabel@pengutronix.de>,
linux-kernel@vger.kernel.org
Subject: [PATCH v2 4/4] clk: gate: Add DT binding
Date: Mon, 17 Apr 2023 01:33:02 +0800 [thread overview]
Message-ID: <20230416173302.1185683-5-mmyangfl@gmail.com> (raw)
In-Reply-To: <20230416173302.1185683-1-mmyangfl@gmail.com>
Add DT binding for gate clock as "gate-clock".
Signed-off-by: David Yang <mmyangfl@gmail.com>
---
drivers/clk/clk-gate.c | 81 ++++++++++++++++++++++++++++++++++++++++++
1 file changed, 81 insertions(+)
diff --git a/drivers/clk/clk-gate.c b/drivers/clk/clk-gate.c
index 64283807600b..a70df4a2a9a7 100644
--- a/drivers/clk/clk-gate.c
+++ b/drivers/clk/clk-gate.c
@@ -12,8 +12,11 @@
#include <linux/slab.h>
#include <linux/io.h>
#include <linux/err.h>
+#include <linux/platform_device.h>
#include <linux/string.h>
+#include "clk-of.h"
+
/**
* DOC: basic gatable clock which can gate and ungate it's ouput
*
@@ -257,3 +260,81 @@ struct clk_hw *__devm_clk_hw_register_gate(struct device *dev,
return hw;
}
EXPORT_SYMBOL_GPL(__devm_clk_hw_register_gate);
+
+#if IS_ENABLED(CONFIG_OF)
+static const struct of_clk_flag of_clk_gate_flags[] = {
+ { "set-to-disable", CLK_GATE_SET_TO_DISABLE },
+ { "hiword-mask", CLK_GATE_HIWORD_MASK },
+ { "big-endian", CLK_GATE_BIG_ENDIAN },
+ { }
+};
+
+static int of_clk_gate_setup(struct device_node *np)
+{
+ struct of_clk_ctrl *ctrl = np->parent->data;
+ const char *name;
+ void __iomem *reg;
+ u32 bit_idx;
+
+ const char *property;
+ struct clk_hw *hw;
+ int ret;
+
+ reg = of_clk_get_reg(np);
+ if (!reg)
+ return -ENOMEM;
+ name = of_clk_get_name(np);
+ if (!name)
+ return -EINVAL;
+
+ property = "bits";
+ if (of_property_read_u32(np, property, &bit_idx))
+ goto err_property;
+
+ hw = __clk_hw_register_gate(NULL, np, name,
+ of_clk_get_parent_name(np, 0),
+ NULL, NULL, of_clk_get_flags(np, NULL),
+ reg, bit_idx,
+ of_clk_get_flags(np, of_clk_gate_flags),
+ &ctrl->lock);
+ if (IS_ERR(hw))
+ return PTR_ERR(hw);
+
+ ret = of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw);
+ if (ret)
+ goto err_register;
+
+ np->data = hw;
+ return 0;
+
+err_register:
+ clk_hw_unregister(hw);
+ return ret;
+
+err_property:
+ pr_err("%s: clock %s missing required property \"%s\"\n",
+ __func__, name, property);
+ return -EINVAL;
+}
+
+static void __init of_clk_gate_init(struct device_node *np)
+{
+ of_clk_gate_setup(np);
+}
+CLK_OF_DECLARE(of_clk_gate, "gate-clock", of_clk_gate_init);
+
+static const struct of_device_id of_clk_gate_ids[] = {
+ { .compatible = "gate-clock", .data = of_clk_gate_setup },
+ { }
+};
+
+static struct platform_driver of_clk_gate_driver = {
+ .driver = {
+ .name = "clk_gate",
+ .of_match_table = of_clk_gate_ids,
+ },
+ .probe = of_clk_probe,
+ .remove = of_clk_remove,
+};
+builtin_platform_driver(of_clk_gate_driver);
+#endif
--
2.39.2
prev parent reply other threads:[~2023-04-16 17:35 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-04-16 17:32 [PATCH v2 0/4] clk: Add basic register clock controller David Yang
2023-04-16 17:32 ` [PATCH v2 1/4] dt-bindings: clock: Add simple-clock-controller David Yang
2023-04-16 17:38 ` Krzysztof Kozlowski
2023-04-16 18:22 ` Yangfl
2023-04-16 18:27 ` Krzysztof Kozlowski
2023-04-17 18:08 ` Yangfl
2023-04-16 17:32 ` [PATCH v2 2/4] clk: Add simple clock controller David Yang
2023-04-16 17:33 ` [PATCH v2 3/4] dt-bindings: clock: Add gate-clock David Yang
2023-04-16 17:41 ` Krzysztof Kozlowski
2023-04-16 18:28 ` Yangfl
2023-04-16 18:31 ` Krzysztof Kozlowski
2023-04-16 17:33 ` David Yang [this message]
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