* [PATCH v2 0/3] Add JH7110 cpufreq support
@ 2023-04-17 6:39 Mason Huo
2023-04-17 6:39 ` [PATCH v2 1/3] riscv: dts: starfive: Enable axp15060 pmic for cpufreq Mason Huo
` (2 more replies)
0 siblings, 3 replies; 6+ messages in thread
From: Mason Huo @ 2023-04-17 6:39 UTC (permalink / raw)
To: Rafael J. Wysocki, Viresh Kumar, Emil Renner Berthing,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Paul Walmsley,
Palmer Dabbelt, Albert Ou
Cc: Shengyu Qu, linux-pm, devicetree, linux-kernel, linux-riscv,
Mason Huo
The StarFive JH7110 SoC has four RISC-V cores,
and it supports up to 4 cpu frequency loads.
This patchset adds the compatible strings into the allowlist
for supporting the generic cpufreq driver on JH7110 SoC.
Also, it enables the axp15060 pmic for the cpu power source.
The series has been tested on the VisionFive 2 boards which
are equipped with JH7110 SoC and axp15060 pmic.
This patchset is based on v6.3-rc4 with these patches applied:
[1] ("Basic clock, reset & device tree support for StarFive JH7110 RISC-V SoC")
https://lore.kernel.org/all/20230401111934.130844-1-hal.feng@starfivetech.com/
[2] ("Add X-Powers AXP15060 PMIC support")
https://lore.kernel.org/all/TY3P286MB2611A814E580C96DC6F187B798969@TY3P286MB2611.JPNP286.PROD.OUTLOOK.COM/
Changes since v1:
- Fix dts node naming issues.
- Move clock properties of cpu node from <board>.dtsi to <soc>.dtsi.
- Follow the alphabetical order to place the cpufreq dt allowlist.
---
v1: https://lore.kernel.org/all/20230411083257.16155-1-mason.huo@starfivetech.com/
Mason Huo (3):
riscv: dts: starfive: Enable axp15060 pmic for cpufreq
cpufreq: dt-platdev: Add JH7110 SOC to the allowlist
riscv: dts: starfive: Add cpu scaling for JH7110 SoC
.../jh7110-starfive-visionfive-2.dtsi | 31 +++++++++++++++++
arch/riscv/boot/dts/starfive/jh7110.dtsi | 33 +++++++++++++++++++
drivers/cpufreq/cpufreq-dt-platdev.c | 2 ++
3 files changed, 66 insertions(+)
base-commit: 197b6b60ae7bc51dd0814953c562833143b292aa
prerequisite-patch-id: 388b8adbb0fe2daf4d07a21eafd4f1bd50ce2403
prerequisite-patch-id: 1117ecaa40a353c667b71802ab34ecf9568d8bb2
prerequisite-patch-id: b00c6b21fbd0353d88b7c9b09093ba30b765f45b
prerequisite-patch-id: 08ec9027e8a5c6fdf201726833168c7464a9b94d
prerequisite-patch-id: fb5120248e48fe1faf053ae0b490c92507ec2b44
prerequisite-patch-id: 4b93d8d590b0a2abe7b4be5287232c494c35be4a
prerequisite-patch-id: 89f049f951e5acf75aab92541992f816fd0acc0d
prerequisite-patch-id: c09c4c68af017b8e5c97b515cb50b70c18a2e705
prerequisite-patch-id: 0df8ccb0e848c2df4c2da95026494bebecede92d
prerequisite-patch-id: 315303931e4b6499de7127a88113763f86e97e16
prerequisite-patch-id: 40cb8212ddb024c20593f73d8b87d9894877e172
prerequisite-patch-id: a1673a9e9f19d6fab5a51abb721e54e36636f067
prerequisite-patch-id: d57cc467fb036241b9276320ff076c4a30d376d6
prerequisite-patch-id: 6e563d68bc5dbf951d4ced17897f9cc4d56169fe
prerequisite-patch-id: 61ec2caa21fd0fc60e57977f7d16d3f72b135745
prerequisite-patch-id: 1387a7e87b446329dfc21f3e575ceae7ebcf954c
prerequisite-patch-id: 258ea5f9b8bf41b6981345dcc81795f25865d38f
prerequisite-patch-id: 8b6f2c9660c0ac0ee4e73e4c21aca8e6b75e81b9
prerequisite-patch-id: dbb0c0151b8bdf093e6ce79fd2fe3f60791a6e0b
prerequisite-patch-id: 9007c8610fdcd387592475949864edde874c20a2
prerequisite-patch-id: d57e95d31686772abc4c4d5aa1cadc344dc293cd
prerequisite-patch-id: 0a0ac5a8a90655b415f6b62e324f3db083cdaaee
prerequisite-patch-id: 4c285d814aa74358a697714eac4415f0bb32bdb3
prerequisite-patch-id: 62735ba4fc7ec7c4435b1b6c1e69abb2345cb0e8
prerequisite-patch-id: 7f653d6f4aebf56544aca906c2719f9d80cb1bb3
prerequisite-patch-id: 1936b8e48a4cb9b0fa4440f7ad25bf267beeeebf
prerequisite-patch-id: 5b39a469bff8f11ed582118ca4c456ba8ebcdcd9
--
2.39.2
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH v2 1/3] riscv: dts: starfive: Enable axp15060 pmic for cpufreq
2023-04-17 6:39 [PATCH v2 0/3] Add JH7110 cpufreq support Mason Huo
@ 2023-04-17 6:39 ` Mason Huo
2023-04-17 6:39 ` [PATCH v2 2/3] cpufreq: dt-platdev: Add JH7110 SOC to the allowlist Mason Huo
2023-04-17 6:39 ` [PATCH v2 3/3] riscv: dts: starfive: Add cpu scaling for JH7110 SoC Mason Huo
2 siblings, 0 replies; 6+ messages in thread
From: Mason Huo @ 2023-04-17 6:39 UTC (permalink / raw)
To: Rafael J. Wysocki, Viresh Kumar, Emil Renner Berthing,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Paul Walmsley,
Palmer Dabbelt, Albert Ou
Cc: Shengyu Qu, linux-pm, devicetree, linux-kernel, linux-riscv,
Mason Huo
The VisionFive 2 board has an embedded pmic axp15060,
which supports the cpu DVFS through the dcdc2 regulator.
This patch enables axp15060 pmic and configs the dcdc2.
Signed-off-by: Mason Huo <mason.huo@starfivetech.com>
---
.../dts/starfive/jh7110-starfive-visionfive-2.dtsi | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
index 2a6d81609284..cca1c8040801 100644
--- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
@@ -114,6 +114,20 @@ &i2c5 {
pinctrl-names = "default";
pinctrl-0 = <&i2c5_pins>;
status = "okay";
+
+ axp15060: pmic@36 {
+ compatible = "x-powers,axp15060";
+ reg = <0x36>;
+
+ regulators {
+ vdd_cpu: dcdc2 {
+ regulator-always-on;
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <1540000>;
+ regulator-name = "vdd-cpu";
+ };
+ };
+ };
};
&i2c6 {
--
2.39.2
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH v2 2/3] cpufreq: dt-platdev: Add JH7110 SOC to the allowlist
2023-04-17 6:39 [PATCH v2 0/3] Add JH7110 cpufreq support Mason Huo
2023-04-17 6:39 ` [PATCH v2 1/3] riscv: dts: starfive: Enable axp15060 pmic for cpufreq Mason Huo
@ 2023-04-17 6:39 ` Mason Huo
2023-04-17 6:39 ` [PATCH v2 3/3] riscv: dts: starfive: Add cpu scaling for JH7110 SoC Mason Huo
2 siblings, 0 replies; 6+ messages in thread
From: Mason Huo @ 2023-04-17 6:39 UTC (permalink / raw)
To: Rafael J. Wysocki, Viresh Kumar, Emil Renner Berthing,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Paul Walmsley,
Palmer Dabbelt, Albert Ou
Cc: Shengyu Qu, linux-pm, devicetree, linux-kernel, linux-riscv,
Mason Huo
Add the compatible strings for supporting the generic
cpufreq driver on the StarFive JH7110 SoC.
Signed-off-by: Mason Huo <mason.huo@starfivetech.com>
---
drivers/cpufreq/cpufreq-dt-platdev.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/cpufreq/cpufreq-dt-platdev.c b/drivers/cpufreq/cpufreq-dt-platdev.c
index e85703651098..79537d0ed7cf 100644
--- a/drivers/cpufreq/cpufreq-dt-platdev.c
+++ b/drivers/cpufreq/cpufreq-dt-platdev.c
@@ -86,6 +86,8 @@ static const struct of_device_id allowlist[] __initconst = {
{ .compatible = "st-ericsson,u9500", },
{ .compatible = "st-ericsson,u9540", },
+ { .compatible = "starfive,jh7110", },
+
{ .compatible = "ti,omap2", },
{ .compatible = "ti,omap4", },
{ .compatible = "ti,omap5", },
--
2.39.2
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH v2 3/3] riscv: dts: starfive: Add cpu scaling for JH7110 SoC
2023-04-17 6:39 [PATCH v2 0/3] Add JH7110 cpufreq support Mason Huo
2023-04-17 6:39 ` [PATCH v2 1/3] riscv: dts: starfive: Enable axp15060 pmic for cpufreq Mason Huo
2023-04-17 6:39 ` [PATCH v2 2/3] cpufreq: dt-platdev: Add JH7110 SOC to the allowlist Mason Huo
@ 2023-04-17 6:39 ` Mason Huo
2023-04-18 17:28 ` Conor Dooley
2 siblings, 1 reply; 6+ messages in thread
From: Mason Huo @ 2023-04-17 6:39 UTC (permalink / raw)
To: Rafael J. Wysocki, Viresh Kumar, Emil Renner Berthing,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Paul Walmsley,
Palmer Dabbelt, Albert Ou
Cc: Shengyu Qu, linux-pm, devicetree, linux-kernel, linux-riscv,
Mason Huo
Add the operating-points-v2 to support cpu scaling on StarFive JH7110 SoC.
It supports up to 4 cpu frequency loads.
Signed-off-by: Mason Huo <mason.huo@starfivetech.com>
---
.../jh7110-starfive-visionfive-2.dtsi | 17 ++++++++++
arch/riscv/boot/dts/starfive/jh7110.dtsi | 33 +++++++++++++++++++
2 files changed, 50 insertions(+)
diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
index cca1c8040801..b25e6d68ce53 100644
--- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
@@ -227,3 +227,20 @@ &uart0 {
pinctrl-0 = <&uart0_pins>;
status = "okay";
};
+
+&U74_1 {
+ cpu-supply = <&vdd_cpu>;
+};
+
+&U74_2 {
+ cpu-supply = <&vdd_cpu>;
+};
+
+&U74_3 {
+ cpu-supply = <&vdd_cpu>;
+};
+
+&U74_4 {
+ cpu-supply = <&vdd_cpu>;
+};
+
diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi
index 4c5fdb905da8..7eef88d2cedb 100644
--- a/arch/riscv/boot/dts/starfive/jh7110.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
@@ -53,6 +53,9 @@ U74_1: cpu@1 {
next-level-cache = <&ccache>;
riscv,isa = "rv64imafdc_zba_zbb";
tlb-split;
+ operating-points-v2 = <&cpu_opp>;
+ clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>;
+ clock-names = "cpu";
cpu1_intc: interrupt-controller {
compatible = "riscv,cpu-intc";
@@ -79,6 +82,9 @@ U74_2: cpu@2 {
next-level-cache = <&ccache>;
riscv,isa = "rv64imafdc_zba_zbb";
tlb-split;
+ operating-points-v2 = <&cpu_opp>;
+ clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>;
+ clock-names = "cpu";
cpu2_intc: interrupt-controller {
compatible = "riscv,cpu-intc";
@@ -105,6 +111,9 @@ U74_3: cpu@3 {
next-level-cache = <&ccache>;
riscv,isa = "rv64imafdc_zba_zbb";
tlb-split;
+ operating-points-v2 = <&cpu_opp>;
+ clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>;
+ clock-names = "cpu";
cpu3_intc: interrupt-controller {
compatible = "riscv,cpu-intc";
@@ -131,6 +140,9 @@ U74_4: cpu@4 {
next-level-cache = <&ccache>;
riscv,isa = "rv64imafdc_zba_zbb";
tlb-split;
+ operating-points-v2 = <&cpu_opp>;
+ clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>;
+ clock-names = "cpu";
cpu4_intc: interrupt-controller {
compatible = "riscv,cpu-intc";
@@ -164,6 +176,27 @@ core4 {
};
};
+ cpu_opp: opp-table-0 {
+ compatible = "operating-points-v2";
+ opp-shared;
+ opp-375000000 {
+ opp-hz = /bits/ 64 <375000000>;
+ opp-microvolt = <800000>;
+ };
+ opp-500000000 {
+ opp-hz = /bits/ 64 <500000000>;
+ opp-microvolt = <800000>;
+ };
+ opp-750000000 {
+ opp-hz = /bits/ 64 <750000000>;
+ opp-microvolt = <800000>;
+ };
+ opp-1500000000 {
+ opp-hz = /bits/ 64 <1500000000>;
+ opp-microvolt = <1040000>;
+ };
+ };
+
gmac0_rgmii_rxin: gmac0-rgmii-rxin-clock {
compatible = "fixed-clock";
clock-output-names = "gmac0_rgmii_rxin";
--
2.39.2
^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH v2 3/3] riscv: dts: starfive: Add cpu scaling for JH7110 SoC
2023-04-17 6:39 ` [PATCH v2 3/3] riscv: dts: starfive: Add cpu scaling for JH7110 SoC Mason Huo
@ 2023-04-18 17:28 ` Conor Dooley
2023-04-20 7:10 ` Mason Huo
0 siblings, 1 reply; 6+ messages in thread
From: Conor Dooley @ 2023-04-18 17:28 UTC (permalink / raw)
To: Mason Huo
Cc: Rafael J. Wysocki, Viresh Kumar, Emil Renner Berthing,
Rob Herring, Krzysztof Kozlowski, Paul Walmsley, Palmer Dabbelt,
Albert Ou, Shengyu Qu, linux-pm, devicetree, linux-kernel,
linux-riscv
[-- Attachment #1: Type: text/plain, Size: 1332 bytes --]
Hey Mason,
Just one minor comment in passing..
On Mon, Apr 17, 2023 at 02:39:42PM +0800, Mason Huo wrote:
> Add the operating-points-v2 to support cpu scaling on StarFive JH7110 SoC.
> It supports up to 4 cpu frequency loads.
>
> Signed-off-by: Mason Huo <mason.huo@starfivetech.com>
> ---
> .../jh7110-starfive-visionfive-2.dtsi | 17 ++++++++++
> arch/riscv/boot/dts/starfive/jh7110.dtsi | 33 +++++++++++++++++++
> 2 files changed, 50 insertions(+)
>
> diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
> index cca1c8040801..b25e6d68ce53 100644
> --- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
> +++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
> @@ -227,3 +227,20 @@ &uart0 {
> pinctrl-0 = <&uart0_pins>;
> status = "okay";
> };
> +
> +&U74_1 {
> + cpu-supply = <&vdd_cpu>;
> +};
> +
> +&U74_2 {
> + cpu-supply = <&vdd_cpu>;
> +};
> +
> +&U74_3 {
> + cpu-supply = <&vdd_cpu>;
> +};
> +
> +&U74_4 {
> + cpu-supply = <&vdd_cpu>;
> +};
> +
Applying: riscv: dts: starfive: Add cpu scaling for JH7110 SoC
/stuff/linux/.git/rebase-apply/patch:30: new blank line at EOF.
+
warning: 1 line adds whitespace errors.
Cheers,
Conor.
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH v2 3/3] riscv: dts: starfive: Add cpu scaling for JH7110 SoC
2023-04-18 17:28 ` Conor Dooley
@ 2023-04-20 7:10 ` Mason Huo
0 siblings, 0 replies; 6+ messages in thread
From: Mason Huo @ 2023-04-20 7:10 UTC (permalink / raw)
To: Conor Dooley
Cc: Rafael J. Wysocki, Viresh Kumar, Emil Renner Berthing,
Rob Herring, Krzysztof Kozlowski, Paul Walmsley, Palmer Dabbelt,
Albert Ou, Shengyu Qu, linux-pm, devicetree, linux-kernel,
linux-riscv
On 2023/4/19 1:28, Conor Dooley wrote:
> Hey Mason,
>
> Just one minor comment in passing..
>
> On Mon, Apr 17, 2023 at 02:39:42PM +0800, Mason Huo wrote:
>> Add the operating-points-v2 to support cpu scaling on StarFive JH7110 SoC.
>> It supports up to 4 cpu frequency loads.
>>
>> Signed-off-by: Mason Huo <mason.huo@starfivetech.com>
>> ---
>> .../jh7110-starfive-visionfive-2.dtsi | 17 ++++++++++
>> arch/riscv/boot/dts/starfive/jh7110.dtsi | 33 +++++++++++++++++++
>> 2 files changed, 50 insertions(+)
>>
>> diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
>> index cca1c8040801..b25e6d68ce53 100644
>> --- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
>> +++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
>> @@ -227,3 +227,20 @@ &uart0 {
>> pinctrl-0 = <&uart0_pins>;
>> status = "okay";
>> };
>> +
>> +&U74_1 {
>> + cpu-supply = <&vdd_cpu>;
>> +};
>> +
>> +&U74_2 {
>> + cpu-supply = <&vdd_cpu>;
>> +};
>> +
>> +&U74_3 {
>> + cpu-supply = <&vdd_cpu>;
>> +};
>> +
>> +&U74_4 {
>> + cpu-supply = <&vdd_cpu>;
>> +};
>> +
>
> Applying: riscv: dts: starfive: Add cpu scaling for JH7110 SoC
> /stuff/linux/.git/rebase-apply/patch:30: new blank line at EOF.
> +
> warning: 1 line adds whitespace errors.
>
> Cheers,
> Conor.
>
Hi Conor,
Will fix it soon.
Thanks
Mason
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2023-04-20 7:10 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz follow: Atom feed
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2023-04-17 6:39 [PATCH v2 0/3] Add JH7110 cpufreq support Mason Huo
2023-04-17 6:39 ` [PATCH v2 1/3] riscv: dts: starfive: Enable axp15060 pmic for cpufreq Mason Huo
2023-04-17 6:39 ` [PATCH v2 2/3] cpufreq: dt-platdev: Add JH7110 SOC to the allowlist Mason Huo
2023-04-17 6:39 ` [PATCH v2 3/3] riscv: dts: starfive: Add cpu scaling for JH7110 SoC Mason Huo
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2023-04-20 7:10 ` Mason Huo
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