* [PATCH v2 1/3] riscv: dts: starfive: Enable axp15060 pmic for cpufreq
2023-04-17 6:39 [PATCH v2 0/3] Add JH7110 cpufreq support Mason Huo
@ 2023-04-17 6:39 ` Mason Huo
2023-04-17 6:39 ` [PATCH v2 2/3] cpufreq: dt-platdev: Add JH7110 SOC to the allowlist Mason Huo
2023-04-17 6:39 ` [PATCH v2 3/3] riscv: dts: starfive: Add cpu scaling for JH7110 SoC Mason Huo
2 siblings, 0 replies; 6+ messages in thread
From: Mason Huo @ 2023-04-17 6:39 UTC (permalink / raw)
To: Rafael J. Wysocki, Viresh Kumar, Emil Renner Berthing,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Paul Walmsley,
Palmer Dabbelt, Albert Ou
Cc: Shengyu Qu, linux-pm, devicetree, linux-kernel, linux-riscv,
Mason Huo
The VisionFive 2 board has an embedded pmic axp15060,
which supports the cpu DVFS through the dcdc2 regulator.
This patch enables axp15060 pmic and configs the dcdc2.
Signed-off-by: Mason Huo <mason.huo@starfivetech.com>
---
.../dts/starfive/jh7110-starfive-visionfive-2.dtsi | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
index 2a6d81609284..cca1c8040801 100644
--- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
@@ -114,6 +114,20 @@ &i2c5 {
pinctrl-names = "default";
pinctrl-0 = <&i2c5_pins>;
status = "okay";
+
+ axp15060: pmic@36 {
+ compatible = "x-powers,axp15060";
+ reg = <0x36>;
+
+ regulators {
+ vdd_cpu: dcdc2 {
+ regulator-always-on;
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <1540000>;
+ regulator-name = "vdd-cpu";
+ };
+ };
+ };
};
&i2c6 {
--
2.39.2
^ permalink raw reply related [flat|nested] 6+ messages in thread* [PATCH v2 2/3] cpufreq: dt-platdev: Add JH7110 SOC to the allowlist
2023-04-17 6:39 [PATCH v2 0/3] Add JH7110 cpufreq support Mason Huo
2023-04-17 6:39 ` [PATCH v2 1/3] riscv: dts: starfive: Enable axp15060 pmic for cpufreq Mason Huo
@ 2023-04-17 6:39 ` Mason Huo
2023-04-17 6:39 ` [PATCH v2 3/3] riscv: dts: starfive: Add cpu scaling for JH7110 SoC Mason Huo
2 siblings, 0 replies; 6+ messages in thread
From: Mason Huo @ 2023-04-17 6:39 UTC (permalink / raw)
To: Rafael J. Wysocki, Viresh Kumar, Emil Renner Berthing,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Paul Walmsley,
Palmer Dabbelt, Albert Ou
Cc: Shengyu Qu, linux-pm, devicetree, linux-kernel, linux-riscv,
Mason Huo
Add the compatible strings for supporting the generic
cpufreq driver on the StarFive JH7110 SoC.
Signed-off-by: Mason Huo <mason.huo@starfivetech.com>
---
drivers/cpufreq/cpufreq-dt-platdev.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/cpufreq/cpufreq-dt-platdev.c b/drivers/cpufreq/cpufreq-dt-platdev.c
index e85703651098..79537d0ed7cf 100644
--- a/drivers/cpufreq/cpufreq-dt-platdev.c
+++ b/drivers/cpufreq/cpufreq-dt-platdev.c
@@ -86,6 +86,8 @@ static const struct of_device_id allowlist[] __initconst = {
{ .compatible = "st-ericsson,u9500", },
{ .compatible = "st-ericsson,u9540", },
+ { .compatible = "starfive,jh7110", },
+
{ .compatible = "ti,omap2", },
{ .compatible = "ti,omap4", },
{ .compatible = "ti,omap5", },
--
2.39.2
^ permalink raw reply related [flat|nested] 6+ messages in thread* [PATCH v2 3/3] riscv: dts: starfive: Add cpu scaling for JH7110 SoC
2023-04-17 6:39 [PATCH v2 0/3] Add JH7110 cpufreq support Mason Huo
2023-04-17 6:39 ` [PATCH v2 1/3] riscv: dts: starfive: Enable axp15060 pmic for cpufreq Mason Huo
2023-04-17 6:39 ` [PATCH v2 2/3] cpufreq: dt-platdev: Add JH7110 SOC to the allowlist Mason Huo
@ 2023-04-17 6:39 ` Mason Huo
2023-04-18 17:28 ` Conor Dooley
2 siblings, 1 reply; 6+ messages in thread
From: Mason Huo @ 2023-04-17 6:39 UTC (permalink / raw)
To: Rafael J. Wysocki, Viresh Kumar, Emil Renner Berthing,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Paul Walmsley,
Palmer Dabbelt, Albert Ou
Cc: Shengyu Qu, linux-pm, devicetree, linux-kernel, linux-riscv,
Mason Huo
Add the operating-points-v2 to support cpu scaling on StarFive JH7110 SoC.
It supports up to 4 cpu frequency loads.
Signed-off-by: Mason Huo <mason.huo@starfivetech.com>
---
.../jh7110-starfive-visionfive-2.dtsi | 17 ++++++++++
arch/riscv/boot/dts/starfive/jh7110.dtsi | 33 +++++++++++++++++++
2 files changed, 50 insertions(+)
diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
index cca1c8040801..b25e6d68ce53 100644
--- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
@@ -227,3 +227,20 @@ &uart0 {
pinctrl-0 = <&uart0_pins>;
status = "okay";
};
+
+&U74_1 {
+ cpu-supply = <&vdd_cpu>;
+};
+
+&U74_2 {
+ cpu-supply = <&vdd_cpu>;
+};
+
+&U74_3 {
+ cpu-supply = <&vdd_cpu>;
+};
+
+&U74_4 {
+ cpu-supply = <&vdd_cpu>;
+};
+
diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi
index 4c5fdb905da8..7eef88d2cedb 100644
--- a/arch/riscv/boot/dts/starfive/jh7110.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
@@ -53,6 +53,9 @@ U74_1: cpu@1 {
next-level-cache = <&ccache>;
riscv,isa = "rv64imafdc_zba_zbb";
tlb-split;
+ operating-points-v2 = <&cpu_opp>;
+ clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>;
+ clock-names = "cpu";
cpu1_intc: interrupt-controller {
compatible = "riscv,cpu-intc";
@@ -79,6 +82,9 @@ U74_2: cpu@2 {
next-level-cache = <&ccache>;
riscv,isa = "rv64imafdc_zba_zbb";
tlb-split;
+ operating-points-v2 = <&cpu_opp>;
+ clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>;
+ clock-names = "cpu";
cpu2_intc: interrupt-controller {
compatible = "riscv,cpu-intc";
@@ -105,6 +111,9 @@ U74_3: cpu@3 {
next-level-cache = <&ccache>;
riscv,isa = "rv64imafdc_zba_zbb";
tlb-split;
+ operating-points-v2 = <&cpu_opp>;
+ clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>;
+ clock-names = "cpu";
cpu3_intc: interrupt-controller {
compatible = "riscv,cpu-intc";
@@ -131,6 +140,9 @@ U74_4: cpu@4 {
next-level-cache = <&ccache>;
riscv,isa = "rv64imafdc_zba_zbb";
tlb-split;
+ operating-points-v2 = <&cpu_opp>;
+ clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>;
+ clock-names = "cpu";
cpu4_intc: interrupt-controller {
compatible = "riscv,cpu-intc";
@@ -164,6 +176,27 @@ core4 {
};
};
+ cpu_opp: opp-table-0 {
+ compatible = "operating-points-v2";
+ opp-shared;
+ opp-375000000 {
+ opp-hz = /bits/ 64 <375000000>;
+ opp-microvolt = <800000>;
+ };
+ opp-500000000 {
+ opp-hz = /bits/ 64 <500000000>;
+ opp-microvolt = <800000>;
+ };
+ opp-750000000 {
+ opp-hz = /bits/ 64 <750000000>;
+ opp-microvolt = <800000>;
+ };
+ opp-1500000000 {
+ opp-hz = /bits/ 64 <1500000000>;
+ opp-microvolt = <1040000>;
+ };
+ };
+
gmac0_rgmii_rxin: gmac0-rgmii-rxin-clock {
compatible = "fixed-clock";
clock-output-names = "gmac0_rgmii_rxin";
--
2.39.2
^ permalink raw reply related [flat|nested] 6+ messages in thread* Re: [PATCH v2 3/3] riscv: dts: starfive: Add cpu scaling for JH7110 SoC
2023-04-17 6:39 ` [PATCH v2 3/3] riscv: dts: starfive: Add cpu scaling for JH7110 SoC Mason Huo
@ 2023-04-18 17:28 ` Conor Dooley
2023-04-20 7:10 ` Mason Huo
0 siblings, 1 reply; 6+ messages in thread
From: Conor Dooley @ 2023-04-18 17:28 UTC (permalink / raw)
To: Mason Huo
Cc: Rafael J. Wysocki, Viresh Kumar, Emil Renner Berthing,
Rob Herring, Krzysztof Kozlowski, Paul Walmsley, Palmer Dabbelt,
Albert Ou, Shengyu Qu, linux-pm, devicetree, linux-kernel,
linux-riscv
[-- Attachment #1: Type: text/plain, Size: 1332 bytes --]
Hey Mason,
Just one minor comment in passing..
On Mon, Apr 17, 2023 at 02:39:42PM +0800, Mason Huo wrote:
> Add the operating-points-v2 to support cpu scaling on StarFive JH7110 SoC.
> It supports up to 4 cpu frequency loads.
>
> Signed-off-by: Mason Huo <mason.huo@starfivetech.com>
> ---
> .../jh7110-starfive-visionfive-2.dtsi | 17 ++++++++++
> arch/riscv/boot/dts/starfive/jh7110.dtsi | 33 +++++++++++++++++++
> 2 files changed, 50 insertions(+)
>
> diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
> index cca1c8040801..b25e6d68ce53 100644
> --- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
> +++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
> @@ -227,3 +227,20 @@ &uart0 {
> pinctrl-0 = <&uart0_pins>;
> status = "okay";
> };
> +
> +&U74_1 {
> + cpu-supply = <&vdd_cpu>;
> +};
> +
> +&U74_2 {
> + cpu-supply = <&vdd_cpu>;
> +};
> +
> +&U74_3 {
> + cpu-supply = <&vdd_cpu>;
> +};
> +
> +&U74_4 {
> + cpu-supply = <&vdd_cpu>;
> +};
> +
Applying: riscv: dts: starfive: Add cpu scaling for JH7110 SoC
/stuff/linux/.git/rebase-apply/patch:30: new blank line at EOF.
+
warning: 1 line adds whitespace errors.
Cheers,
Conor.
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]
^ permalink raw reply [flat|nested] 6+ messages in thread* Re: [PATCH v2 3/3] riscv: dts: starfive: Add cpu scaling for JH7110 SoC
2023-04-18 17:28 ` Conor Dooley
@ 2023-04-20 7:10 ` Mason Huo
0 siblings, 0 replies; 6+ messages in thread
From: Mason Huo @ 2023-04-20 7:10 UTC (permalink / raw)
To: Conor Dooley
Cc: Rafael J. Wysocki, Viresh Kumar, Emil Renner Berthing,
Rob Herring, Krzysztof Kozlowski, Paul Walmsley, Palmer Dabbelt,
Albert Ou, Shengyu Qu, linux-pm, devicetree, linux-kernel,
linux-riscv
On 2023/4/19 1:28, Conor Dooley wrote:
> Hey Mason,
>
> Just one minor comment in passing..
>
> On Mon, Apr 17, 2023 at 02:39:42PM +0800, Mason Huo wrote:
>> Add the operating-points-v2 to support cpu scaling on StarFive JH7110 SoC.
>> It supports up to 4 cpu frequency loads.
>>
>> Signed-off-by: Mason Huo <mason.huo@starfivetech.com>
>> ---
>> .../jh7110-starfive-visionfive-2.dtsi | 17 ++++++++++
>> arch/riscv/boot/dts/starfive/jh7110.dtsi | 33 +++++++++++++++++++
>> 2 files changed, 50 insertions(+)
>>
>> diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
>> index cca1c8040801..b25e6d68ce53 100644
>> --- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
>> +++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
>> @@ -227,3 +227,20 @@ &uart0 {
>> pinctrl-0 = <&uart0_pins>;
>> status = "okay";
>> };
>> +
>> +&U74_1 {
>> + cpu-supply = <&vdd_cpu>;
>> +};
>> +
>> +&U74_2 {
>> + cpu-supply = <&vdd_cpu>;
>> +};
>> +
>> +&U74_3 {
>> + cpu-supply = <&vdd_cpu>;
>> +};
>> +
>> +&U74_4 {
>> + cpu-supply = <&vdd_cpu>;
>> +};
>> +
>
> Applying: riscv: dts: starfive: Add cpu scaling for JH7110 SoC
> /stuff/linux/.git/rebase-apply/patch:30: new blank line at EOF.
> +
> warning: 1 line adds whitespace errors.
>
> Cheers,
> Conor.
>
Hi Conor,
Will fix it soon.
Thanks
Mason
^ permalink raw reply [flat|nested] 6+ messages in thread