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[66.90.144.107]) by smtp.gmail.com with ESMTPSA id i11-20020aca3b0b000000b0038c235e24fesm2571828oia.48.2023.04.18.15.41.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 18 Apr 2023 15:41:47 -0700 (PDT) Received: (nullmailer pid 2456811 invoked by uid 1000); Tue, 18 Apr 2023 22:41:46 -0000 Date: Tue, 18 Apr 2023 17:41:46 -0500 From: Rob Herring To: Linus Walleij Cc: Vinod Koul , Krzysztof Kozlowski , dmaengine@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: Re: [PATCH 1/7] dt-bindings: dma: dma40: Prefer to pass sram through phandle Message-ID: <20230418224146.GA2453289-robh@kernel.org> References: <20230417-ux500-dma40-cleanup-v1-0-b26324956e47@linaro.org> <20230417-ux500-dma40-cleanup-v1-1-b26324956e47@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20230417-ux500-dma40-cleanup-v1-1-b26324956e47@linaro.org> Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On Mon, Apr 17, 2023 at 09:55:46AM +0200, Linus Walleij wrote: > Extend the DMA40 bindings so that we can pass two SRAM > segments as phandles instead of directly referring to the > memory address in the second reg cell. This enables more > granular control over the SRAM, and adds the optiona LCLA > SRAM segment as well. > > Deprecate the old way of passing LCPA as a second reg cell, > make sram compulsory. > > Signed-off-by: Linus Walleij > --- > .../devicetree/bindings/dma/stericsson,dma40.yaml | 35 +++++++++++++++++----- > 1 file changed, 27 insertions(+), 8 deletions(-) > > diff --git a/Documentation/devicetree/bindings/dma/stericsson,dma40.yaml b/Documentation/devicetree/bindings/dma/stericsson,dma40.yaml > index 64845347f44d..4fe0df937171 100644 > --- a/Documentation/devicetree/bindings/dma/stericsson,dma40.yaml > +++ b/Documentation/devicetree/bindings/dma/stericsson,dma40.yaml > @@ -112,14 +112,23 @@ properties: > - const: stericsson,dma40 > > reg: > - items: > - - description: DMA40 memory base > - - description: LCPA memory base > + oneOf: > + - items: > + - description: DMA40 memory base > + - items: > + - description: DMA40 memory base > + - description: LCPA memory base, deprecated, use eSRAM pool instead > + deprecated: true > + > > reg-names: > - items: > - - const: base > - - const: lcpa > + oneOf: > + - items: > + - const: base > + - items: > + - const: base > + - const: lcpa > + deprecated: true > > interrupts: > maxItems: 1 > @@ -127,6 +136,14 @@ properties: > clocks: > maxItems: 1 > > + sram: > + $ref: '/schemas/types.yaml#/definitions/phandle-array' Drop quotes. > + items: > + maxItems: 2 phandle-array really means phandle+args array. So the inner size is 1 plus number of arg cells. Since you have no arg cells, that would be: maxItems: 2 items: maxItems: 1 > + description: > + List of phandles for the SRAM used by the DMA40 block, the first > + phandle is the LCPA memory, the second is the LCLA memory. > + > memcpy-channels: > $ref: /schemas/types.yaml#/definitions/uint32-array > description: Array of u32 elements indicating which channels on the DMA > @@ -138,6 +155,7 @@ required: > - reg > - interrupts > - clocks > + - sram > - memcpy-channels > > additionalProperties: false > @@ -149,8 +167,9 @@ examples: > #include > dma-controller@801c0000 { > compatible = "stericsson,db8500-dma40", "stericsson,dma40"; > - reg = <0x801c0000 0x1000>, <0x40010000 0x800>; > - reg-names = "base", "lcpa"; > + reg = <0x801c0000 0x1000>; > + reg-names = "base"; > + sram = <&lcpa>, <&lcla>; > interrupts = ; > #dma-cells = <3>; > memcpy-channels = <56 57 58 59 60>; > > -- > 2.39.2 >