public inbox for devicetree@vger.kernel.org
 help / color / mirror / Atom feed
From: Manivannan Sadhasivam <mani@kernel.org>
To: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Cc: jingoohan1@gmail.com, gustavo.pimentel@synopsys.com,
	fancer.lancer@gmail.com, lpieralisi@kernel.org,
	robh+dt@kernel.org, kw@linux.com, bhelgaas@google.com,
	kishon@kernel.org, marek.vasut+renesas@gmail.com,
	linux-pci@vger.kernel.org, devicetree@vger.kernel.org,
	linux-renesas-soc@vger.kernel.org
Subject: Re: [PATCH v13 09/22] PCI: dwc: Add support for triggering INTx IRQs
Date: Sat, 22 Apr 2023 17:09:08 +0530	[thread overview]
Message-ID: <20230422113908.GF4769@thinkpad> (raw)
In-Reply-To: <20230418122403.3178462-10-yoshihiro.shimoda.uh@renesas.com>

On Tue, Apr 18, 2023 at 09:23:50PM +0900, Yoshihiro Shimoda wrote:

It's good to add "endpoint drivers" in subject as below:

PCI: dwc: Add support for triggering INTx IRQs from endpoint drivers

> Add support for triggering INTx IRQs by using outbound iATU.
> Outbound iATU is utilized to send assert and de-assert INTx TLPs.
> The message is generated based on the payloadless Msg TLP with type
> 0x14, where 0x4 is the routing code implying the Terminate at
> Receiver message. The message code is specified as b1000xx for
> the INTx assertion and b1001xx for the INTx de-assertion.
> 
> Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
> ---
>  .../pci/controller/dwc/pcie-designware-ep.c   | 70 +++++++++++++++++--
>  drivers/pci/controller/dwc/pcie-designware.h  |  2 +
>  2 files changed, 68 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c
> index 96375b0aba82..304ed093f551 100644
> --- a/drivers/pci/controller/dwc/pcie-designware-ep.c
> +++ b/drivers/pci/controller/dwc/pcie-designware-ep.c
> @@ -6,6 +6,7 @@
>   * Author: Kishon Vijay Abraham I <kishon@ti.com>
>   */
>  
> +#include <linux/delay.h>
>  #include <linux/of.h>
>  #include <linux/platform_device.h>
>  
> @@ -485,14 +486,62 @@ static const struct pci_epc_ops epc_ops = {
>  	.get_features		= dw_pcie_ep_get_features,
>  };
>  
> +static int dw_pcie_ep_send_msg(struct dw_pcie_ep *ep, u8 func_no, u8 code,
> +			       u8 routing)
> +{
> +	struct dw_pcie_outbound_atu atu = { 0 };
> +	struct pci_epc *epc = ep->epc;
> +	int ret;
> +
> +	atu.func_no = func_no;
> +	atu.code = code;
> +	atu.routing = routing;
> +	atu.type = PCIE_ATU_TYPE_MSG;
> +	atu.cpu_addr = ep->intx_mem_phys;
> +	atu.size = epc->mem->window.page_size;

Newline here.

> +	ret = dw_pcie_ep_outbound_atu(ep, &atu);
> +	if (ret)
> +		return ret;
> +
> +	writel(0, ep->intx_mem);
> +
> +	dw_pcie_ep_unmap_addr(epc, func_no, 0, ep->intx_mem_phys);
> +
> +	return 0;
> +}
> +
> +static int __dw_pcie_ep_raise_intx_irq(struct dw_pcie_ep *ep, u8 func_no,
> +					 int intx)
> +{
> +	int ret;
> +
> +	ret = dw_pcie_ep_send_msg(ep, func_no, PCI_CODE_ASSERT_INTA + intx,
> +				  PCI_MSG_ROUTING_LOCAL);
> +	if (ret)
> +		return ret;
> +
> +	/*
> +	 * The documents of PCIe and the controller don't mention how long
> +	 * the INTx should be asserted. If 10 usec, sometimes it failed.
> +	 * So, asserted for 50 usec.
> +	 */
> +	usleep_range(50, 100);
> +
> +	return dw_pcie_ep_send_msg(ep, func_no, PCI_CODE_DEASSERT_INTA + intx,
> +				   PCI_MSG_ROUTING_LOCAL);
> +}
> +
>  int dw_pcie_ep_raise_intx_irq(struct dw_pcie_ep *ep, u8 func_no)
>  {
>  	struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
>  	struct device *dev = pci->dev;
>  
> -	dev_err(dev, "EP cannot trigger INTx IRQs\n");
> +	if (!ep->intx_mem) {
> +		dev_err(dev, "EP cannot trigger INTx IRQs\n");

INTx not supported.

> +		return -EINVAL;

-ENOTSUPP

- Mani

> +	}
>  
> -	return -EINVAL;
> +	return __dw_pcie_ep_raise_intx_irq(ep, func_no, 0);
>  }
>  EXPORT_SYMBOL_GPL(dw_pcie_ep_raise_intx_irq);
>  
> @@ -623,6 +672,10 @@ void dw_pcie_ep_exit(struct dw_pcie_ep *ep)
>  
>  	dw_pcie_edma_remove(pci);
>  
> +	if (ep->intx_mem)
> +		pci_epc_mem_free_addr(epc, ep->intx_mem_phys, ep->intx_mem,
> +				      epc->mem->window.page_size);
> +
>  	pci_epc_mem_free_addr(epc, ep->msi_mem_phys, ep->msi_mem,
>  			      epc->mem->window.page_size);
>  
> @@ -794,9 +847,14 @@ int dw_pcie_ep_init(struct dw_pcie_ep *ep)
>  		goto err_exit_epc_mem;
>  	}
>  
> +	ep->intx_mem = pci_epc_mem_alloc_addr(epc, &ep->intx_mem_phys,
> +					      epc->mem->window.page_size);
> +	if (!ep->intx_mem)
> +		dev_warn(dev, "Failed to reserve memory for INTx\n");
> +
>  	ret = dw_pcie_edma_detect(pci);
>  	if (ret)
> -		goto err_free_epc_mem;
> +		goto err_free_epc_mem_intx;
>  
>  	if (ep->ops->get_features) {
>  		epc_features = ep->ops->get_features(ep);
> @@ -813,7 +871,11 @@ int dw_pcie_ep_init(struct dw_pcie_ep *ep)
>  err_remove_edma:
>  	dw_pcie_edma_remove(pci);
>  
> -err_free_epc_mem:
> +err_free_epc_mem_intx:
> +	if (ep->intx_mem)
> +		pci_epc_mem_free_addr(epc, ep->intx_mem_phys, ep->intx_mem,
> +				      epc->mem->window.page_size);
> +
>  	pci_epc_mem_free_addr(epc, ep->msi_mem_phys, ep->msi_mem,
>  			      epc->mem->window.page_size);
>  
> diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h
> index 954d504890a1..8c08159ea08e 100644
> --- a/drivers/pci/controller/dwc/pcie-designware.h
> +++ b/drivers/pci/controller/dwc/pcie-designware.h
> @@ -369,6 +369,8 @@ struct dw_pcie_ep {
>  	unsigned long		*ob_window_map;
>  	void __iomem		*msi_mem;
>  	phys_addr_t		msi_mem_phys;
> +	void __iomem		*intx_mem;
> +	phys_addr_t		intx_mem_phys;
>  	struct pci_epf_bar	*epf_bar[PCI_STD_NUM_BARS];
>  };
>  
> -- 
> 2.25.1
> 

-- 
மணிவண்ணன் சதாசிவம்

  reply	other threads:[~2023-04-22 11:39 UTC|newest]

Thread overview: 58+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-04-18 12:23 [PATCH v13 00/22] PCI: rcar-gen4: Add R-Car Gen4 PCIe support Yoshihiro Shimoda
2023-04-18 12:23 ` [PATCH v13 01/22] PCI: Add PCI_EXP_LNKCAP_MLW macros Yoshihiro Shimoda
2023-04-18 12:23 ` [PATCH v13 02/22] PCI: Add PCI_HEADER_TYPE_MULTI_FUNC Yoshihiro Shimoda
2023-04-18 12:23 ` [PATCH v13 03/22] PCI: Add INTx Mechanism Messages macros Yoshihiro Shimoda
2023-04-18 12:23 ` [PATCH v13 04/22] PCI: Rename PCI_EPC_IRQ_LEGACY with PCI_EPC_IRQ_INTX Yoshihiro Shimoda
2023-04-22 10:56   ` Manivannan Sadhasivam
2023-04-24  5:00     ` Yoshihiro Shimoda
2023-04-24  6:44   ` Jesper Nilsson
2023-04-18 12:23 ` [PATCH v13 05/22] PCI: dwc: Rename with dw_pcie_ep_raise_intx_irq() Yoshihiro Shimoda
2023-04-22 11:01   ` Manivannan Sadhasivam
2023-04-24  5:02     ` Yoshihiro Shimoda
2023-04-18 12:23 ` [PATCH v13 06/22] PCI: dwc: Introduce struct dw_pcie_outbound_atu Yoshihiro Shimoda
2023-04-22 11:09   ` Manivannan Sadhasivam
2023-04-22 11:15     ` Manivannan Sadhasivam
2023-04-24  5:23       ` Yoshihiro Shimoda
2023-04-18 12:23 ` [PATCH v13 07/22] PCI: dwc: Add members into " Yoshihiro Shimoda
2023-04-18 12:23 ` [PATCH v13 08/22] PCI: dwc: Change arguments of dw_pcie_prog_ep_outbound_atu() Yoshihiro Shimoda
2023-04-22 11:14   ` Manivannan Sadhasivam
2023-04-24  5:22     ` Yoshihiro Shimoda
2023-04-18 12:23 ` [PATCH v13 09/22] PCI: dwc: Add support for triggering INTx IRQs Yoshihiro Shimoda
2023-04-22 11:39   ` Manivannan Sadhasivam [this message]
2023-04-24  5:25     ` Yoshihiro Shimoda
2023-04-18 12:23 ` [PATCH v13 10/22] PCI: dwc: Add dw_pcie_link_set_max_link_width() Yoshihiro Shimoda
2023-04-22 11:45   ` Manivannan Sadhasivam
2023-04-18 12:23 ` [PATCH v13 11/22] PCI: dwc: Add dw_pcie_link_set_max_width() Yoshihiro Shimoda
2023-04-22 11:50   ` Manivannan Sadhasivam
2023-04-24  5:27     ` Yoshihiro Shimoda
2023-04-18 12:23 ` [PATCH v13 12/22] PCI: dwc: Add dw_pcie_link_set_max_cap_width() Yoshihiro Shimoda
2023-04-22 13:49   ` Manivannan Sadhasivam
2023-04-24  5:34     ` Yoshihiro Shimoda
2023-04-18 12:23 ` [PATCH v13 13/22] PCI: dwc: Add EDMA_UNROLL capability flag Yoshihiro Shimoda
2023-04-22 13:56   ` Manivannan Sadhasivam
2023-04-24  6:00     ` Yoshihiro Shimoda
2023-04-18 12:23 ` [PATCH v13 14/22] PCI: dwc: Expose dw_pcie_ep_exit() to module Yoshihiro Shimoda
2023-04-22 13:58   ` Manivannan Sadhasivam
2023-04-24  6:26     ` Yoshihiro Shimoda
2023-04-18 12:23 ` [PATCH v13 15/22] PCI: dwc: Introduce .ep_pre_init() and .ep_deinit() Yoshihiro Shimoda
2023-04-22 14:00   ` Manivannan Sadhasivam
2023-04-24  6:27     ` Yoshihiro Shimoda
2023-04-18 12:23 ` [PATCH v13 16/22] dt-bindings: PCI: dwc: Update maxItems of reg and reg-names Yoshihiro Shimoda
2023-04-21 18:04   ` Rob Herring
2023-04-22 14:02   ` Manivannan Sadhasivam
2023-04-24  6:28     ` Yoshihiro Shimoda
2023-04-18 12:23 ` [PATCH v13 17/22] dt-bindings: PCI: renesas: Add R-Car Gen4 PCIe Host Yoshihiro Shimoda
2023-04-22 14:06   ` Manivannan Sadhasivam
2023-04-24  8:59     ` Yoshihiro Shimoda
2023-04-18 12:23 ` [PATCH v13 18/22] dt-bindings: PCI: renesas: Add R-Car Gen4 PCIe Endpoint Yoshihiro Shimoda
2023-04-22 14:08   ` Manivannan Sadhasivam
2023-04-18 12:24 ` [PATCH v13 19/22] PCI: rcar-gen4: Add R-Car Gen4 PCIe Host support Yoshihiro Shimoda
2023-04-22 14:38   ` Manivannan Sadhasivam
2023-04-24 10:46     ` Yoshihiro Shimoda
2023-04-18 12:24 ` [PATCH v13 20/22] PCI: rcar-gen4-ep: Add R-Car Gen4 PCIe Endpoint support Yoshihiro Shimoda
2023-04-22 14:47   ` Manivannan Sadhasivam
2023-04-24 11:37     ` Yoshihiro Shimoda
2023-04-18 12:24 ` [PATCH v13 21/22] MAINTAINERS: Update PCI DRIVER FOR RENESAS R-CAR for R-Car Gen4 Yoshihiro Shimoda
2023-04-22 14:49   ` Manivannan Sadhasivam
2023-04-18 12:24 ` [PATCH v13 22/22] misc: pci_endpoint_test: Add Device ID for R-Car S4-8 PCIe controller Yoshihiro Shimoda
2023-04-22 14:51   ` Manivannan Sadhasivam

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20230422113908.GF4769@thinkpad \
    --to=mani@kernel.org \
    --cc=bhelgaas@google.com \
    --cc=devicetree@vger.kernel.org \
    --cc=fancer.lancer@gmail.com \
    --cc=gustavo.pimentel@synopsys.com \
    --cc=jingoohan1@gmail.com \
    --cc=kishon@kernel.org \
    --cc=kw@linux.com \
    --cc=linux-pci@vger.kernel.org \
    --cc=linux-renesas-soc@vger.kernel.org \
    --cc=lpieralisi@kernel.org \
    --cc=marek.vasut+renesas@gmail.com \
    --cc=robh+dt@kernel.org \
    --cc=yoshihiro.shimoda.uh@renesas.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox