* [PATCH 1/2] dt-bindings: arm: ti: Add bindings for PHYTEC AM62x based hardware
@ 2023-05-04 14:01 Wadim Egorov
2023-05-04 14:01 ` [PATCH 2/2] arm64: dts: ti: Add basic support for phyBOARD-Lyra-AM625 Wadim Egorov
` (3 more replies)
0 siblings, 4 replies; 10+ messages in thread
From: Wadim Egorov @ 2023-05-04 14:01 UTC (permalink / raw)
To: linux-kernel, devicetree, linux-arm-kernel, linux-hardening
Cc: upstream, nm, vigneshr, kristo, robh+dt, krzysztof.kozlowski+dt,
keescook, tony.luck, gpiccoli
Add devicetree bindings for AM62x based phyCORE-AM62 SoM
and phyBOARD-Lyra RDK.
Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
---
Documentation/devicetree/bindings/arm/ti/k3.yaml | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/ti/k3.yaml b/Documentation/devicetree/bindings/arm/ti/k3.yaml
index e1183f90bb06..254b5ec51f34 100644
--- a/Documentation/devicetree/bindings/arm/ti/k3.yaml
+++ b/Documentation/devicetree/bindings/arm/ti/k3.yaml
@@ -25,6 +25,12 @@ properties:
- ti,am62a7-sk
- const: ti,am62a7
+ - description: K3 AM625 SoC PHYTEC phyBOARD-Lyra
+ items:
+ - const: phytec,am625-phyboard-lyra-rdk
+ - const: phytec,am62-phycore-som
+ - const: ti,am625
+
- description: K3 AM625 SoC
items:
- enum:
--
2.25.1
^ permalink raw reply related [flat|nested] 10+ messages in thread* [PATCH 2/2] arm64: dts: ti: Add basic support for phyBOARD-Lyra-AM625 2023-05-04 14:01 [PATCH 1/2] dt-bindings: arm: ti: Add bindings for PHYTEC AM62x based hardware Wadim Egorov @ 2023-05-04 14:01 ` Wadim Egorov 2023-05-04 14:26 ` Nishanth Menon 2023-05-05 9:41 ` Tony Lindgren 2023-05-05 6:53 ` [PATCH 1/2] dt-bindings: arm: ti: Add bindings for PHYTEC AM62x based hardware Krzysztof Kozlowski ` (2 subsequent siblings) 3 siblings, 2 replies; 10+ messages in thread From: Wadim Egorov @ 2023-05-04 14:01 UTC (permalink / raw) To: linux-kernel, devicetree, linux-arm-kernel, linux-hardening Cc: upstream, nm, vigneshr, kristo, robh+dt, krzysztof.kozlowski+dt, keescook, tony.luck, gpiccoli The phyCORE-AM62x [1] is a SoM (System on Module) featuring TI's AM62x SoC. It can be used in combination with different carrier boards. This module can come with different sizes and models for DDR, eMMC, SPI NOR Flash and various SoCs from the AM62x family. A development Kit, called phyBOARD-Lyra [2] is used as a carrier board reference design around the AM62x SoM. Supported features: * Debug UART * SPI NOR Flash * eMMC * 2x Ethernet * Micro SD card * I2C EEPROM * I2C RTC * GPIO Expander * LEDs * USB For more details, see: [1] Product page SoM: https://www.phytec.com/product/phycore-am62x [2] Product page CB: https://www.phytec.com/product/phyboard-am62x Signed-off-by: Wadim Egorov <w.egorov@phytec.de> --- arch/arm64/boot/dts/ti/Makefile | 1 + .../boot/dts/ti/k3-am62-phycore-som.dtsi | 324 ++++++++++++++++++ .../dts/ti/k3-am625-phyboard-lyra-rdk.dts | 267 +++++++++++++++ 3 files changed, 592 insertions(+) create mode 100644 arch/arm64/boot/dts/ti/k3-am62-phycore-som.dtsi create mode 100644 arch/arm64/boot/dts/ti/k3-am625-phyboard-lyra-rdk.dts diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makefile index c83c9d772b81..9388dc481d7d 100644 --- a/arch/arm64/boot/dts/ti/Makefile +++ b/arch/arm64/boot/dts/ti/Makefile @@ -10,6 +10,7 @@ # Boards with AM62x SoC dtb-$(CONFIG_ARCH_K3) += k3-am625-beagleplay.dtb +dtb-$(CONFIG_ARCH_K3) += k3-am625-phyboard-lyra-rdk.dtb dtb-$(CONFIG_ARCH_K3) += k3-am625-sk.dtb dtb-$(CONFIG_ARCH_K3) += k3-am62-lp-sk.dtb diff --git a/arch/arm64/boot/dts/ti/k3-am62-phycore-som.dtsi b/arch/arm64/boot/dts/ti/k3-am62-phycore-som.dtsi new file mode 100644 index 000000000000..32264296c8c6 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am62-phycore-som.dtsi @@ -0,0 +1,324 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2022 - 2023 PHYTEC Messtechnik GmbH + * Author: Wadim Egorov <w.egorov@phytec.de> + * + * Product homepage: + * https://www.phytec.com/product/phycore-am62x + */ + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/leds/common.h> +#include <dt-bindings/net/ti-dp83867.h> + +/ { + model = "PHYTEC phyCORE-AM62x"; + compatible = "phytec,am62-phycore-som", "ti,am625"; + + aliases { + ethernet0 = &cpsw_port1; + gpio0 = &main_gpio0; + gpio1 = &main_gpio1; + i2c0 = &main_i2c0; + mmc0 = &sdhci0; + rtc0 = &i2c_som_rtc; + rtc1 = &wkup_rtc0; + spi0 = &ospi0; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x00000000 0x80000000 0x00000000 0x80000000>; + }; + + reserved_memory: reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + ramoops@9ca00000 { + compatible = "ramoops"; + reg = <0x00 0x9ca00000 0x00 0x00100000>; + record-size = <0x8000>; + console-size = <0x8000>; + ftrace-size = <0x00>; + pmsg-size = <0x8000>; + }; + + secure_tfa_ddr: tfa@9e780000 { + reg = <0x00 0x9e780000 0x00 0x80000>; + alignment = <0x1000>; + no-map; + }; + + secure_ddr: optee@9e800000 { + reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */ + alignment = <0x1000>; + no-map; + }; + + wkup_r5fss0_core0_dma_memory_region: r5f-dma-memory@9db00000 { + compatible = "shared-dma-pool"; + reg = <0x00 0x9db00000 0x00 0x00c00000>; + no-map; + }; + }; + + vcc_5v0_som: regulator-vcc-5v0-som { + compatible = "regulator-fixed"; + regulator-name = "VCC_5V0_SOM"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + }; + + vdd_1v8: regulator-vdd-1v8 { + compatible = "regulator-fixed"; + regulator-name = "VDD_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc_5v0_som>; + regulator-always-on; + regulator-boot-on; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&leds_pins_default>; + + led-0 { + color = <LED_COLOR_ID_GREEN>; + gpios = <&main_gpio0 13 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + function = LED_FUNCTION_HEARTBEAT; + }; + }; +}; + +&main_pmx0 { + leds_pins_default: leds-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x034, PIN_OUTPUT, 7) /* (H21) OSPI0_CSN2.GPIO0_13 */ + >; + }; + + main_i2c0_pins_default: main-i2c0-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x1e0, PIN_INPUT_PULLUP, 0) /* (B16) I2C0_SCL */ + AM62X_IOPAD(0x1e4, PIN_INPUT_PULLUP, 0) /* (A16) I2C0_SDA */ + >; + }; + + main_mdio1_pins_default: main_mdio1-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x160, PIN_OUTPUT, 0) /* (AD24) MDIO0_MDC */ + AM62X_IOPAD(0x15c, PIN_INPUT, 0) /* (AB22) MDIO0_MDIO */ + >; + }; + + main_mmc0_pins_default: main-mmc0-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x220, PIN_INPUT_PULLUP, 0) /* (Y3) MMC0_CMD */ + AM62X_IOPAD(0x218, PIN_INPUT_PULLDOWN, 0) /* (AB1) MMC0_CLK */ + AM62X_IOPAD(0x214, PIN_INPUT_PULLUP, 0) /* (AA2) MMC0_DAT0 */ + AM62X_IOPAD(0x210, PIN_INPUT_PULLUP, 0) /* (AA1) MMC0_DAT1 */ + AM62X_IOPAD(0x20c, PIN_INPUT_PULLUP, 0) /* (AA3) MMC0_DAT2 */ + AM62X_IOPAD(0x208, PIN_INPUT_PULLUP, 0) /* (Y4) MMC0_DAT3 */ + AM62X_IOPAD(0x204, PIN_INPUT_PULLUP, 0) /* (AB2) MMC0_DAT4 */ + AM62X_IOPAD(0x200, PIN_INPUT_PULLUP, 0) /* (AC1) MMC0_DAT5 */ + AM62X_IOPAD(0x1fc, PIN_INPUT_PULLUP, 0) /* (AD2) MMC0_DAT6 */ + AM62X_IOPAD(0x1f8, PIN_INPUT_PULLUP, 0) /* (AC2) MMC0_DAT7 */ + >; + }; + + main_rgmii1_pins_default: main-rgmii1-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x14c, PIN_INPUT, 0) /* (AB17) RGMII1_RD0 */ + AM62X_IOPAD(0x150, PIN_INPUT, 0) /* (AC17) RGMII1_RD1 */ + AM62X_IOPAD(0x154, PIN_INPUT, 0) /* (AB16) RGMII1_RD2 */ + AM62X_IOPAD(0x158, PIN_INPUT, 0) /* (AA15) RGMII1_RD3 */ + AM62X_IOPAD(0x148, PIN_INPUT, 0) /* (AD17) RGMII1_RXC */ + AM62X_IOPAD(0x144, PIN_INPUT, 0) /* (AE17) RGMII1_RX_CTL */ + AM62X_IOPAD(0x134, PIN_OUTPUT, 0) /* (AE20) RGMII1_TD0 */ + AM62X_IOPAD(0x138, PIN_OUTPUT, 0) /* (AD20) RGMII1_TD1 */ + AM62X_IOPAD(0x13c, PIN_OUTPUT, 0) /* (AE18) RGMII1_TD2 */ + AM62X_IOPAD(0x140, PIN_OUTPUT, 0) /* (AD18) RGMII1_TD3 */ + AM62X_IOPAD(0x130, PIN_OUTPUT, 0) /* (AE19) RGMII1_TXC */ + AM62X_IOPAD(0x12c, PIN_OUTPUT, 0) /* (AD19) RGMII1_TX_CTL */ + >; + }; + + ospi0_pins_default: ospi0-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x000, PIN_OUTPUT, 0) /* (H24) OSPI0_CLK */ + AM62X_IOPAD(0x02c, PIN_OUTPUT, 0) /* (F23) OSPI0_CSn0 */ + AM62X_IOPAD(0x00c, PIN_INPUT, 0) /* (E25) OSPI0_D0 */ + AM62X_IOPAD(0x010, PIN_INPUT, 0) /* (G24) OSPI0_D1 */ + AM62X_IOPAD(0x014, PIN_INPUT, 0) /* (F25) OSPI0_D2 */ + AM62X_IOPAD(0x018, PIN_INPUT, 0) /* (F24) OSPI0_D3 */ + AM62X_IOPAD(0x01c, PIN_INPUT, 0) /* (J23) OSPI0_D4 */ + AM62X_IOPAD(0x020, PIN_INPUT, 0) /* (J25) OSPI0_D5 */ + AM62X_IOPAD(0x024, PIN_INPUT, 0) /* (H25) OSPI0_D6 */ + AM62X_IOPAD(0x028, PIN_INPUT, 0) /* (J22) OSPI0_D7 */ + AM62X_IOPAD(0x008, PIN_INPUT, 0) /* (J24) OSPI0_DQS */ + >; + }; + + pmic_irq_pins_default: pmic-irq-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x01f4, PIN_INPUT, 0) /* (D16) EXTINTn */ + >; + }; +}; + +&cpsw3g { + pinctrl-names = "default"; + pinctrl-0 = <&main_rgmii1_pins_default>; +}; + +&cpsw_port1 { + phy-mode = "rgmii-rxid"; + phy-handle = <&cpsw3g_phy1>; +}; + +&cpsw3g_mdio { + pinctrl-names = "default"; + pinctrl-0 = <&main_mdio1_pins_default>; + status = "okay"; + + cpsw3g_phy1: ethernet-phy@1 { + compatible = "ethernet-phy-id2000.a231", "ethernet-phy-ieee802.3-c22"; + reg = <1>; + ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; + ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; + }; +}; + +&main_i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&main_i2c0_pins_default>; + clock-frequency = <400000>; + status = "okay"; + + pmic@30 { + compatible = "ti,tps65219"; + reg = <0x30>; + buck1-supply = <&vcc_5v0_som>; + buck2-supply = <&vcc_5v0_som>; + buck3-supply = <&vcc_5v0_som>; + ldo1-supply = <&vdd_3v3>; + ldo2-supply = <&vdd_1v8>; + ldo3-supply = <&vcc_5v0_som>; + ldo4-supply = <&vcc_5v0_som>; + + pinctrl-names = "default"; + pinctrl-0 = <&pmic_irq_pins_default>; + interrupt-parent = <&gic500>; + interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <1>; + + ti,power-button; + system-power-controller; + + regulators { + vdd_core: buck1 { + regulator-name = "VDD_CORE"; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + regulator-boot-on; + regulator-always-on; + }; + + vdd_3v3: buck2 { + regulator-name = "VDD_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + vdd_ddr4: buck3 { + regulator-name = "VDD_DDR4"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-boot-on; + regulator-always-on; + }; + + vddshv5_sdio: ldo1 { + regulator-name = "VDDSHV5_SDIO"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-allow-bypass; + regulator-boot-on; + regulator-always-on; + }; + + vddr_core: ldo2 { + regulator-name = "VDDR_CORE"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + regulator-boot-on; + regulator-always-on; + }; + + vdda_1v8: ldo3 { + regulator-name = "VDDA_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + vdd_2v5: ldo4 { + regulator-name = "VDD_2V5"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-boot-on; + regulator-always-on; + }; + }; + }; + + eeprom@50 { + compatible = "atmel,24c32"; + pagesize = <32>; + reg = <0x50>; + }; + + i2c_som_rtc: rtc@52 { + compatible = "microcrystal,rv3028"; + reg = <0x52>; + }; +}; + +&ospi0 { + pinctrl-names = "default"; + pinctrl-0 = <&ospi0_pins_default>; + status = "okay"; + + serial_flash: flash@0 { + compatible = "jedec,spi-nor"; + reg = <0x0>; + spi-tx-bus-width = <8>; + spi-rx-bus-width = <8>; + spi-max-frequency = <25000000>; + cdns,tshsl-ns = <60>; + cdns,tsd2d-ns = <60>; + cdns,tchsh-ns = <60>; + cdns,tslch-ns = <60>; + cdns,read-delay = <0>; + }; +}; + +&sdhci0 { + pinctrl-names = "default"; + pinctrl-0 = <&main_mmc0_pins_default>; + ti,driver-strength-ohm = <50>; + disable-wp; + non-removable; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/ti/k3-am625-phyboard-lyra-rdk.dts b/arch/arm64/boot/dts/ti/k3-am625-phyboard-lyra-rdk.dts new file mode 100644 index 000000000000..bad26b554f98 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am625-phyboard-lyra-rdk.dts @@ -0,0 +1,267 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2022 - 2023 PHYTEC Messtechnik GmbH + * Author: Wadim Egorov <w.egorov@phytec.de> + * + * Product homepage: + * https://www.phytec.com/product/phyboard-am62x + */ + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> +#include <dt-bindings/leds/common.h> +#include <dt-bindings/net/ti-dp83867.h> +#include "k3-am625.dtsi" +#include "k3-am62-phycore-som.dtsi" + +/ { + compatible = "phytec,am625-phyboard-lyra-rdk", + "phytec,am62-phycore-som", "ti,am625"; + model = "PHYTEC phyBOARD-Lyra AM625"; + + aliases { + serial2 = &main_uart0; + serial3 = &main_uart1; + mmc1 = &sdhci1; + usb0 = &usb0; + usb1 = &usb1; + ethernet1 = &cpsw_port2; + }; + + can_tc1: can-phy0 { + compatible = "ti,tcan1042"; + #phy-cells = <0>; + max-bitrate = <5000000>; + standby-gpios = <&gpio_exp 1 GPIO_ACTIVE_HIGH>; + }; + + keys { + compatible = "gpio-keys"; + autorepeat; + pinctrl-names = "default"; + pinctrl-0 = <&gpio_keys_pins_default>; + + key-home { + label = "home"; + linux,code = <KEY_HOME>; + gpios = <&main_gpio1 23 GPIO_ACTIVE_HIGH>; + }; + + key-menu { + label = "menu"; + linux,code = <KEY_MENU>; + gpios = <&gpio_exp 4 GPIO_ACTIVE_HIGH>; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&leds_pins_default &user_leds_pins_default>; + + led-1 { + gpios = <&main_gpio0 32 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "mmc0"; + }; + + led-2 { + gpios = <&gpio_exp 2 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "mmc1"; + }; + }; + + vcc_3v3_mmc: regulator-vcc-3v3-mmc { + compatible = "regulator-fixed"; + regulator-name = "VCC_3V3_MMC"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; +}; + +&main_pmx0 { + gpio_keys_pins_default: gpio-keys-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x1d4, PIN_INPUT, 7) /* (B15) UART0_RTSn.GPIO1_23 */ + >; + }; + + gpio_exp_int_pins_default: gpio-exp-int-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x244, PIN_INPUT, 7) /* (C17) MMC1_SDWP.GPIO1_49 */ + >; + }; + + main_i2c1_pins_default: main-i2c1-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x1e8, PIN_INPUT_PULLUP, 0) /* (B17) I2C1_SCL */ + AM62X_IOPAD(0x1ec, PIN_INPUT_PULLUP, 0) /* (A17) I2C1_SDA */ + >; + }; + + main_mcan0_pins_default: main-mcan0-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x1dc, PIN_INPUT, 0) /* (E15) MCAN0_RX */ + AM62X_IOPAD(0x1d8, PIN_OUTPUT, 0) /* (C15) MCAN0_TX */ + >; + }; + + main_mmc1_pins_default: main-mmc1-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x23c, PIN_INPUT_PULLUP, 0) /* (A21) MMC1_CMD */ + AM62X_IOPAD(0x234, PIN_INPUT_PULLDOWN, 0) /* (B22) MMC1_CLK */ + AM62X_IOPAD(0x230, PIN_INPUT_PULLUP, 0) /* (A22) MMC1_DAT0 */ + AM62X_IOPAD(0x22c, PIN_INPUT_PULLUP, 0) /* (B21) MMC1_DAT1 */ + AM62X_IOPAD(0x228, PIN_INPUT_PULLUP, 0) /* (C21) MMC1_DAT2 */ + AM62X_IOPAD(0x224, PIN_INPUT_PULLUP, 0) /* (D22) MMC1_DAT3 */ + AM62X_IOPAD(0x240, PIN_INPUT_PULLUP, 0) /* (D17) MMC1_SDCD */ + >; + }; + + main_rgmii2_pins_default: main-rgmii2-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x184, PIN_INPUT, 0) /* (AE23) RGMII2_RD0 */ + AM62X_IOPAD(0x188, PIN_INPUT, 0) /* (AB20) RGMII2_RD1 */ + AM62X_IOPAD(0x18c, PIN_INPUT, 0) /* (AC21) RGMII2_RD2 */ + AM62X_IOPAD(0x190, PIN_INPUT, 0) /* (AE22) RGMII2_RD3 */ + AM62X_IOPAD(0x180, PIN_INPUT, 0) /* (AD23) RGMII2_RXC */ + AM62X_IOPAD(0x17c, PIN_INPUT, 0) /* (AD22) RGMII2_RX_CTL */ + AM62X_IOPAD(0x16c, PIN_OUTPUT, 0) /* (Y18) RGMII2_TD0 */ + AM62X_IOPAD(0x170, PIN_OUTPUT, 0) /* (AA18) RGMII2_TD1 */ + AM62X_IOPAD(0x174, PIN_OUTPUT, 0) /* (AD21) RGMII2_TD2 */ + AM62X_IOPAD(0x178, PIN_OUTPUT, 0) /* (AC20) RGMII2_TD3 */ + AM62X_IOPAD(0x168, PIN_OUTPUT, 0) /* (AE21) RGMII2_TXC */ + AM62X_IOPAD(0x164, PIN_OUTPUT, 0) /* (AA19) RGMII2_TX_CTL */ + >; + }; + + main_uart0_pins_default: main-uart0-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x1c8, PIN_INPUT, 0) /* (D14) UART0_RXD */ + AM62X_IOPAD(0x1cc, PIN_OUTPUT, 0) /* (E14) UART0_TXD */ + >; + }; + + main_uart1_pins_default: main-uart1-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x194, PIN_INPUT, 2) /* (B19) MCASP0_AXR3.UART1_CTSn */ + AM62X_IOPAD(0x198, PIN_OUTPUT, 2) /* (A19) MCASP0_AXR2.UART1_RTSn */ + AM62X_IOPAD(0x1ac, PIN_INPUT, 2) /* (E19) MCASP0_AFSR.UART1_RXD */ + AM62X_IOPAD(0x1b0, PIN_OUTPUT, 2) /* (A20) MCASP0_ACLKR.UART1_TXD */ + >; + }; + + main_usb1_pins_default: main-usb1-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x258, PIN_OUTPUT, 0) /* (F18) USB1_DRVVBUS */ + >; + }; + + user_leds_pins_default: user-leds-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x084, PIN_OUTPUT, 7) /* (L23) GPMC0_ADVn_ALE.GPIO0_32 */ + >; + }; +}; + +&cpsw3g { + pinctrl-names = "default"; + pinctrl-0 = <&main_rgmii1_pins_default + &main_rgmii2_pins_default>; +}; + +&cpsw_port2 { + phy-mode = "rgmii-rxid"; + phy-handle = <&cpsw3g_phy3>; +}; + +&cpsw3g_mdio { + cpsw3g_phy3: ethernet-phy@3 { + compatible = "ethernet-phy-id2000.a231", "ethernet-phy-ieee802.3-c22"; + reg = <3>; + ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; + ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; + }; +}; + +&main_i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&main_i2c1_pins_default>; + clock-frequency = <400000>; + status = "okay"; + + gpio_exp: gpio-expander@21 { + pinctrl-names = "default"; + pinctrl-0 = <&gpio_exp_int_pins_default>; + compatible = "nxp,pcf8574"; + reg = <0x21>; + interrupt-parent = <&main_gpio1>; + interrupts = <49 0>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + gpio-line-names = "GPIO0_HDMI_RST", "GPIO1_CAN0_nEN", + "GPIO2_LED2", "GPIO3_LVDS_GPIO", + "GPIO4_BUT2", "GPIO5_LVDS_BKLT_EN", + "GPIO6_ETH1_USER_RESET", "GPIO7_AUDIO_USER_RESET"; + }; + + eeprom@51 { + compatible = "atmel,24c02"; + pagesize = <16>; + reg = <0x51>; + }; +}; + +&main_mcan0 { + pinctrl-names = "default"; + pinctrl-0 = <&main_mcan0_pins_default>; + phys = <&can_tc1>; + status = "okay"; +}; + +&main_uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&main_uart0_pins_default>; + status = "okay"; +}; + +&main_uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&main_uart1_pins_default>; + /* Main UART1 may be used by TIFS firmware */ + status = "okay"; +}; + +&sdhci1 { + vmmc-supply = <&vcc_3v3_mmc>; + vqmmc-supply = <&vddshv5_sdio>; + pinctrl-names = "default"; + pinctrl-0 = <&main_mmc1_pins_default>; + ti,driver-strength-ohm = <50>; + disable-wp; + no-1-8-v; + status = "okay"; +}; + +&usbss0 { + ti,vbus-divider; + status = "okay"; +}; + +&usbss1 { + ti,vbus-divider; + status = "okay"; +}; + +&usb0 { + dr_mode = "peripheral"; +}; + +&usb1 { + dr_mode = "host"; + pinctrl-names = "default"; + pinctrl-0 = <&main_usb1_pins_default>; +}; -- 2.25.1 ^ permalink raw reply related [flat|nested] 10+ messages in thread
* Re: [PATCH 2/2] arm64: dts: ti: Add basic support for phyBOARD-Lyra-AM625 2023-05-04 14:01 ` [PATCH 2/2] arm64: dts: ti: Add basic support for phyBOARD-Lyra-AM625 Wadim Egorov @ 2023-05-04 14:26 ` Nishanth Menon 2023-05-05 9:39 ` Tony Lindgren 2023-05-05 9:41 ` Tony Lindgren 1 sibling, 1 reply; 10+ messages in thread From: Nishanth Menon @ 2023-05-04 14:26 UTC (permalink / raw) To: Wadim Egorov Cc: linux-kernel, devicetree, linux-arm-kernel, linux-hardening, upstream, vigneshr, kristo, robh+dt, krzysztof.kozlowski+dt, keescook, tony.luck, gpiccoli On 16:01-20230504, Wadim Egorov wrote: > The phyCORE-AM62x [1] is a SoM (System on Module) featuring TI's AM62x SoC. > It can be used in combination with different carrier boards. > This module can come with different sizes and models for > DDR, eMMC, SPI NOR Flash and various SoCs from the AM62x family. > > A development Kit, called phyBOARD-Lyra [2] is used as a carrier board > reference design around the AM62x SoM. > > Supported features: > * Debug UART > * SPI NOR Flash > * eMMC > * 2x Ethernet > * Micro SD card > * I2C EEPROM > * I2C RTC > * GPIO Expander > * LEDs > * USB > > For more details, see: > > [1] Product page SoM: https://www.phytec.com/product/phycore-am62x > [2] Product page CB: https://www.phytec.com/product/phyboard-am62x > > Signed-off-by: Wadim Egorov <w.egorov@phytec.de> > --- > arch/arm64/boot/dts/ti/Makefile | 1 + > .../boot/dts/ti/k3-am62-phycore-som.dtsi | 324 ++++++++++++++++++ > .../dts/ti/k3-am625-phyboard-lyra-rdk.dts | 267 +++++++++++++++ Just wondering: if the carrier board can easily work with different SoMs.. in which case, we could do overlay to create the som + carrier overlay to create rdk dtb - this might allow the scheme to scale to additional SoMs and carrier combinations.. and the SoM dtb could be sufficient for something like a bootloader. > 3 files changed, 592 insertions(+) > create mode 100644 arch/arm64/boot/dts/ti/k3-am62-phycore-som.dtsi > create mode 100644 arch/arm64/boot/dts/ti/k3-am625-phyboard-lyra-rdk.dts > > diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makefile > index c83c9d772b81..9388dc481d7d 100644 > --- a/arch/arm64/boot/dts/ti/Makefile > +++ b/arch/arm64/boot/dts/ti/Makefile > @@ -10,6 +10,7 @@ > > # Boards with AM62x SoC > dtb-$(CONFIG_ARCH_K3) += k3-am625-beagleplay.dtb > +dtb-$(CONFIG_ARCH_K3) += k3-am625-phyboard-lyra-rdk.dtb > dtb-$(CONFIG_ARCH_K3) += k3-am625-sk.dtb > dtb-$(CONFIG_ARCH_K3) += k3-am62-lp-sk.dtb > > diff --git a/arch/arm64/boot/dts/ti/k3-am62-phycore-som.dtsi b/arch/arm64/boot/dts/ti/k3-am62-phycore-som.dtsi > new file mode 100644 > index 000000000000..32264296c8c6 > --- /dev/null > +++ b/arch/arm64/boot/dts/ti/k3-am62-phycore-som.dtsi > @@ -0,0 +1,324 @@ > +// SPDX-License-Identifier: GPL-2.0 > +/* > + * Copyright (C) 2022 - 2023 PHYTEC Messtechnik GmbH > + * Author: Wadim Egorov <w.egorov@phytec.de> > + * > + * Product homepage: > + * https://www.phytec.com/product/phycore-am62x > + */ > + > +#include <dt-bindings/gpio/gpio.h> > +#include <dt-bindings/leds/common.h> > +#include <dt-bindings/net/ti-dp83867.h> > + > +/ { > + model = "PHYTEC phyCORE-AM62x"; > + compatible = "phytec,am62-phycore-som", "ti,am625"; > + > + aliases { > + ethernet0 = &cpsw_port1; > + gpio0 = &main_gpio0; > + gpio1 = &main_gpio1; > + i2c0 = &main_i2c0; > + mmc0 = &sdhci0; > + rtc0 = &i2c_som_rtc; > + rtc1 = &wkup_rtc0; > + spi0 = &ospi0; > + }; > + > + memory@80000000 { > + device_type = "memory"; > + reg = <0x00000000 0x80000000 0x00000000 0x80000000>; > + }; > + > + reserved_memory: reserved-memory { > + #address-cells = <2>; > + #size-cells = <2>; > + ranges; > + > + ramoops@9ca00000 { > + compatible = "ramoops"; > + reg = <0x00 0x9ca00000 0x00 0x00100000>; > + record-size = <0x8000>; > + console-size = <0x8000>; > + ftrace-size = <0x00>; > + pmsg-size = <0x8000>; > + }; > + > + secure_tfa_ddr: tfa@9e780000 { > + reg = <0x00 0x9e780000 0x00 0x80000>; > + alignment = <0x1000>; > + no-map; > + }; > + > + secure_ddr: optee@9e800000 { > + reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */ > + alignment = <0x1000>; > + no-map; > + }; > + > + wkup_r5fss0_core0_dma_memory_region: r5f-dma-memory@9db00000 { > + compatible = "shared-dma-pool"; > + reg = <0x00 0x9db00000 0x00 0x00c00000>; > + no-map; > + }; > + }; > + > + vcc_5v0_som: regulator-vcc-5v0-som { > + compatible = "regulator-fixed"; > + regulator-name = "VCC_5V0_SOM"; > + regulator-min-microvolt = <5000000>; > + regulator-max-microvolt = <5000000>; > + regulator-always-on; > + regulator-boot-on; > + }; > + > + vdd_1v8: regulator-vdd-1v8 { > + compatible = "regulator-fixed"; > + regulator-name = "VDD_1V8"; > + regulator-min-microvolt = <1800000>; > + regulator-max-microvolt = <1800000>; > + vin-supply = <&vcc_5v0_som>; > + regulator-always-on; > + regulator-boot-on; > + }; > + > + leds { > + compatible = "gpio-leds"; > + pinctrl-names = "default"; > + pinctrl-0 = <&leds_pins_default>; > + > + led-0 { > + color = <LED_COLOR_ID_GREEN>; > + gpios = <&main_gpio0 13 GPIO_ACTIVE_HIGH>; > + linux,default-trigger = "heartbeat"; > + function = LED_FUNCTION_HEARTBEAT; > + }; > + }; > +}; > + > +&main_pmx0 { > + leds_pins_default: leds-pins-default { > + pinctrl-single,pins = < > + AM62X_IOPAD(0x034, PIN_OUTPUT, 7) /* (H21) OSPI0_CSN2.GPIO0_13 */ > + >; > + }; > + > + main_i2c0_pins_default: main-i2c0-pins-default { > + pinctrl-single,pins = < > + AM62X_IOPAD(0x1e0, PIN_INPUT_PULLUP, 0) /* (B16) I2C0_SCL */ > + AM62X_IOPAD(0x1e4, PIN_INPUT_PULLUP, 0) /* (A16) I2C0_SDA */ > + >; > + }; > + > + main_mdio1_pins_default: main_mdio1-pins-default { > + pinctrl-single,pins = < > + AM62X_IOPAD(0x160, PIN_OUTPUT, 0) /* (AD24) MDIO0_MDC */ > + AM62X_IOPAD(0x15c, PIN_INPUT, 0) /* (AB22) MDIO0_MDIO */ > + >; > + }; > + > + main_mmc0_pins_default: main-mmc0-pins-default { > + pinctrl-single,pins = < > + AM62X_IOPAD(0x220, PIN_INPUT_PULLUP, 0) /* (Y3) MMC0_CMD */ > + AM62X_IOPAD(0x218, PIN_INPUT_PULLDOWN, 0) /* (AB1) MMC0_CLK */ > + AM62X_IOPAD(0x214, PIN_INPUT_PULLUP, 0) /* (AA2) MMC0_DAT0 */ > + AM62X_IOPAD(0x210, PIN_INPUT_PULLUP, 0) /* (AA1) MMC0_DAT1 */ > + AM62X_IOPAD(0x20c, PIN_INPUT_PULLUP, 0) /* (AA3) MMC0_DAT2 */ > + AM62X_IOPAD(0x208, PIN_INPUT_PULLUP, 0) /* (Y4) MMC0_DAT3 */ > + AM62X_IOPAD(0x204, PIN_INPUT_PULLUP, 0) /* (AB2) MMC0_DAT4 */ > + AM62X_IOPAD(0x200, PIN_INPUT_PULLUP, 0) /* (AC1) MMC0_DAT5 */ > + AM62X_IOPAD(0x1fc, PIN_INPUT_PULLUP, 0) /* (AD2) MMC0_DAT6 */ > + AM62X_IOPAD(0x1f8, PIN_INPUT_PULLUP, 0) /* (AC2) MMC0_DAT7 */ > + >; > + }; > + > + main_rgmii1_pins_default: main-rgmii1-pins-default { > + pinctrl-single,pins = < > + AM62X_IOPAD(0x14c, PIN_INPUT, 0) /* (AB17) RGMII1_RD0 */ > + AM62X_IOPAD(0x150, PIN_INPUT, 0) /* (AC17) RGMII1_RD1 */ > + AM62X_IOPAD(0x154, PIN_INPUT, 0) /* (AB16) RGMII1_RD2 */ > + AM62X_IOPAD(0x158, PIN_INPUT, 0) /* (AA15) RGMII1_RD3 */ > + AM62X_IOPAD(0x148, PIN_INPUT, 0) /* (AD17) RGMII1_RXC */ > + AM62X_IOPAD(0x144, PIN_INPUT, 0) /* (AE17) RGMII1_RX_CTL */ > + AM62X_IOPAD(0x134, PIN_OUTPUT, 0) /* (AE20) RGMII1_TD0 */ > + AM62X_IOPAD(0x138, PIN_OUTPUT, 0) /* (AD20) RGMII1_TD1 */ > + AM62X_IOPAD(0x13c, PIN_OUTPUT, 0) /* (AE18) RGMII1_TD2 */ > + AM62X_IOPAD(0x140, PIN_OUTPUT, 0) /* (AD18) RGMII1_TD3 */ > + AM62X_IOPAD(0x130, PIN_OUTPUT, 0) /* (AE19) RGMII1_TXC */ > + AM62X_IOPAD(0x12c, PIN_OUTPUT, 0) /* (AD19) RGMII1_TX_CTL */ > + >; > + }; > + > + ospi0_pins_default: ospi0-pins-default { > + pinctrl-single,pins = < > + AM62X_IOPAD(0x000, PIN_OUTPUT, 0) /* (H24) OSPI0_CLK */ > + AM62X_IOPAD(0x02c, PIN_OUTPUT, 0) /* (F23) OSPI0_CSn0 */ > + AM62X_IOPAD(0x00c, PIN_INPUT, 0) /* (E25) OSPI0_D0 */ > + AM62X_IOPAD(0x010, PIN_INPUT, 0) /* (G24) OSPI0_D1 */ > + AM62X_IOPAD(0x014, PIN_INPUT, 0) /* (F25) OSPI0_D2 */ > + AM62X_IOPAD(0x018, PIN_INPUT, 0) /* (F24) OSPI0_D3 */ > + AM62X_IOPAD(0x01c, PIN_INPUT, 0) /* (J23) OSPI0_D4 */ > + AM62X_IOPAD(0x020, PIN_INPUT, 0) /* (J25) OSPI0_D5 */ > + AM62X_IOPAD(0x024, PIN_INPUT, 0) /* (H25) OSPI0_D6 */ > + AM62X_IOPAD(0x028, PIN_INPUT, 0) /* (J22) OSPI0_D7 */ > + AM62X_IOPAD(0x008, PIN_INPUT, 0) /* (J24) OSPI0_DQS */ > + >; > + }; > + > + pmic_irq_pins_default: pmic-irq-pins-default { > + pinctrl-single,pins = < > + AM62X_IOPAD(0x01f4, PIN_INPUT, 0) /* (D16) EXTINTn */ > + >; > + }; > +}; > + > +&cpsw3g { > + pinctrl-names = "default"; > + pinctrl-0 = <&main_rgmii1_pins_default>; > +}; > + > +&cpsw_port1 { > + phy-mode = "rgmii-rxid"; > + phy-handle = <&cpsw3g_phy1>; > +}; > + > +&cpsw3g_mdio { > + pinctrl-names = "default"; > + pinctrl-0 = <&main_mdio1_pins_default>; > + status = "okay"; > + > + cpsw3g_phy1: ethernet-phy@1 { > + compatible = "ethernet-phy-id2000.a231", "ethernet-phy-ieee802.3-c22"; > + reg = <1>; > + ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; > + ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; > + }; > +}; > + > +&main_i2c0 { > + pinctrl-names = "default"; > + pinctrl-0 = <&main_i2c0_pins_default>; > + clock-frequency = <400000>; > + status = "okay"; > + > + pmic@30 { > + compatible = "ti,tps65219"; > + reg = <0x30>; > + buck1-supply = <&vcc_5v0_som>; > + buck2-supply = <&vcc_5v0_som>; > + buck3-supply = <&vcc_5v0_som>; > + ldo1-supply = <&vdd_3v3>; > + ldo2-supply = <&vdd_1v8>; > + ldo3-supply = <&vcc_5v0_som>; > + ldo4-supply = <&vcc_5v0_som>; > + > + pinctrl-names = "default"; > + pinctrl-0 = <&pmic_irq_pins_default>; > + interrupt-parent = <&gic500>; > + interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; > + interrupt-controller; > + #interrupt-cells = <1>; > + > + ti,power-button; > + system-power-controller; > + > + regulators { > + vdd_core: buck1 { > + regulator-name = "VDD_CORE"; > + regulator-min-microvolt = <750000>; > + regulator-max-microvolt = <750000>; > + regulator-boot-on; > + regulator-always-on; > + }; > + > + vdd_3v3: buck2 { > + regulator-name = "VDD_3V3"; > + regulator-min-microvolt = <3300000>; > + regulator-max-microvolt = <3300000>; > + regulator-boot-on; > + regulator-always-on; > + }; > + > + vdd_ddr4: buck3 { > + regulator-name = "VDD_DDR4"; > + regulator-min-microvolt = <1200000>; > + regulator-max-microvolt = <1200000>; > + regulator-boot-on; > + regulator-always-on; > + }; > + > + vddshv5_sdio: ldo1 { > + regulator-name = "VDDSHV5_SDIO"; > + regulator-min-microvolt = <3300000>; > + regulator-max-microvolt = <3300000>; > + regulator-allow-bypass; > + regulator-boot-on; > + regulator-always-on; > + }; > + > + vddr_core: ldo2 { > + regulator-name = "VDDR_CORE"; > + regulator-min-microvolt = <850000>; > + regulator-max-microvolt = <850000>; > + regulator-boot-on; > + regulator-always-on; > + }; > + > + vdda_1v8: ldo3 { > + regulator-name = "VDDA_1V8"; > + regulator-min-microvolt = <1800000>; > + regulator-max-microvolt = <1800000>; > + regulator-boot-on; > + regulator-always-on; > + }; > + > + vdd_2v5: ldo4 { > + regulator-name = "VDD_2V5"; > + regulator-min-microvolt = <2500000>; > + regulator-max-microvolt = <2500000>; > + regulator-boot-on; > + regulator-always-on; > + }; > + }; > + }; > + > + eeprom@50 { > + compatible = "atmel,24c32"; > + pagesize = <32>; > + reg = <0x50>; > + }; > + > + i2c_som_rtc: rtc@52 { > + compatible = "microcrystal,rv3028"; > + reg = <0x52>; > + }; > +}; > + > +&ospi0 { > + pinctrl-names = "default"; > + pinctrl-0 = <&ospi0_pins_default>; > + status = "okay"; > + > + serial_flash: flash@0 { > + compatible = "jedec,spi-nor"; > + reg = <0x0>; > + spi-tx-bus-width = <8>; > + spi-rx-bus-width = <8>; > + spi-max-frequency = <25000000>; > + cdns,tshsl-ns = <60>; > + cdns,tsd2d-ns = <60>; > + cdns,tchsh-ns = <60>; > + cdns,tslch-ns = <60>; > + cdns,read-delay = <0>; > + }; > +}; > + > +&sdhci0 { > + pinctrl-names = "default"; > + pinctrl-0 = <&main_mmc0_pins_default>; > + ti,driver-strength-ohm = <50>; > + disable-wp; > + non-removable; > + status = "okay"; > +}; > diff --git a/arch/arm64/boot/dts/ti/k3-am625-phyboard-lyra-rdk.dts b/arch/arm64/boot/dts/ti/k3-am625-phyboard-lyra-rdk.dts > new file mode 100644 > index 000000000000..bad26b554f98 > --- /dev/null > +++ b/arch/arm64/boot/dts/ti/k3-am625-phyboard-lyra-rdk.dts > @@ -0,0 +1,267 @@ > +// SPDX-License-Identifier: GPL-2.0 > +/* > + * Copyright (C) 2022 - 2023 PHYTEC Messtechnik GmbH > + * Author: Wadim Egorov <w.egorov@phytec.de> > + * > + * Product homepage: > + * https://www.phytec.com/product/phyboard-am62x > + */ > + > +#include <dt-bindings/gpio/gpio.h> > +#include <dt-bindings/input/input.h> > +#include <dt-bindings/leds/common.h> > +#include <dt-bindings/net/ti-dp83867.h> > +#include "k3-am625.dtsi" > +#include "k3-am62-phycore-som.dtsi" > + > +/ { > + compatible = "phytec,am625-phyboard-lyra-rdk", > + "phytec,am62-phycore-som", "ti,am625"; > + model = "PHYTEC phyBOARD-Lyra AM625"; > + > + aliases { > + serial2 = &main_uart0; > + serial3 = &main_uart1; > + mmc1 = &sdhci1; > + usb0 = &usb0; > + usb1 = &usb1; > + ethernet1 = &cpsw_port2; > + }; > + > + can_tc1: can-phy0 { > + compatible = "ti,tcan1042"; > + #phy-cells = <0>; > + max-bitrate = <5000000>; > + standby-gpios = <&gpio_exp 1 GPIO_ACTIVE_HIGH>; > + }; > + > + keys { > + compatible = "gpio-keys"; > + autorepeat; > + pinctrl-names = "default"; > + pinctrl-0 = <&gpio_keys_pins_default>; > + > + key-home { > + label = "home"; > + linux,code = <KEY_HOME>; > + gpios = <&main_gpio1 23 GPIO_ACTIVE_HIGH>; > + }; > + > + key-menu { > + label = "menu"; > + linux,code = <KEY_MENU>; > + gpios = <&gpio_exp 4 GPIO_ACTIVE_HIGH>; > + }; > + }; > + > + leds { > + compatible = "gpio-leds"; > + pinctrl-names = "default"; > + pinctrl-0 = <&leds_pins_default &user_leds_pins_default>; > + > + led-1 { > + gpios = <&main_gpio0 32 GPIO_ACTIVE_HIGH>; > + linux,default-trigger = "mmc0"; > + }; > + > + led-2 { > + gpios = <&gpio_exp 2 GPIO_ACTIVE_HIGH>; > + linux,default-trigger = "mmc1"; > + }; > + }; > + > + vcc_3v3_mmc: regulator-vcc-3v3-mmc { > + compatible = "regulator-fixed"; > + regulator-name = "VCC_3V3_MMC"; > + regulator-min-microvolt = <3300000>; > + regulator-max-microvolt = <3300000>; > + regulator-always-on; > + regulator-boot-on; > + }; > +}; > + > +&main_pmx0 { > + gpio_keys_pins_default: gpio-keys-pins-default { > + pinctrl-single,pins = < > + AM62X_IOPAD(0x1d4, PIN_INPUT, 7) /* (B15) UART0_RTSn.GPIO1_23 */ > + >; > + }; > + > + gpio_exp_int_pins_default: gpio-exp-int-pins-default { > + pinctrl-single,pins = < > + AM62X_IOPAD(0x244, PIN_INPUT, 7) /* (C17) MMC1_SDWP.GPIO1_49 */ > + >; > + }; > + > + main_i2c1_pins_default: main-i2c1-pins-default { > + pinctrl-single,pins = < > + AM62X_IOPAD(0x1e8, PIN_INPUT_PULLUP, 0) /* (B17) I2C1_SCL */ > + AM62X_IOPAD(0x1ec, PIN_INPUT_PULLUP, 0) /* (A17) I2C1_SDA */ > + >; > + }; > + > + main_mcan0_pins_default: main-mcan0-pins-default { > + pinctrl-single,pins = < > + AM62X_IOPAD(0x1dc, PIN_INPUT, 0) /* (E15) MCAN0_RX */ > + AM62X_IOPAD(0x1d8, PIN_OUTPUT, 0) /* (C15) MCAN0_TX */ > + >; > + }; > + > + main_mmc1_pins_default: main-mmc1-pins-default { > + pinctrl-single,pins = < > + AM62X_IOPAD(0x23c, PIN_INPUT_PULLUP, 0) /* (A21) MMC1_CMD */ > + AM62X_IOPAD(0x234, PIN_INPUT_PULLDOWN, 0) /* (B22) MMC1_CLK */ > + AM62X_IOPAD(0x230, PIN_INPUT_PULLUP, 0) /* (A22) MMC1_DAT0 */ > + AM62X_IOPAD(0x22c, PIN_INPUT_PULLUP, 0) /* (B21) MMC1_DAT1 */ > + AM62X_IOPAD(0x228, PIN_INPUT_PULLUP, 0) /* (C21) MMC1_DAT2 */ > + AM62X_IOPAD(0x224, PIN_INPUT_PULLUP, 0) /* (D22) MMC1_DAT3 */ > + AM62X_IOPAD(0x240, PIN_INPUT_PULLUP, 0) /* (D17) MMC1_SDCD */ > + >; > + }; > + > + main_rgmii2_pins_default: main-rgmii2-pins-default { > + pinctrl-single,pins = < > + AM62X_IOPAD(0x184, PIN_INPUT, 0) /* (AE23) RGMII2_RD0 */ > + AM62X_IOPAD(0x188, PIN_INPUT, 0) /* (AB20) RGMII2_RD1 */ > + AM62X_IOPAD(0x18c, PIN_INPUT, 0) /* (AC21) RGMII2_RD2 */ > + AM62X_IOPAD(0x190, PIN_INPUT, 0) /* (AE22) RGMII2_RD3 */ > + AM62X_IOPAD(0x180, PIN_INPUT, 0) /* (AD23) RGMII2_RXC */ > + AM62X_IOPAD(0x17c, PIN_INPUT, 0) /* (AD22) RGMII2_RX_CTL */ > + AM62X_IOPAD(0x16c, PIN_OUTPUT, 0) /* (Y18) RGMII2_TD0 */ > + AM62X_IOPAD(0x170, PIN_OUTPUT, 0) /* (AA18) RGMII2_TD1 */ > + AM62X_IOPAD(0x174, PIN_OUTPUT, 0) /* (AD21) RGMII2_TD2 */ > + AM62X_IOPAD(0x178, PIN_OUTPUT, 0) /* (AC20) RGMII2_TD3 */ > + AM62X_IOPAD(0x168, PIN_OUTPUT, 0) /* (AE21) RGMII2_TXC */ > + AM62X_IOPAD(0x164, PIN_OUTPUT, 0) /* (AA19) RGMII2_TX_CTL */ > + >; > + }; > + > + main_uart0_pins_default: main-uart0-pins-default { > + pinctrl-single,pins = < > + AM62X_IOPAD(0x1c8, PIN_INPUT, 0) /* (D14) UART0_RXD */ > + AM62X_IOPAD(0x1cc, PIN_OUTPUT, 0) /* (E14) UART0_TXD */ > + >; > + }; > + > + main_uart1_pins_default: main-uart1-pins-default { > + pinctrl-single,pins = < > + AM62X_IOPAD(0x194, PIN_INPUT, 2) /* (B19) MCASP0_AXR3.UART1_CTSn */ > + AM62X_IOPAD(0x198, PIN_OUTPUT, 2) /* (A19) MCASP0_AXR2.UART1_RTSn */ > + AM62X_IOPAD(0x1ac, PIN_INPUT, 2) /* (E19) MCASP0_AFSR.UART1_RXD */ > + AM62X_IOPAD(0x1b0, PIN_OUTPUT, 2) /* (A20) MCASP0_ACLKR.UART1_TXD */ > + >; > + }; > + > + main_usb1_pins_default: main-usb1-pins-default { > + pinctrl-single,pins = < > + AM62X_IOPAD(0x258, PIN_OUTPUT, 0) /* (F18) USB1_DRVVBUS */ > + >; > + }; > + > + user_leds_pins_default: user-leds-pins-default { > + pinctrl-single,pins = < > + AM62X_IOPAD(0x084, PIN_OUTPUT, 7) /* (L23) GPMC0_ADVn_ALE.GPIO0_32 */ > + >; > + }; > +}; > + > +&cpsw3g { > + pinctrl-names = "default"; > + pinctrl-0 = <&main_rgmii1_pins_default > + &main_rgmii2_pins_default>; > +}; > + > +&cpsw_port2 { > + phy-mode = "rgmii-rxid"; > + phy-handle = <&cpsw3g_phy3>; > +}; > + > +&cpsw3g_mdio { > + cpsw3g_phy3: ethernet-phy@3 { > + compatible = "ethernet-phy-id2000.a231", "ethernet-phy-ieee802.3-c22"; > + reg = <3>; > + ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; > + ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; > + }; > +}; > + > +&main_i2c1 { > + pinctrl-names = "default"; > + pinctrl-0 = <&main_i2c1_pins_default>; > + clock-frequency = <400000>; > + status = "okay"; > + > + gpio_exp: gpio-expander@21 { > + pinctrl-names = "default"; > + pinctrl-0 = <&gpio_exp_int_pins_default>; > + compatible = "nxp,pcf8574"; > + reg = <0x21>; > + interrupt-parent = <&main_gpio1>; > + interrupts = <49 0>; > + #gpio-cells = <2>; > + gpio-controller; > + interrupt-controller; > + #interrupt-cells = <2>; > + gpio-line-names = "GPIO0_HDMI_RST", "GPIO1_CAN0_nEN", > + "GPIO2_LED2", "GPIO3_LVDS_GPIO", > + "GPIO4_BUT2", "GPIO5_LVDS_BKLT_EN", > + "GPIO6_ETH1_USER_RESET", "GPIO7_AUDIO_USER_RESET"; > + }; > + > + eeprom@51 { > + compatible = "atmel,24c02"; > + pagesize = <16>; > + reg = <0x51>; > + }; > +}; > + > +&main_mcan0 { > + pinctrl-names = "default"; > + pinctrl-0 = <&main_mcan0_pins_default>; > + phys = <&can_tc1>; > + status = "okay"; > +}; > + > +&main_uart0 { > + pinctrl-names = "default"; > + pinctrl-0 = <&main_uart0_pins_default>; > + status = "okay"; > +}; > + > +&main_uart1 { > + pinctrl-names = "default"; > + pinctrl-0 = <&main_uart1_pins_default>; > + /* Main UART1 may be used by TIFS firmware */ > + status = "okay"; > +}; > + > +&sdhci1 { > + vmmc-supply = <&vcc_3v3_mmc>; > + vqmmc-supply = <&vddshv5_sdio>; > + pinctrl-names = "default"; > + pinctrl-0 = <&main_mmc1_pins_default>; > + ti,driver-strength-ohm = <50>; > + disable-wp; > + no-1-8-v; > + status = "okay"; > +}; > + > +&usbss0 { > + ti,vbus-divider; > + status = "okay"; > +}; > + > +&usbss1 { > + ti,vbus-divider; > + status = "okay"; > +}; > + > +&usb0 { > + dr_mode = "peripheral"; > +}; > + > +&usb1 { > + dr_mode = "host"; > + pinctrl-names = "default"; > + pinctrl-0 = <&main_usb1_pins_default>; > +}; > -- > 2.25.1 > -- Regards, Nishanth Menon Key (0xDDB5849D1736249D) / Fingerprint: F8A2 8693 54EB 8232 17A3 1A34 DDB5 849D 1736 249D ^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH 2/2] arm64: dts: ti: Add basic support for phyBOARD-Lyra-AM625 2023-05-04 14:26 ` Nishanth Menon @ 2023-05-05 9:39 ` Tony Lindgren 2023-05-05 13:38 ` Wadim Egorov 0 siblings, 1 reply; 10+ messages in thread From: Tony Lindgren @ 2023-05-05 9:39 UTC (permalink / raw) To: Nishanth Menon Cc: Wadim Egorov, linux-kernel, devicetree, linux-arm-kernel, linux-hardening, upstream, vigneshr, kristo, robh+dt, krzysztof.kozlowski+dt, keescook, tony.luck, gpiccoli * Nishanth Menon <nm@ti.com> [230504 14:33]: > Just wondering: if the carrier board can easily work with different > SoMs.. in which case, we could do overlay to create the som + carrier > overlay to create rdk dtb - this might allow the scheme to scale to > additional SoMs and carrier combinations.. and the SoM dtb could be > sufficient for something like a bootloader. It might be best to limit the overlay usage to devices that might see dual use on the carrier board.. Not sure if setting up the entire carrier board makes sense as an overlay :) Not sure if folks want to debug boot issues on a remote server for example if an overlay is needed to boot with Ethernet :) Regards, Tony ^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH 2/2] arm64: dts: ti: Add basic support for phyBOARD-Lyra-AM625 2023-05-05 9:39 ` Tony Lindgren @ 2023-05-05 13:38 ` Wadim Egorov 2023-05-08 8:41 ` Tony Lindgren 0 siblings, 1 reply; 10+ messages in thread From: Wadim Egorov @ 2023-05-05 13:38 UTC (permalink / raw) To: Tony Lindgren, Nishanth Menon Cc: linux-kernel, devicetree, linux-arm-kernel, linux-hardening, upstream, vigneshr, kristo, robh+dt, krzysztof.kozlowski+dt, keescook, tony.luck, gpiccoli Am 05.05.23 um 11:39 schrieb Tony Lindgren: > * Nishanth Menon <nm@ti.com> [230504 14:33]: >> Just wondering: if the carrier board can easily work with different >> SoMs.. in which case, we could do overlay to create the som + carrier >> overlay to create rdk dtb - this might allow the scheme to scale to >> additional SoMs and carrier combinations.. and the SoM dtb could be >> sufficient for something like a bootloader. > It might be best to limit the overlay usage to devices that might see > dual use on the carrier board.. Not sure if setting up the entire > carrier board makes sense as an overlay :) Not sure if folks want to > debug boot issues on a remote server for example if an overlay is > needed to boot with Ethernet :) Our idea is to create overlays for SoM variants, e.g. an overlay for a SoM without SPI NOR flash populated. If we want to reuse a carrier board, we could factor out the carrier board dts into a dtsi file and provide the needed combinations in form of different dts files. In the bootloader world the situation is a bit different. Here we would like to have a universal phycore_am62x "board" that should be able to handle most carrier board designs using that SoM. And since u-boot is moving towards having a single source of device trees, this concept will probably no longer work anymore. So your idea with a SoM dtb sounds interesting. I wonder what ideas other SoM vendors have or how it is handled on other architectures. Regards, Wadim > > Regards, > > Tony ^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH 2/2] arm64: dts: ti: Add basic support for phyBOARD-Lyra-AM625 2023-05-05 13:38 ` Wadim Egorov @ 2023-05-08 8:41 ` Tony Lindgren 0 siblings, 0 replies; 10+ messages in thread From: Tony Lindgren @ 2023-05-08 8:41 UTC (permalink / raw) To: Wadim Egorov Cc: Nishanth Menon, linux-kernel, devicetree, linux-arm-kernel, linux-hardening, upstream, vigneshr, kristo, robh+dt, krzysztof.kozlowski+dt, keescook, tony.luck, gpiccoli * Wadim Egorov <w.egorov@phytec.de> [230505 13:38]: > > Am 05.05.23 um 11:39 schrieb Tony Lindgren: > > * Nishanth Menon <nm@ti.com> [230504 14:33]: > > > Just wondering: if the carrier board can easily work with different > > > SoMs.. in which case, we could do overlay to create the som + carrier > > > overlay to create rdk dtb - this might allow the scheme to scale to > > > additional SoMs and carrier combinations.. and the SoM dtb could be > > > sufficient for something like a bootloader. > > It might be best to limit the overlay usage to devices that might see > > dual use on the carrier board.. Not sure if setting up the entire > > carrier board makes sense as an overlay :) Not sure if folks want to > > debug boot issues on a remote server for example if an overlay is > > needed to boot with Ethernet :) > > Our idea is to create overlays for SoM variants, e.g. an overlay for a SoM > without SPI NOR flash populated. > If we want to reuse a carrier board, we could factor out the carrier board > dts into a dtsi file and provide the needed combinations in form of > different dts files. It probably makes sens to limit the overlays for optional features that are not hardwired. > In the bootloader world the situation is a bit different. > Here we would like to have a universal phycore_am62x "board" that should be > able to handle most carrier board designs using that SoM. And since u-boot > is moving towards having a single source of device trees, this concept will > probably no longer work anymore. So your idea with a SoM dtb sounds > interesting. > I wonder what ideas other SoM vendors have or how it is handled on other > architectures. I'm not sure what the best way to organize things is if there are many SoM and carrier board variants, I guess it depends on the number of the possible permutations :) Regards, Tony ^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH 2/2] arm64: dts: ti: Add basic support for phyBOARD-Lyra-AM625 2023-05-04 14:01 ` [PATCH 2/2] arm64: dts: ti: Add basic support for phyBOARD-Lyra-AM625 Wadim Egorov 2023-05-04 14:26 ` Nishanth Menon @ 2023-05-05 9:41 ` Tony Lindgren 1 sibling, 0 replies; 10+ messages in thread From: Tony Lindgren @ 2023-05-05 9:41 UTC (permalink / raw) To: Wadim Egorov Cc: linux-kernel, devicetree, linux-arm-kernel, linux-hardening, upstream, nm, vigneshr, kristo, robh+dt, krzysztof.kozlowski+dt, keescook, tony.luck, gpiccoli * Wadim Egorov <w.egorov@phytec.de> [230504 14:12]: > The phyCORE-AM62x [1] is a SoM (System on Module) featuring TI's AM62x SoC. > It can be used in combination with different carrier boards. > This module can come with different sizes and models for > DDR, eMMC, SPI NOR Flash and various SoCs from the AM62x family. The patch looks good to me: Reviewed-by: Tony Lindgren <tony@atomide.com> ^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH 1/2] dt-bindings: arm: ti: Add bindings for PHYTEC AM62x based hardware 2023-05-04 14:01 [PATCH 1/2] dt-bindings: arm: ti: Add bindings for PHYTEC AM62x based hardware Wadim Egorov 2023-05-04 14:01 ` [PATCH 2/2] arm64: dts: ti: Add basic support for phyBOARD-Lyra-AM625 Wadim Egorov @ 2023-05-05 6:53 ` Krzysztof Kozlowski 2023-05-05 9:40 ` Tony Lindgren 2023-06-15 10:45 ` Vignesh Raghavendra 3 siblings, 0 replies; 10+ messages in thread From: Krzysztof Kozlowski @ 2023-05-05 6:53 UTC (permalink / raw) To: Wadim Egorov, linux-kernel, devicetree, linux-arm-kernel, linux-hardening Cc: upstream, nm, vigneshr, kristo, robh+dt, krzysztof.kozlowski+dt, keescook, tony.luck, gpiccoli On 04/05/2023 16:01, Wadim Egorov wrote: > Add devicetree bindings for AM62x based phyCORE-AM62 SoM > and phyBOARD-Lyra RDK. If there is going to be new version: Subject: drop second/last, redundant "bindings". The "dt-bindings" prefix is already stating that these are bindings. > > Signed-off-by: Wadim Egorov <w.egorov@phytec.de> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Best regards, Krzysztof ^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH 1/2] dt-bindings: arm: ti: Add bindings for PHYTEC AM62x based hardware 2023-05-04 14:01 [PATCH 1/2] dt-bindings: arm: ti: Add bindings for PHYTEC AM62x based hardware Wadim Egorov 2023-05-04 14:01 ` [PATCH 2/2] arm64: dts: ti: Add basic support for phyBOARD-Lyra-AM625 Wadim Egorov 2023-05-05 6:53 ` [PATCH 1/2] dt-bindings: arm: ti: Add bindings for PHYTEC AM62x based hardware Krzysztof Kozlowski @ 2023-05-05 9:40 ` Tony Lindgren 2023-06-15 10:45 ` Vignesh Raghavendra 3 siblings, 0 replies; 10+ messages in thread From: Tony Lindgren @ 2023-05-05 9:40 UTC (permalink / raw) To: Wadim Egorov Cc: linux-kernel, devicetree, linux-arm-kernel, linux-hardening, upstream, nm, vigneshr, kristo, robh+dt, krzysztof.kozlowski+dt, keescook, tony.luck, gpiccoli * Wadim Egorov <w.egorov@phytec.de> [230504 14:08]: > Add devicetree bindings for AM62x based phyCORE-AM62 SoM > and phyBOARD-Lyra RDK. Reviewed-by: Tony Lindgren <tony@atomide.com> ^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH 1/2] dt-bindings: arm: ti: Add bindings for PHYTEC AM62x based hardware 2023-05-04 14:01 [PATCH 1/2] dt-bindings: arm: ti: Add bindings for PHYTEC AM62x based hardware Wadim Egorov ` (2 preceding siblings ...) 2023-05-05 9:40 ` Tony Lindgren @ 2023-06-15 10:45 ` Vignesh Raghavendra 3 siblings, 0 replies; 10+ messages in thread From: Vignesh Raghavendra @ 2023-06-15 10:45 UTC (permalink / raw) To: linux-kernel, devicetree, linux-arm-kernel, linux-hardening, Wadim Egorov Cc: Vignesh Raghavendra, upstream, nm, kristo, robh+dt, krzysztof.kozlowski+dt, keescook, tony.luck, gpiccoli Hi Wadim Egorov, On Thu, 04 May 2023 16:01:42 +0200, Wadim Egorov wrote: > Add devicetree bindings for AM62x based phyCORE-AM62 SoM > and phyBOARD-Lyra RDK. > > I have applied the following to branch ti-k3-dts-next on [1]. Thank you! [1/2] dt-bindings: arm: ti: Add bindings for PHYTEC AM62x based hardware commit: 94a58c5f131d7f0cf735af24574b7626aab77ab1 [2/2] arm64: dts: ti: Add basic support for phyBOARD-Lyra-AM625 commit: 0ad58871f63cbc4a03360bebd4ccc967bd9346db All being well this means that it will be integrated into the linux-next tree (usually sometime in the next 24 hours) and sent up the chain during the next merge window (or sooner if it is a relevant bug fix), however if problems are discovered then the patch may be dropped or reverted. You may get further e-mails resulting from automated or manual testing and review of the tree, please engage with people reporting problems and send followup patches addressing any issues that are reported if needed. If any updates are required or you are submitting further changes they should be sent as incremental updates against current git, existing patches will not be replaced. Please add any relevant lists and maintainers to the CCs when replying to this mail. [1] https://git.kernel.org/pub/scm/linux/kernel/git/ti/linux.git -- Vignesh ^ permalink raw reply [flat|nested] 10+ messages in thread
end of thread, other threads:[~2023-06-15 10:45 UTC | newest] Thread overview: 10+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2023-05-04 14:01 [PATCH 1/2] dt-bindings: arm: ti: Add bindings for PHYTEC AM62x based hardware Wadim Egorov 2023-05-04 14:01 ` [PATCH 2/2] arm64: dts: ti: Add basic support for phyBOARD-Lyra-AM625 Wadim Egorov 2023-05-04 14:26 ` Nishanth Menon 2023-05-05 9:39 ` Tony Lindgren 2023-05-05 13:38 ` Wadim Egorov 2023-05-08 8:41 ` Tony Lindgren 2023-05-05 9:41 ` Tony Lindgren 2023-05-05 6:53 ` [PATCH 1/2] dt-bindings: arm: ti: Add bindings for PHYTEC AM62x based hardware Krzysztof Kozlowski 2023-05-05 9:40 ` Tony Lindgren 2023-06-15 10:45 ` Vignesh Raghavendra
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