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From: Jisheng Zhang <jszhang@kernel.org>
To: Thomas Gleixner <tglx@linutronix.de>,
	Marc Zyngier <maz@kernel.org>, Rob Herring <robh+dt@kernel.org>,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
	Conor Dooley <conor+dt@kernel.org>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	Albert Ou <aou@eecs.berkeley.edu>
Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
	linux-riscv@lists.infradead.org, Guo Ren <guoren@kernel.org>
Subject: [PATCH 4/5] riscv: dts: thead: add sipeed Lichee Pi 4A board device tree
Date: Mon,  8 May 2023 02:23:03 +0800	[thread overview]
Message-ID: <20230507182304.2934-5-jszhang@kernel.org> (raw)
In-Reply-To: <20230507182304.2934-1-jszhang@kernel.org>

Sipeed's Lichee Pi 4A development board uses Lichee Module 4A core
module which is powered by T-HEAD's light(a.k.a TH1520) SoC. Add
minimal device tree files for the core module and the development
board.

Support basic uart/gpio/dmac drivers, so supports booting to a basic
shell.

Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
---
 arch/riscv/boot/dts/Makefile                  |  1 +
 arch/riscv/boot/dts/thead/Makefile            |  2 +
 .../dts/thead/light-lichee-module-4a.dtsi     | 38 +++++++++++++++++++
 .../boot/dts/thead/light-lichee-pi-4a.dts     | 32 ++++++++++++++++
 4 files changed, 73 insertions(+)
 create mode 100644 arch/riscv/boot/dts/thead/Makefile
 create mode 100644 arch/riscv/boot/dts/thead/light-lichee-module-4a.dtsi
 create mode 100644 arch/riscv/boot/dts/thead/light-lichee-pi-4a.dts

diff --git a/arch/riscv/boot/dts/Makefile b/arch/riscv/boot/dts/Makefile
index f0d9f89054f8..1e884868ccba 100644
--- a/arch/riscv/boot/dts/Makefile
+++ b/arch/riscv/boot/dts/Makefile
@@ -2,6 +2,7 @@
 subdir-y += allwinner
 subdir-y += sifive
 subdir-y += starfive
+subdir-y += thead
 subdir-y += canaan
 subdir-y += microchip
 subdir-y += renesas
diff --git a/arch/riscv/boot/dts/thead/Makefile b/arch/riscv/boot/dts/thead/Makefile
new file mode 100644
index 000000000000..9e00acc714cc
--- /dev/null
+++ b/arch/riscv/boot/dts/thead/Makefile
@@ -0,0 +1,2 @@
+# SPDX-License-Identifier: GPL-2.0
+dtb-$(CONFIG_ARCH_THEAD) += light-lichee-pi-4a.dtb
diff --git a/arch/riscv/boot/dts/thead/light-lichee-module-4a.dtsi b/arch/riscv/boot/dts/thead/light-lichee-module-4a.dtsi
new file mode 100644
index 000000000000..24c9971e0fb5
--- /dev/null
+++ b/arch/riscv/boot/dts/thead/light-lichee-module-4a.dtsi
@@ -0,0 +1,38 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2023 Jisheng Zhang <jszhang@kernel.org>
+ */
+
+/dts-v1/;
+
+#include "light.dtsi"
+
+/ {
+	model = "Sipeed Lichee Module 4A";
+	compatible = "sipeed,lichee-module-4a", "thead,light";
+
+	memory@0 {
+		device_type = "memory";
+		reg = <0x0 0x00000000 0x2 0x00000000>;
+	};
+};
+
+&osc {
+	clock-frequency = <24000000>;
+};
+
+&osc_32k {
+	clock-frequency = <32768>;
+};
+
+&apb_clk {
+	clock-frequency = <62500000>;
+};
+
+&uart_sclk {
+	clock-frequency = <100000000>;
+};
+
+&dmac0 {
+	status = "okay";
+};
diff --git a/arch/riscv/boot/dts/thead/light-lichee-pi-4a.dts b/arch/riscv/boot/dts/thead/light-lichee-pi-4a.dts
new file mode 100644
index 000000000000..4f0ba2149d2d
--- /dev/null
+++ b/arch/riscv/boot/dts/thead/light-lichee-pi-4a.dts
@@ -0,0 +1,32 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2023 Jisheng Zhang <jszhang@kernel.org>
+ */
+
+#include "light-lichee-module-4a.dtsi"
+
+/ {
+	model = "Sipeed Lichee Pi 4A";
+	compatible = "sipeed,lichee-pi-4a", "sipeed,lichee-module-4a", "thead,light";
+
+	aliases {
+		gpio0 = &gpio0;
+		gpio1 = &gpio1;
+		gpio2 = &gpio2;
+		gpio3 = &gpio3;
+		serial0 = &uart0;
+		serial1 = &uart1;
+		serial2 = &uart2;
+		serial3 = &uart3;
+		serial4 = &uart4;
+		serial5 = &uart5;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+};
+
+&uart0 {
+	status = "okay";
+};
-- 
2.40.0


  parent reply	other threads:[~2023-05-07 18:34 UTC|newest]

Thread overview: 37+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-05-07 18:22 [PATCH 0/5] Add Sipeed Lichee Pi 4A RISC-V board support Jisheng Zhang
2023-05-07 18:23 ` [PATCH 1/5] irqchip/sifive-plic: Support T-HEAD's C910 PLIC Jisheng Zhang
2023-05-07 21:18   ` Conor Dooley
2023-05-08  3:14   ` Icenowy Zheng
2023-05-08  6:52   ` Guo Ren
2023-05-08  7:07     ` Conor Dooley
2023-05-08 16:09     ` Jisheng Zhang
2023-05-08  9:17   ` Krzysztof Kozlowski
2023-05-07 18:23 ` [PATCH 2/5] riscv: Add the T-HEAD SoC family Kconfig option Jisheng Zhang
2023-05-07 21:22   ` Conor Dooley
2023-05-08  6:42     ` Guo Ren
2023-05-08  6:52       ` Conor Dooley
2023-05-08  6:58         ` Guo Ren
2023-05-08  7:04           ` Conor Dooley
2023-05-07 18:23 ` [PATCH 3/5] riscv: dts: add initial T-HEAD light SoC device tree Jisheng Zhang
2023-05-07 21:35   ` Conor Dooley
2023-05-08  3:32     ` Icenowy Zheng
2023-05-08  7:01       ` Conor Dooley
2023-05-08  8:23       ` Heiko Stübner
2023-05-08  8:35         ` Conor Dooley
2023-05-08 15:56           ` Heiko Stübner
2023-05-08 16:26     ` Jisheng Zhang
2023-05-08 16:44       ` Conor Dooley
2023-05-08 17:09         ` Heiko Stübner
2023-05-21 15:37         ` Guo Ren
2023-05-21 17:08           ` Conor Dooley
2023-05-22  1:36             ` Guo Ren
2023-05-08  9:20   ` Krzysztof Kozlowski
2023-05-07 18:23 ` Jisheng Zhang [this message]
2023-05-07 21:27   ` [PATCH 4/5] riscv: dts: thead: add sipeed Lichee Pi 4A board " Conor Dooley
2023-05-08  6:44   ` Guo Ren
2023-05-07 18:23 ` [PATCH 5/5] MAINTAINERS: add entry for T-HEAD RISC-V SoC Jisheng Zhang
2023-05-07 21:21   ` Conor Dooley
2023-05-08 16:17     ` Jisheng Zhang
2023-05-08 17:23       ` Conor Dooley
2023-05-08  6:22   ` Guo Ren
2023-05-08  6:16 ` [PATCH 0/5] Add Sipeed Lichee Pi 4A RISC-V board support Guo Ren

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