From: Conor Dooley <conor@kernel.org>
To: linux-riscv@lists.infradead.org
Cc: conor@kernel.org, Conor Dooley <conor.dooley@microchip.com>,
Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Conor Dooley <conor+dt@kernel.org>,
Palmer Dabbelt <palmer@dabbelt.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
Heiko Stuebner <heiko@sntech.de>,
Andrew Jones <ajones@ventanamicro.com>,
Sunil V L <sunilvl@ventanamicro.com>,
Yangyu Chen <cyy@cyyself.name>,
devicetree@vger.kernel.org
Subject: [RFC 6/6] riscv: dts: microchip: use new riscv,isa-extension-* properties for mpfs
Date: Mon, 8 May 2023 19:16:26 +0100 [thread overview]
Message-ID: <20230508-elf-dismay-799bb48a635e@spud> (raw)
In-Reply-To: <20230508-hypnotic-phobia-99598439d828@spud>
From: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
arch/riscv/boot/dts/microchip/mpfs.dtsi | 42 ++++++++++++++++++++++---
1 file changed, 37 insertions(+), 5 deletions(-)
diff --git a/arch/riscv/boot/dts/microchip/mpfs.dtsi b/arch/riscv/boot/dts/microchip/mpfs.dtsi
index 104504352e99..53efb5e03c64 100644
--- a/arch/riscv/boot/dts/microchip/mpfs.dtsi
+++ b/arch/riscv/boot/dts/microchip/mpfs.dtsi
@@ -21,7 +21,11 @@ cpu0: cpu@0 {
i-cache-sets = <128>;
i-cache-size = <16384>;
reg = <0>;
- riscv,isa = "rv64imac";
+ riscv,isa-base = "rv64i";
+ riscv,isa-extension-i = "v1.0.0";
+ riscv,isa-extension-m = "v1.0.0";
+ riscv,isa-extension-a = "v1.0.0";
+ riscv,isa-extension-c = "v1.0.0";
clocks = <&clkcfg CLK_CPU>;
status = "disabled";
@@ -47,7 +51,14 @@ cpu1: cpu@1 {
i-tlb-size = <32>;
mmu-type = "riscv,sv39";
reg = <1>;
- riscv,isa = "rv64imafdc";
+ riscv,isa-base = "rv64i";
+ riscv,isa-extension-i = "v1.0.0";
+ riscv,isa-extension-m = "v1.0.0";
+ riscv,isa-extension-a = "v1.0.0";
+ riscv,isa-extension-f = "v1.0.0";
+ riscv,isa-extension-d = "v1.0.0";
+ riscv,isa-extension-c = "v1.0.0";
+ riscv,isa-extension-zicsr = "v1.0.0";
clocks = <&clkcfg CLK_CPU>;
tlb-split;
next-level-cache = <&cctrllr>;
@@ -75,7 +86,14 @@ cpu2: cpu@2 {
i-tlb-size = <32>;
mmu-type = "riscv,sv39";
reg = <2>;
- riscv,isa = "rv64imafdc";
+ riscv,isa-base = "rv64i";
+ riscv,isa-extension-i = "v1.0.0";
+ riscv,isa-extension-m = "v1.0.0";
+ riscv,isa-extension-a = "v1.0.0";
+ riscv,isa-extension-f = "v1.0.0";
+ riscv,isa-extension-d = "v1.0.0";
+ riscv,isa-extension-c = "v1.0.0";
+ riscv,isa-extension-zicsr = "v1.0.0";
clocks = <&clkcfg CLK_CPU>;
tlb-split;
next-level-cache = <&cctrllr>;
@@ -103,7 +121,14 @@ cpu3: cpu@3 {
i-tlb-size = <32>;
mmu-type = "riscv,sv39";
reg = <3>;
- riscv,isa = "rv64imafdc";
+ riscv,isa-base = "rv64i";
+ riscv,isa-extension-i = "v1.0.0";
+ riscv,isa-extension-m = "v1.0.0";
+ riscv,isa-extension-a = "v1.0.0";
+ riscv,isa-extension-f = "v1.0.0";
+ riscv,isa-extension-d = "v1.0.0";
+ riscv,isa-extension-c = "v1.0.0";
+ riscv,isa-extension-zicsr = "v1.0.0";
clocks = <&clkcfg CLK_CPU>;
tlb-split;
next-level-cache = <&cctrllr>;
@@ -131,7 +156,14 @@ cpu4: cpu@4 {
i-tlb-size = <32>;
mmu-type = "riscv,sv39";
reg = <4>;
- riscv,isa = "rv64imafdc";
+ riscv,isa-base = "rv64i";
+ riscv,isa-extension-i = "v1.0.0";
+ riscv,isa-extension-m = "v1.0.0";
+ riscv,isa-extension-a = "v1.0.0";
+ riscv,isa-extension-f = "v1.0.0";
+ riscv,isa-extension-d = "v1.0.0";
+ riscv,isa-extension-c = "v1.0.0";
+ riscv,isa-extension-zicsr = "v1.0.0";
clocks = <&clkcfg CLK_CPU>;
tlb-split;
next-level-cache = <&cctrllr>;
--
2.39.2
next prev parent reply other threads:[~2023-05-08 18:17 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-05-08 18:16 [RFC 0/6] Deprecate riscv,isa DT property? Conor Dooley
2023-05-08 18:16 ` [RFC 1/6] dt-bindings: riscv: clarify what an unversioned extension means Conor Dooley
2023-05-13 17:46 ` Krzysztof Kozlowski
2023-05-08 18:16 ` [RFC 2/6] dt-bindings: riscv: add riscv,isa-extension-* property and incompatible example Conor Dooley
2023-05-13 17:50 ` Krzysztof Kozlowski
2023-05-13 18:00 ` Conor Dooley
2023-05-08 18:16 ` [RFC 3/6] RISC-V: deprecate riscv,isa & replace it with per-extension properties Conor Dooley
2023-05-08 18:16 ` [RFC 4/6] RISC-V: add support for riscv,isa-base property Conor Dooley
2023-05-08 18:16 ` [RFC 5/6] RISC-V: drop a needless check in print_isa_ext() Conor Dooley
2023-05-08 18:16 ` Conor Dooley [this message]
2023-05-11 21:27 ` [RFC 0/6] Deprecate riscv,isa DT property? Atish Patra
2023-05-11 21:47 ` Conor Dooley
2023-05-11 22:34 ` Atish Patra
2023-05-11 22:38 ` Conor Dooley
2023-05-12 18:01 ` Palmer Dabbelt
2023-05-12 19:40 ` Conor Dooley
2023-05-12 22:05 ` Conor Dooley
2023-05-12 23:20 ` Atish Patra
2023-05-12 23:52 ` Conor Dooley
2023-05-12 23:55 ` Palmer Dabbelt
2023-05-13 0:09 ` Conor Dooley
2023-05-13 0:38 ` Palmer Dabbelt
2023-05-13 7:47 ` Anup Patel
2023-05-13 21:34 ` Jessica Clarke
2023-05-13 21:54 ` Conor Dooley
2023-05-15 4:38 ` Sunil V L
2023-05-15 7:52 ` Conor Dooley
2023-05-12 18:08 ` Palmer Dabbelt
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