From: dinh.nguyen@linux.intel.com
To: linux-hwmon@vger.kernel.org
Cc: dinguyen@kernel.org, devicetree@vger.kernel.org,
robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org,
linux-kernel@vger.kernel.org, jdelvare@suse.com,
linux@roeck-us.net, Dinh Nguyen <dinh.nguyen@linux.intel.com>
Subject: [PATCHv2 6/6] arm64: dts: socfpga: add hwmon properties
Date: Mon, 8 May 2023 16:28:52 -0500 [thread overview]
Message-ID: <20230508212852.8413-6-dinh.nguyen@linux.intel.com> (raw)
In-Reply-To: <20230508212852.8413-1-dinh.nguyen@linux.intel.com>
From: Dinh Nguyen <dinh.nguyen@linux.intel.com>
Add the hardware monitoring properties for Stratix10 and Agilex.
Signed-off-by: Dinh Nguyen <dinh.nguyen@linux.intel.com>
---
v2: add platform specific platforms to DTS files
---
.../boot/dts/altera/socfpga_stratix10.dtsi | 4 ++
.../dts/altera/socfpga_stratix10_socdk.dts | 31 +++++++++
arch/arm64/boot/dts/intel/socfpga_agilex.dtsi | 4 ++
.../boot/dts/intel/socfpga_agilex_n6000.dts | 66 +++++++++++++++++++
.../boot/dts/intel/socfpga_agilex_socdk.dts | 66 +++++++++++++++++++
.../dts/intel/socfpga_agilex_socdk_nand.dts | 66 +++++++++++++++++++
.../boot/dts/intel/socfpga_n5x_socdk.dts | 47 +++++++++++++
7 files changed, 284 insertions(+)
diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
index 41c9eb51d0ee..2526afa687d6 100644
--- a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
+++ b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
@@ -633,6 +633,10 @@ svc {
fpga_mgr: fpga-mgr {
compatible = "intel,stratix10-soc-fpga-mgr";
};
+
+ hwmon: temp-volt {
+ compatible = "intel,socfpga-stratix10-hwmon", "intel,socfpga-hwmon";
+ };
};
};
};
diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts b/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts
index 38ae674f2f02..d506dcf8dc7c 100644
--- a/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts
+++ b/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts
@@ -212,3 +212,34 @@ qspi_rootfs: partition@3FE0000 {
};
};
};
+
+&hwmon {
+ voltage {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ input@2 {
+ label = "0.8V VCC";
+ reg = <2>;
+ };
+
+ input@3 {
+ label = "1.0V VCCIO";
+ reg = <3>;
+ };
+
+ input@6 {
+ label = "0.9V VCCERAM";
+ reg = <6>;
+ };
+ };
+
+ temperature {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ input@0 {
+ label = "Main Die SDM";
+ reg = <0x0>;
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi
index f9674cc46764..552f9a05d039 100644
--- a/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi
+++ b/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi
@@ -666,6 +666,10 @@ svc {
fpga_mgr: fpga-mgr {
compatible = "intel,agilex-soc-fpga-mgr";
};
+
+ hwmon: temp-volt {
+ compatible = "intel,socfpga-agilex-hwmon", "intel,socfpga-hwmon";
+ };
};
};
};
diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex_n6000.dts b/arch/arm64/boot/dts/intel/socfpga_agilex_n6000.dts
index 6231a69204b1..c0642353b506 100644
--- a/arch/arm64/boot/dts/intel/socfpga_agilex_n6000.dts
+++ b/arch/arm64/boot/dts/intel/socfpga_agilex_n6000.dts
@@ -64,3 +64,69 @@ &watchdog0 {
&fpga_mgr {
status = "disabled";
};
+
+&hwmon {
+ voltage {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ input@2 {
+ label = "0.8V VCC";
+ reg = <2>;
+ };
+
+ input@3 {
+ label = "1.8V VCCIO_SDM";
+ reg = <3>;
+ };
+
+ input@4 {
+ label = "1.8V VCCPT";
+ reg = <4>;
+ };
+
+ input@5 {
+ label = "1.2V VCCCRCORE";
+ reg = <5>;
+ };
+
+ input@6 {
+ label = "0.9V VCCH";
+ reg = <6>;
+ };
+
+ input@7 {
+ label = "0.8V VCCL";
+ reg = <7>;
+ };
+ };
+
+ temperature {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ input@0 {
+ label = "Main Die SDM";
+ reg = <0x0>;
+ };
+
+ input@10000 {
+ label = "Main Die corner bottom left max";
+ reg = <0x10000>;
+ };
+
+ input@20000 {
+ label = "Main Die corner top left max";
+ reg = <0x20000>;
+ };
+
+ input@30000 {
+ label = "Main Die corner bottom right max";
+ reg = <0x30000>;
+ };
+
+ input@40000 {
+ label = "Main Die corner top right max";
+ reg = <0x40000>;
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts b/arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts
index 07c3f8876613..4bd8cdd8a7ca 100644
--- a/arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts
+++ b/arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts
@@ -138,3 +138,69 @@ qspi_rootfs: partition@3FE0000 {
};
};
};
+
+&hwmon {
+ voltage {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ input@2 {
+ label = "0.8V VCC";
+ reg = <2>;
+ };
+
+ input@3 {
+ label = "1.8V VCCIO_SDM";
+ reg = <3>;
+ };
+
+ input@4 {
+ label = "1.8V VCCPT";
+ reg = <4>;
+ };
+
+ input@5 {
+ label = "1.2V VCCCRCORE";
+ reg = <5>;
+ };
+
+ input@6 {
+ label = "0.9V VCCH";
+ reg = <6>;
+ };
+
+ input@7 {
+ label = "0.8V VCCL";
+ reg = <7>;
+ };
+ };
+
+ temperature {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ input@0 {
+ label = "Main Die SDM";
+ reg = <0x0>;
+ };
+
+ input@10000 {
+ label = "Main Die corner bottom left max";
+ reg = <0x10000>;
+ };
+
+ input@20000 {
+ label = "Main Die corner top left max";
+ reg = <0x20000>;
+ };
+
+ input@30000 {
+ label = "Main Die corner bottom right max";
+ reg = <0x30000>;
+ };
+
+ input@40000 {
+ label = "Main Die corner top right max";
+ reg = <0x40000>;
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex_socdk_nand.dts b/arch/arm64/boot/dts/intel/socfpga_agilex_socdk_nand.dts
index 51f83f96ec65..bfee1ca0bd6e 100644
--- a/arch/arm64/boot/dts/intel/socfpga_agilex_socdk_nand.dts
+++ b/arch/arm64/boot/dts/intel/socfpga_agilex_socdk_nand.dts
@@ -114,3 +114,69 @@ &usb0 {
&watchdog0 {
status = "okay";
};
+
+&hwmon {
+ voltage {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ input@2 {
+ label = "0.8V VCC";
+ reg = <2>;
+ };
+
+ input@3 {
+ label = "1.8V VCCIO_SDM";
+ reg = <3>;
+ };
+
+ input@4 {
+ label = "1.8V VCCPT";
+ reg = <4>;
+ };
+
+ input@5 {
+ label = "1.2V VCCCRCORE";
+ reg = <5>;
+ };
+
+ input@6 {
+ label = "0.9V VCCH";
+ reg = <6>;
+ };
+
+ input@7 {
+ label = "0.8V VCCL";
+ reg = <7>;
+ };
+ };
+
+ temperature {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ input@0 {
+ label = "Main Die SDM";
+ reg = <0x0>;
+ };
+
+ input@10000 {
+ label = "Main Die corner bottom left max";
+ reg = <0x10000>;
+ };
+
+ input@20000 {
+ label = "Main Die corner top left max";
+ reg = <0x20000>;
+ };
+
+ input@30000 {
+ label = "Main Die corner bottom right max";
+ reg = <0x30000>;
+ };
+
+ input@40000 {
+ label = "Main Die corner top right max";
+ reg = <0x40000>;
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/intel/socfpga_n5x_socdk.dts b/arch/arm64/boot/dts/intel/socfpga_n5x_socdk.dts
index 08c088571270..090b0382db98 100644
--- a/arch/arm64/boot/dts/intel/socfpga_n5x_socdk.dts
+++ b/arch/arm64/boot/dts/intel/socfpga_n5x_socdk.dts
@@ -129,3 +129,50 @@ &usb0 {
&watchdog0 {
status = "okay";
};
+
+&hwmon {
+ compatible = "intel,socfpga-n5x-hwmon", "intel,socfpga-hwmon";
+ voltage {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ input@2 {
+ label = "0.8V VDD";
+ reg = <2>;
+ };
+
+ input@3 {
+ label = "0.8V VDD_SDM";
+ reg = <3>;
+ };
+
+ input@4 {
+ label = "1.8V VCCADC";
+ reg = <4>;
+ };
+
+ input@5 {
+ label = "1.8V VCCPD";
+ reg = <5>;
+ };
+
+ input@6 {
+ label = "1.8V VCCIO_SDM";
+ reg = <6>;
+ };
+
+ input@7 {
+ label = "0.8V VDD_HPS";
+ reg = <7>;
+ };
+ };
+
+ temperature {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ input@0 {
+ label = "Main Die SDM";
+ reg = <0x0>;
+ };
+ };
+};
--
2.40.0
next prev parent reply other threads:[~2023-05-08 21:41 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-05-08 21:28 [PATCHv2 1/6] units: add a macro for MILLIVOLT_PER_VOLT dinh.nguyen
2023-05-08 21:28 ` [PATCHv2 2/6] firmware: stratix10-svc: add method for reading voltage and temperature dinh.nguyen
2023-05-08 21:28 ` [PATCHv2 3/6] hwmon: (socfpga) Add hardware monitoring support on SoCFPGA platforms dinh.nguyen
2023-05-09 0:57 ` Armin Wolf
2023-05-25 20:47 ` Dinh Nguyen
2023-05-09 6:57 ` Krzysztof Kozlowski
2023-05-12 11:11 ` Andy Shevchenko
2023-05-25 21:20 ` Dinh Nguyen
2023-05-27 8:28 ` Andy Shevchenko
2023-05-08 21:28 ` [PATCHv2 4/6] MAINTAINERS: add Dinh Nguyen for socfpga-hwmon driver dinh.nguyen
2023-05-08 21:28 ` [PATCHv2 5/6] dt-bindings: hwmon: intel: add hardware monitor bindings for SoCFPGA dinh.nguyen
2023-05-09 7:01 ` Krzysztof Kozlowski
2023-05-08 21:28 ` dinh.nguyen [this message]
2023-05-09 7:04 ` [PATCHv2 6/6] arm64: dts: socfpga: add hwmon properties Krzysztof Kozlowski
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20230508212852.8413-6-dinh.nguyen@linux.intel.com \
--to=dinh.nguyen@linux.intel.com \
--cc=devicetree@vger.kernel.org \
--cc=dinguyen@kernel.org \
--cc=jdelvare@suse.com \
--cc=krzysztof.kozlowski+dt@linaro.org \
--cc=linux-hwmon@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux@roeck-us.net \
--cc=robh+dt@kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).