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Fri, 12 May 2023 02:35:27 -0700 Date: Fri, 12 May 2023 10:35:07 +0100 From: Conor Dooley To: Xingyu Wu CC: , , Michael Turquette , Stephen Boyd , Krzysztof Kozlowski , Philipp Zabel , Conor Dooley , Emil Renner Berthing , Rob Herring , Paul Walmsley , Palmer Dabbelt , Albert Ou , Hal Feng , William Qiu , , Subject: Re: [PATCH v4 3/7] dt-bindings: clock: jh7110-syscrg: Add PLL clock inputs Message-ID: <20230512-backlit-radiated-ded0b38b4a94@wendy> References: <20230512022036.97987-1-xingyu.wu@starfivetech.com> <20230512022036.97987-4-xingyu.wu@starfivetech.com> <20230512-uproar-external-49a9e793fbc4@wendy> <91e4fd3c-20cb-724b-c9a8-e038600aabb7@starfivetech.com> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="QcQ3Y5HHQp1oxn9V" Content-Disposition: inline In-Reply-To: <91e4fd3c-20cb-724b-c9a8-e038600aabb7@starfivetech.com> Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org --QcQ3Y5HHQp1oxn9V Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Fri, May 12, 2023 at 04:07:47PM +0800, Xingyu Wu wrote: > On 2023/5/12 14:47, Conor Dooley wrote: > > On Fri, May 12, 2023 at 10:20:32AM +0800, Xingyu Wu wrote: > >> Add PLL clock inputs from PLL clock generator. > >>=20 > >> Acked-by: Krzysztof Kozlowski > >> Signed-off-by: Xingyu Wu > >> --- > >> .../clock/starfive,jh7110-syscrg.yaml | 20 +++++++++++++++++-- > >> 1 file changed, 18 insertions(+), 2 deletions(-) > >=20 > > /tmp/tmp.KDlzwQM5ma/arch/riscv/boot/dts/starfive/jh7110-starfive-vision= five-2-v1.3b.dtb: clock-controller@13020000: clocks: 'oneOf' conditional fa= iled, one must be fixed: > > [[19], [20], [21], [22], [23], [24], [25], [26], [27]] is too short > > From schema: /Documentation/devicetree/bindings/clock/starfive,jh7110-= syscrg.yaml > > /tmp/tmp.KDlzwQM5ma/arch/riscv/boot/dts/starfive/jh7110-starfive-vision= five-2-v1.3b.dtb: clock-controller@13020000: clock-names: 'oneOf' condition= al failed, one must be fixed: > > ['osc', 'gmac1_rmii_refin', 'gmac1_rgmii_rxin', 'i2stx_bclk_ext', 'i2s= tx_lrck_ext', 'i2srx_bclk_ext', 'i2srx_lrck_ext', 'tdm_ext', 'mclk_ext'] is= too short > > 'i2stx_bclk_ext' was expected > > 'i2stx_lrck_ext' was expected > > 'i2srx_bclk_ext' was expected > > 'i2srx_lrck_ext' was expected > > 'tdm_ext' was expected > > 'mclk_ext' was expected > > 'pll0_out' was expected > > From schema: /Documentation/devicetree/bindings/clock/starfive,jh7110-= syscrg.yaml > > /tmp/tmp.KDlzwQM5ma/arch/riscv/boot/dts/starfive/jh7110-starfive-vision= five-2-v1.2a.dtb: clock-controller@13020000: clocks: 'oneOf' conditional fa= iled, one must be fixed: > > [[19], [20], [21], [22], [23], [24], [25], [26], [27]] is too short > > From schema: Documentation/devicetree/bindings/clock/starfive,jh7110-s= yscrg.yaml > > /tmp/tmp.KDlzwQM5ma/arch/riscv/boot/dts/starfive/jh7110-starfive-vision= five-2-v1.2a.dtb: clock-controller@13020000: clock-names: 'oneOf' condition= al failed, one must be fixed: > > ['osc', 'gmac1_rmii_refin', 'gmac1_rgmii_rxin', 'i2stx_bclk_ext', 'i2s= tx_lrck_ext', 'i2srx_bclk_ext', 'i2srx_lrck_ext', 'tdm_ext', 'mclk_ext'] is= too short > > 'i2stx_bclk_ext' was expected > > 'i2stx_lrck_ext' was expected > > 'i2srx_bclk_ext' was expected > > 'i2srx_lrck_ext' was expected > > 'tdm_ext' was expected > > 'mclk_ext' was expected > > 'pll0_out' was expected > > Documentation/devicetree/bindings/clock/starfive,jh7110-syscrg.yaml > >=20 > > This binding change is incompatible with the existing devicetrees for > > the visionfive 2. >=20 > This looks like less clocks about PLL in SYSCRG node. And I add this in p= atch 7. The existing devicetree is a valid, albeit limited, description of the hardware. After your changes to the clock driver in this series, but *without* the changes to the devicetrees, does the system still function? =46rom a quick check of 4/7, it looks like it will not? --QcQ3Y5HHQp1oxn9V Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iHUEABYIAB0WIQRh246EGq/8RLhDjO14tDGHoIJi0gUCZF4ISwAKCRB4tDGHoIJi 0iZ9AP4u9KYEMY6ijX89u7Z+3hMOXU9bpxiDpvO0ou//U3u5/QEA/iV3wF+GGG2p Xe3b7nBI0NXFjIeBsr4Ow5b4xMFfZQc= =4554 -----END PGP SIGNATURE----- --QcQ3Y5HHQp1oxn9V--