From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 259D0C77B7D for ; Mon, 15 May 2023 04:26:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229590AbjEOE0E (ORCPT ); Mon, 15 May 2023 00:26:04 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33066 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229539AbjEOE0C (ORCPT ); Mon, 15 May 2023 00:26:02 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [139.178.84.217]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 25C3310D9; Sun, 14 May 2023 21:26:01 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id BF1FF60FC4; Mon, 15 May 2023 04:26:00 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 78C2DC433EF; Mon, 15 May 2023 04:25:55 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1684124760; bh=+Bww6kGRqCRZ3zp1IyWYbqBA69VGGPKf4nQa2AuyNfg=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=t0NrA/MDKouAujbuQ2um+9+EdT2rme/1+tUbqwaIqLZO+QAhBs8W4sBEKjOPUf8bF JzlPt0werBVtCEAT8o21eojkI1REj6TxMEh0la5pYutBMYQZV/WFIE6OvkbBDGwLCm 9Ehtf7HraKPcYnRwZLgLgYNgR2UmAKkwIe93QTCFKajVBtOA91wtw71vqCURwCa7dn nbzj/CLR7NmM8yUxXfK99vSRaIFMmr2E1b3hOi6Wc1J+kH4U1S9rfJj286ZHfKB2T0 IWv6GPgQN4JjG4jFnOekDAk0TinLkNCoxrA6L/HphXwG5gCMmEzkHo760h66bZH34h XRdtZYV7aPvtg== Date: Mon, 15 May 2023 09:55:51 +0530 From: Manivannan Sadhasivam To: Bartosz Golaszewski Cc: Andy Gross , Bjorn Andersson , Konrad Dybcio , Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Manivannan Sadhasivam , Alim Akhtar , Avri Altman , Bart Van Assche , linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-scsi@vger.kernel.org, Bartosz Golaszewski Subject: Re: [PATCH v3 4/5] arm64: dts: qcom: sa8775p: add UFS nodes Message-ID: <20230515042551.GC5143@thinkpad> References: <20230411130446.401440-1-brgl@bgdev.pl> <20230411130446.401440-5-brgl@bgdev.pl> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20230411130446.401440-5-brgl@bgdev.pl> Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On Tue, Apr 11, 2023 at 03:04:45PM +0200, Bartosz Golaszewski wrote: > From: Bartosz Golaszewski > > Add nodes for the UFS and its PHY on sa8775p platforms. > > Signed-off-by: Bartosz Golaszewski > Reviewed-by: Konrad Dybcio > --- > arch/arm64/boot/dts/qcom/sa8775p.dtsi | 58 +++++++++++++++++++++++++++ > 1 file changed, 58 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi > index 2343df7e0ea4..5de0fbbe9752 100644 > --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi > +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi > @@ -585,6 +585,64 @@ &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, > }; > }; > > + ufs_mem_hc: ufs@1d84000 { > + compatible = "qcom,sa8775p-ufshc", "qcom,ufshc", "jedec,ufs-2.0"; > + reg = <0x0 0x01d84000 0x0 0x3000>; > + interrupts = ; > + phys = <&ufs_mem_phy>; > + phy-names = "ufsphy"; > + lanes-per-direction = <2>; > + #reset-cells = <1>; > + resets = <&gcc GCC_UFS_PHY_BCR>; > + reset-names = "rst"; > + power-domains = <&gcc UFS_PHY_GDSC>; > + required-opps = <&rpmhpd_opp_nom>; > + iommus = <&apps_smmu 0x100 0x0>; > + clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, > + <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, > + <&gcc GCC_UFS_PHY_AHB_CLK>, > + <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, > + <&rpmhcc RPMH_CXO_CLK>, > + <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, > + <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, > + <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; > + clock-names = "core_clk", > + "bus_aggr_clk", > + "iface_clk", > + "core_clk_unipro", > + "ref_clk", > + "tx_lane0_sync_clk", > + "rx_lane0_sync_clk", > + "rx_lane1_sync_clk"; > + freq-table-hz = <75000000 300000000>, > + <0 0>, > + <0 0>, > + <75000000 300000000>, > + <0 0>, > + <0 0>, > + <0 0>, > + <0 0>; > + status = "disabled"; I'm pretty sure that the UFS controllers found in latest SoCs are cache coherent. So you'd need "dma-coherent" property here. - Mani > + }; > + > + ufs_mem_phy: phy@1d87000 { > + compatible = "qcom,sa8775p-qmp-ufs-phy"; > + reg = <0x0 0x01d87000 0x0 0xe10>; > + /* > + * Yes, GCC_EDP_REF_CLKREF_EN is correct in qref. It > + * enables the CXO clock to eDP *and* UFS PHY. > + */ > + clocks = <&rpmhcc RPMH_CXO_CLK>, > + <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, > + <&gcc GCC_EDP_REF_CLKREF_EN>; > + clock-names = "ref", "ref_aux", "qref"; > + power-domains = <&gcc UFS_PHY_GDSC>; > + resets = <&ufs_mem_hc 0>; > + reset-names = "ufsphy"; > + #phy-cells = <0>; > + status = "disabled"; > + }; > + > tcsr_mutex: hwlock@1f40000 { > compatible = "qcom,tcsr-mutex"; > reg = <0x0 0x01f40000 0x0 0x20000>; > -- > 2.37.2 > -- மணிவண்ணன் சதாசிவம்