Re: [PATCH 2/2] arm64: dts: qcom: sm8550: Use the correct LLCC register scheme

[Manivannan Sadhasivam <mani@kernel.org>]

On Wed, May 17, 2023 at 04:18:50AM +0200, Konrad Dybcio wrote:
> During the ABI-breaking (for good reasons) conversion of the LLCC
> register description, SM8550 was not taken into account, resulting
> in LLCC being broken on any kernel containing the patch referenced
> in the fixes tag.
> 
> Fix it by describing the regions properly.
> 
> Fixes: ee13b5008707 ("qcom: llcc/edac: Fix the base address used for accessing LLCC banks")

Same comment about the Fixes tag.

> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>

I do not have access to the SM8550 documentation to confirm the base address but
I hope that it has been taken care of.

Acked-by: Manivannan Sadhasivam <mani@kernel.org>

- Mani

> ---
>  arch/arm64/boot/dts/qcom/sm8550.dtsi | 11 +++++++++--
>  1 file changed, 9 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi
> index 6e9bad8f6f33..70ae7e2e900a 100644
> --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi
> @@ -3762,9 +3762,16 @@ gem_noc: interconnect@24100000 {
>  
>  		system-cache-controller@25000000 {
>  			compatible = "qcom,sm8550-llcc";
> -			reg = <0 0x25000000 0 0x800000>,
> +			reg = <0 0x25000000 0 0x200000>,
> +			      <0 0x25200000 0 0x200000>,
> +			      <0 0x25400000 0 0x200000>,
> +			      <0 0x25600000 0 0x200000>,
>  			      <0 0x25800000 0 0x200000>;
> -			reg-names = "llcc_base", "llcc_broadcast_base";
> +			reg-names = "llcc0_base",
> +				    "llcc1_base",
> +				    "llcc2_base",
> +				    "llcc3_base",
> +				    "llcc_broadcast_base";
>  			interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
>  		};
>  
> 
> -- 
> 2.40.1
> 

-- 
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