From: Conor Dooley <conor@kernel.org>
To: palmer@dabbelt.com
Cc: conor@kernel.org, Conor Dooley <conor.dooley@microchip.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
Andrew Jones <ajones@ventanamicro.com>,
Sunil V L <sunilvl@ventanamicro.com>,
Yangyu Chen <cyy@cyyself.name>, Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
devicetree@vger.kernel.org, linux-riscv@lists.infradead.org
Subject: [PATCH v2 6/8] RISC-V: remove decrement/increment dance in ISA string parser
Date: Thu, 18 May 2023 23:39:07 +0100 [thread overview]
Message-ID: <20230518-growl-nickname-f219c1cd04fa@spud> (raw)
In-Reply-To: <20230518-moneybags-rebalance-1484db493d6a@spud>
From: Conor Dooley <conor.dooley@microchip.com>
While expanding on the comments in the ISA string parsing code, I
noticed that the conditional decrement of `isa` at the end of the loop
was a bit odd.
The parsing code expects that at the start of the for loop, `isa` will
point to the first character of the next unparsed extension.
However, depending on what the next extension is, this may not be true.
Unless the next extension is a multi-letter extension preceded by an
underscore, `isa` will either point to the string's null-terminator or
to the first character of the next extension, once the switch statement
has been evaluated.
Obviously incrementing `isa` at the end of the loop could cause it to
increment past the null terminator or miss a single letter extension, so
`isa` is conditionally decremented, just so that the loop can increment
it again.
It's easier to understand the code if, instead of this decrement +
increment dance, we instead use a while loop & rely on the handling of
individual extension types to leave `isa` pointing to the first
character of the next extension.
As already mentioned, this won't be the case where the following
extension is multi-letter & preceded by an underscore. To handle that,
invert the check and increment rather than decrement.
Hopefully this eliminates a "huh?!?" moment the next time somebody tries
to understand this code.
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
arch/riscv/kernel/cpufeature.c | 14 ++++++--------
1 file changed, 6 insertions(+), 8 deletions(-)
diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
index cc5189c7c64e..bbf3cd203fad 100644
--- a/arch/riscv/kernel/cpufeature.c
+++ b/arch/riscv/kernel/cpufeature.c
@@ -139,7 +139,7 @@ void __init riscv_fill_hwcap(void)
isa += 4;
bitmap_zero(this_isa, RISCV_ISA_EXT_MAX);
- for (; *isa; ++isa) {
+ while (*isa) {
const char *ext = isa++;
const char *ext_end = isa;
bool ext_long = false, ext_err = false;
@@ -252,14 +252,12 @@ void __init riscv_fill_hwcap(void)
/*
* The parser expects that at the start of an iteration isa points to the
- * character before the start of the next extension. This will not be the
- * case if we have just parsed a single-letter extension and the next
- * extension is not a multi-letter extension prefixed with an "_". It is
- * also not the case at the end of the string, where it will point to the
- * terminating null character.
+ * first character of the next extension. As we stop parsing an extension
+ * on meeting a non-alphanumeric character, an extra increment is needed
+ * where the succeeding extension is a multi-letter prefixed with an "_".
*/
- if (*isa != '_')
- --isa;
+ if (*isa == '_')
+ ++isa;
#define SET_ISA_EXT_MAP(name, bit) \
do { \
--
2.39.2
next prev parent reply other threads:[~2023-05-18 22:40 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-05-18 22:39 [PATCH v2 0/8] ISA string parser cleanups++ Conor Dooley
2023-05-18 22:39 ` [PATCH v2 1/8] RISC-V: simplify register width check in ISA string parsing Conor Dooley
2023-05-18 22:39 ` [PATCH v2 2/8] RISC-V: only iterate over possible CPUs in ISA string parser Conor Dooley
2023-05-18 22:39 ` [PATCH v2 3/8] RISC-V: split early & late of_node to hartid mapping Conor Dooley
2023-05-18 22:39 ` [PATCH v2 4/8] RISC-V: validate riscv,isa at boot, not during ISA string parsing Conor Dooley
2023-05-18 22:39 ` [PATCH v2 5/8] RISC-V: rework comments in ISA string parser Conor Dooley
2023-05-18 22:39 ` Conor Dooley [this message]
2023-05-18 22:39 ` [PATCH v2 7/8] dt-bindings: riscv: explicitly mention assumption of Zicntr & Zihpm support Conor Dooley
2023-05-18 22:39 ` [PATCH v2 8/8] RISC-V: always report presence of extenstions formerly part of the base ISA Conor Dooley
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