Re: [PATCH v15 5/6] dt-bindings: clock: meson: add A1 Peripherals clock controller bindings

[Dmitry Rokosov <ddrokosov@sberdevices.ru>]

Martin,

On Fri, May 19, 2023 at 11:09:29PM +0200, Martin Blumenstingl wrote:
> Hi Krzysztof and Dmitry,
> 
> On Wed, May 17, 2023 at 3:33 PM Dmitry Rokosov <ddrokosov@sberdevices.ru> wrote:
> [...]
> > +  clocks:
> > +    items:
> > +      - description: input fixed pll div2
> > +      - description: input fixed pll div3
> > +      - description: input fixed pll div5
> > +      - description: input fixed pll div7
> > +      - description: input hifi pll
> > +      - description: input oscillator (usually at 24MHz)
> > +
> > +  clock-names:
> > +    items:
> > +      - const: fclk_div2
> > +      - const: fclk_div3
> > +      - const: fclk_div5
> > +      - const: fclk_div7
> > +      - const: hifi_pll
> > +      - const: xtal
> This IP block has at least one additional input called "sys_pll_div16".
> My understanding is that the "sys_pll_div16" clock is generated by the
> CPU clock controller. Support for the CPU clock controller
> (dt-bindings and a driver) will be added at a later time by Dmitry.
> How can we manage incrementally implementing the clock controllers?
> From a hardware perspective the "sys_pll_div16" input is mandatory.
> How to manage this in the .dts patches then (for example: does this
> mean that Dmitry can only add the clock controller to the .dts when
> all clock controller bindings have been implemented - or is there
> another way)?

You're absolutely right: currently, not all inputs are supported because
the CPU clock controller isn't ready yet – I'm working on it at the
moment.

I understand your concerns about bindings and schema description, but
there is an issue to be considered. I'm developing the entire clock
controller A1 subsystem incrementally in three stages: peripherals and
PLL, CPU, and Audio. This is because the CPU can operate at a static
frequency and voltage, and the board boots normally without the CPU
clock controller, thermal sensor, and OPP table. Audio is also
important, but it's optional. On the other hand, without setting up the
peripherals and PLL controllers, the board won't function because
they're fundamental.

Right now, we're in the first stage of the plan. Unfortunately, I can't
disclose the exact names and number of clock bindings for the CPU and
Audio, as they're still in development and only exist in my head or
draft versions.

If possible, I'd prefer to provide the new bindings and connections once
all the appropriate drivers are finalized.

-- 
Thank you,
Dmitry