* [PATCH v6 1/5] dt-bindings: PCI: qcom: Add SDX65 SoC
2023-05-18 17:47 [PATCH v6 0/5] Add PCIe EP support for SDX65 Rohit Agarwal
@ 2023-05-18 17:47 ` Rohit Agarwal
2023-05-25 4:22 ` Bjorn Andersson
2023-05-18 17:47 ` [PATCH v6 2/5] ARM: dts: qcom: sdx65: Add support for PCIe PHY Rohit Agarwal
` (4 subsequent siblings)
5 siblings, 1 reply; 10+ messages in thread
From: Rohit Agarwal @ 2023-05-18 17:47 UTC (permalink / raw)
To: agross, andersson, konrad.dybcio, mani, bhelgaas, lpieralisi, kw,
robh, krzysztof.kozlowski+dt, conor+dt, manivannan.sadhasivam
Cc: linux-arm-msm, linux-pci, devicetree, linux-kernel, Rohit Agarwal
Add PCIe EP compatible string for SDX65 SoC.
Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
---
Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml
index b3c22eb..8111122 100644
--- a/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml
+++ b/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml
@@ -13,6 +13,7 @@ properties:
compatible:
enum:
- qcom,sdx55-pcie-ep
+ - qcom,sdx65-pcie-ep
- qcom,sm8450-pcie-ep
reg:
@@ -109,6 +110,7 @@ allOf:
contains:
enum:
- qcom,sdx55-pcie-ep
+ - qcom,sdx65-pcie-ep
then:
properties:
clocks:
--
2.7.4
^ permalink raw reply related [flat|nested] 10+ messages in thread* Re: [PATCH v6 1/5] dt-bindings: PCI: qcom: Add SDX65 SoC
2023-05-18 17:47 ` [PATCH v6 1/5] dt-bindings: PCI: qcom: Add SDX65 SoC Rohit Agarwal
@ 2023-05-25 4:22 ` Bjorn Andersson
0 siblings, 0 replies; 10+ messages in thread
From: Bjorn Andersson @ 2023-05-25 4:22 UTC (permalink / raw)
To: Rohit Agarwal, bhelgaas, lpieralisi
Cc: kw, agross, konrad.dybcio, mani, robh, krzysztof.kozlowski+dt,
conor+dt, manivannan.sadhasivam, linux-arm-msm, linux-pci,
devicetree, linux-kernel
On Thu, May 18, 2023 at 11:17:49PM +0530, Rohit Agarwal wrote:
> Add PCIe EP compatible string for SDX65 SoC.
>
> Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com>
> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Bjorn, Lorenzo, please pick this patch through the PCI tree (to avoid
any merge issues).
Thanks,
Bjorn
> ---
> Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml
> index b3c22eb..8111122 100644
> --- a/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml
> +++ b/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml
> @@ -13,6 +13,7 @@ properties:
> compatible:
> enum:
> - qcom,sdx55-pcie-ep
> + - qcom,sdx65-pcie-ep
> - qcom,sm8450-pcie-ep
>
> reg:
> @@ -109,6 +110,7 @@ allOf:
> contains:
> enum:
> - qcom,sdx55-pcie-ep
> + - qcom,sdx65-pcie-ep
> then:
> properties:
> clocks:
> --
> 2.7.4
>
^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH v6 2/5] ARM: dts: qcom: sdx65: Add support for PCIe PHY
2023-05-18 17:47 [PATCH v6 0/5] Add PCIe EP support for SDX65 Rohit Agarwal
2023-05-18 17:47 ` [PATCH v6 1/5] dt-bindings: PCI: qcom: Add SDX65 SoC Rohit Agarwal
@ 2023-05-18 17:47 ` Rohit Agarwal
2023-05-18 17:47 ` [PATCH v6 3/5] ARM: dts: qcom: sdx65: Add support for PCIe EP Rohit Agarwal
` (3 subsequent siblings)
5 siblings, 0 replies; 10+ messages in thread
From: Rohit Agarwal @ 2023-05-18 17:47 UTC (permalink / raw)
To: agross, andersson, konrad.dybcio, mani, bhelgaas, lpieralisi, kw,
robh, krzysztof.kozlowski+dt, conor+dt, manivannan.sadhasivam
Cc: linux-arm-msm, linux-pci, devicetree, linux-kernel, Rohit Agarwal
Add devicetree support for PCIe PHY used in SDX65 platform. This PHY is
used by the PCIe EP controller.
Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
---
arch/arm/boot/dts/qcom-sdx65.dtsi | 31 +++++++++++++++++++++++++++++++
1 file changed, 31 insertions(+)
diff --git a/arch/arm/boot/dts/qcom-sdx65.dtsi b/arch/arm/boot/dts/qcom-sdx65.dtsi
index 525dd8a1..2fe61c2 100644
--- a/arch/arm/boot/dts/qcom-sdx65.dtsi
+++ b/arch/arm/boot/dts/qcom-sdx65.dtsi
@@ -295,6 +295,37 @@
status = "disabled";
};
+ pcie_phy: phy@1c06000 {
+ compatible = "qcom,sdx65-qmp-gen4x2-pcie-phy";
+ reg = <0x01c06000 0x2000>;
+
+ clocks = <&gcc GCC_PCIE_AUX_PHY_CLK_SRC>,
+ <&gcc GCC_PCIE_CFG_AHB_CLK>,
+ <&gcc GCC_PCIE_0_CLKREF_EN>,
+ <&gcc GCC_PCIE_RCHNG_PHY_CLK>,
+ <&gcc GCC_PCIE_PIPE_CLK>;
+ clock-names = "aux",
+ "cfg_ahb",
+ "ref",
+ "rchng",
+ "pipe";
+
+ resets = <&gcc GCC_PCIE_PHY_BCR>;
+ reset-names = "phy";
+
+ assigned-clocks = <&gcc GCC_PCIE_RCHNG_PHY_CLK>;
+ assigned-clock-rates = <100000000>;
+
+ power-domains = <&gcc PCIE_GDSC>;
+
+ #clock-cells = <0>;
+ clock-output-names = "pcie_pipe_clk";
+
+ #phy-cells = <0>;
+
+ status = "disabled";
+ };
+
tcsr_mutex: hwlock@1f40000 {
compatible = "qcom,tcsr-mutex";
reg = <0x01f40000 0x40000>;
--
2.7.4
^ permalink raw reply related [flat|nested] 10+ messages in thread* [PATCH v6 3/5] ARM: dts: qcom: sdx65: Add support for PCIe EP
2023-05-18 17:47 [PATCH v6 0/5] Add PCIe EP support for SDX65 Rohit Agarwal
2023-05-18 17:47 ` [PATCH v6 1/5] dt-bindings: PCI: qcom: Add SDX65 SoC Rohit Agarwal
2023-05-18 17:47 ` [PATCH v6 2/5] ARM: dts: qcom: sdx65: Add support for PCIe PHY Rohit Agarwal
@ 2023-05-18 17:47 ` Rohit Agarwal
2023-05-18 17:47 ` [PATCH v6 4/5] ARM: dts: qcom: sdx65-mtp: Enable PCIe PHY Rohit Agarwal
` (2 subsequent siblings)
5 siblings, 0 replies; 10+ messages in thread
From: Rohit Agarwal @ 2023-05-18 17:47 UTC (permalink / raw)
To: agross, andersson, konrad.dybcio, mani, bhelgaas, lpieralisi, kw,
robh, krzysztof.kozlowski+dt, conor+dt, manivannan.sadhasivam
Cc: linux-arm-msm, linux-pci, devicetree, linux-kernel, Rohit Agarwal
Add support for PCIe Endpoint controller on the
Qualcomm SDX65 platform.
Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
---
arch/arm/boot/dts/qcom-sdx65.dtsi | 56 +++++++++++++++++++++++++++++++++++++++
1 file changed, 56 insertions(+)
diff --git a/arch/arm/boot/dts/qcom-sdx65.dtsi b/arch/arm/boot/dts/qcom-sdx65.dtsi
index 2fe61c2..1a35830 100644
--- a/arch/arm/boot/dts/qcom-sdx65.dtsi
+++ b/arch/arm/boot/dts/qcom-sdx65.dtsi
@@ -8,6 +8,7 @@
#include <dt-bindings/clock/qcom,gcc-sdx65.h>
#include <dt-bindings/clock/qcom,rpmh.h>
+#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/power/qcom-rpmpd.h>
#include <dt-bindings/soc/qcom,rpmh-rsc.h>
@@ -295,6 +296,56 @@
status = "disabled";
};
+ pcie_ep: pcie-ep@1c00000 {
+ compatible = "qcom,sdx65-pcie-ep", "qcom,sdx55-pcie-ep";
+ reg = <0x01c00000 0x3000>,
+ <0x40000000 0xf1d>,
+ <0x40000f20 0xa8>,
+ <0x40001000 0x1000>,
+ <0x40200000 0x100000>,
+ <0x01c03000 0x3000>;
+ reg-names = "parf",
+ "dbi",
+ "elbi",
+ "atu",
+ "addr_space",
+ "mmio";
+
+ qcom,perst-regs = <&tcsr 0xb258 0xb270>;
+
+ clocks = <&gcc GCC_PCIE_AUX_CLK>,
+ <&gcc GCC_PCIE_CFG_AHB_CLK>,
+ <&gcc GCC_PCIE_MSTR_AXI_CLK>,
+ <&gcc GCC_PCIE_SLV_AXI_CLK>,
+ <&gcc GCC_PCIE_SLV_Q2A_AXI_CLK>,
+ <&gcc GCC_PCIE_SLEEP_CLK>,
+ <&gcc GCC_PCIE_0_CLKREF_EN>;
+ clock-names = "aux",
+ "cfg",
+ "bus_master",
+ "bus_slave",
+ "slave_q2a",
+ "sleep",
+ "ref";
+
+ interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "global", "doorbell";
+
+ resets = <&gcc GCC_PCIE_BCR>;
+ reset-names = "core";
+
+ power-domains = <&gcc PCIE_GDSC>;
+
+ phys = <&pcie_phy>;
+ phy-names = "pcie-phy";
+
+ max-link-speed = <3>;
+ num-lanes = <2>;
+
+ status = "disabled";
+ };
+
pcie_phy: phy@1c06000 {
compatible = "qcom,sdx65-qmp-gen4x2-pcie-phy";
reg = <0x01c06000 0x2000>;
@@ -332,6 +383,11 @@
#hwlock-cells = <1>;
};
+ tcsr: syscon@1fcb000 {
+ compatible = "qcom,sdx65-tcsr", "syscon";
+ reg = <0x01fc0000 0x1000>;
+ };
+
ipa: ipa@3f40000 {
compatible = "qcom,sdx65-ipa";
--
2.7.4
^ permalink raw reply related [flat|nested] 10+ messages in thread* [PATCH v6 4/5] ARM: dts: qcom: sdx65-mtp: Enable PCIe PHY
2023-05-18 17:47 [PATCH v6 0/5] Add PCIe EP support for SDX65 Rohit Agarwal
` (2 preceding siblings ...)
2023-05-18 17:47 ` [PATCH v6 3/5] ARM: dts: qcom: sdx65: Add support for PCIe EP Rohit Agarwal
@ 2023-05-18 17:47 ` Rohit Agarwal
2023-05-18 17:47 ` [PATCH v6 5/5] ARM: dts: qcom: sdx65-mtp: Enable PCIe EP Rohit Agarwal
2023-05-25 4:54 ` [PATCH v6 0/5] Add PCIe EP support for SDX65 Bjorn Andersson
5 siblings, 0 replies; 10+ messages in thread
From: Rohit Agarwal @ 2023-05-18 17:47 UTC (permalink / raw)
To: agross, andersson, konrad.dybcio, mani, bhelgaas, lpieralisi, kw,
robh, krzysztof.kozlowski+dt, conor+dt, manivannan.sadhasivam
Cc: linux-arm-msm, linux-pci, devicetree, linux-kernel, Rohit Agarwal
Enable PCIe PHY on SDX65 MTP for PCIe EP.
Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
---
arch/arm/boot/dts/qcom-sdx65-mtp.dts | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/arch/arm/boot/dts/qcom-sdx65-mtp.dts b/arch/arm/boot/dts/qcom-sdx65-mtp.dts
index 57bc3b0..29ccb158 100644
--- a/arch/arm/boot/dts/qcom-sdx65-mtp.dts
+++ b/arch/arm/boot/dts/qcom-sdx65-mtp.dts
@@ -250,6 +250,13 @@
status = "okay";
};
+&pcie_phy {
+ vdda-phy-supply = <&vreg_l1b_1p2>;
+ vdda-pll-supply = <&vreg_l4b_0p88>;
+
+ status = "okay";
+};
+
&qpic_bam {
status = "okay";
};
--
2.7.4
^ permalink raw reply related [flat|nested] 10+ messages in thread* [PATCH v6 5/5] ARM: dts: qcom: sdx65-mtp: Enable PCIe EP
2023-05-18 17:47 [PATCH v6 0/5] Add PCIe EP support for SDX65 Rohit Agarwal
` (3 preceding siblings ...)
2023-05-18 17:47 ` [PATCH v6 4/5] ARM: dts: qcom: sdx65-mtp: Enable PCIe PHY Rohit Agarwal
@ 2023-05-18 17:47 ` Rohit Agarwal
2023-05-25 4:54 ` [PATCH v6 0/5] Add PCIe EP support for SDX65 Bjorn Andersson
5 siblings, 0 replies; 10+ messages in thread
From: Rohit Agarwal @ 2023-05-18 17:47 UTC (permalink / raw)
To: agross, andersson, konrad.dybcio, mani, bhelgaas, lpieralisi, kw,
robh, krzysztof.kozlowski+dt, conor+dt, manivannan.sadhasivam
Cc: linux-arm-msm, linux-pci, devicetree, linux-kernel, Rohit Agarwal
Enable PCIe Endpoint controller on the SDX65 MTP board based
on Qualcomm SDX65 platform.
Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
---
arch/arm/boot/dts/qcom-sdx65-mtp.dts | 35 +++++++++++++++++++++++++++++++++++
1 file changed, 35 insertions(+)
diff --git a/arch/arm/boot/dts/qcom-sdx65-mtp.dts b/arch/arm/boot/dts/qcom-sdx65-mtp.dts
index 29ccb158..02d8d6e 100644
--- a/arch/arm/boot/dts/qcom-sdx65-mtp.dts
+++ b/arch/arm/boot/dts/qcom-sdx65-mtp.dts
@@ -250,6 +250,18 @@
status = "okay";
};
+&pcie_ep {
+ pinctrl-0 = <&pcie_ep_clkreq_default
+ &pcie_ep_perst_default
+ &pcie_ep_wake_default>;
+ pinctrl-names = "default";
+
+ reset-gpios = <&tlmm 57 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 53 GPIO_ACTIVE_LOW>;
+
+ status = "okay";
+};
+
&pcie_phy {
vdda-phy-supply = <&vreg_l1b_1p2>;
vdda-pll-supply = <&vreg_l4b_0p88>;
@@ -281,6 +293,29 @@
status = "okay";
};
+&tlmm {
+ pcie_ep_clkreq_default: pcie-ep-clkreq-default-state {
+ pins = "gpio56";
+ function = "pcie_clkreq";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ pcie_ep_perst_default: pcie-ep-perst-default-state {
+ pins = "gpio57";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ pcie_ep_wake_default: pcie-ep-wake-default-state {
+ pins = "gpio53";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+};
+
&usb {
status = "okay";
};
--
2.7.4
^ permalink raw reply related [flat|nested] 10+ messages in thread* Re: [PATCH v6 0/5] Add PCIe EP support for SDX65
2023-05-18 17:47 [PATCH v6 0/5] Add PCIe EP support for SDX65 Rohit Agarwal
` (4 preceding siblings ...)
2023-05-18 17:47 ` [PATCH v6 5/5] ARM: dts: qcom: sdx65-mtp: Enable PCIe EP Rohit Agarwal
@ 2023-05-25 4:54 ` Bjorn Andersson
2023-05-25 22:13 ` Bjorn Helgaas
5 siblings, 1 reply; 10+ messages in thread
From: Bjorn Andersson @ 2023-05-25 4:54 UTC (permalink / raw)
To: agross, Rohit Agarwal, robh, bhelgaas, lpieralisi, conor+dt, kw,
manivannan.sadhasivam, krzysztof.kozlowski+dt, mani,
konrad.dybcio
Cc: linux-kernel, linux-arm-msm, devicetree, linux-pci
On Thu, 18 May 2023 23:17:48 +0530, Rohit Agarwal wrote:
> Changes in v6:
> - Rebased on top of 6.4-rc2.
>
> Changes in v5:
> - Addressed some minor comments from Konrad
> - Rebased on top of 6.3-rc5.
>
> [...]
Applied, thanks!
[1/5] dt-bindings: PCI: qcom: Add SDX65 SoC
(no commit info)
[2/5] ARM: dts: qcom: sdx65: Add support for PCIe PHY
commit: 92543a1ef22d0270425a4dfe8efe4ab30c4a8a5e
[3/5] ARM: dts: qcom: sdx65: Add support for PCIe EP
commit: 91dfb64ba70bab4d3517f4e7cb2e4cc8f5a8f81a
[4/5] ARM: dts: qcom: sdx65-mtp: Enable PCIe PHY
commit: 07bb20f207cb5868a47217681e4843f566843d29
[5/5] ARM: dts: qcom: sdx65-mtp: Enable PCIe EP
commit: e110dea61ff3f35e6d15e8c5009fb0e876a7d8ae
Best regards,
--
Bjorn Andersson <andersson@kernel.org>
^ permalink raw reply [flat|nested] 10+ messages in thread* Re: [PATCH v6 0/5] Add PCIe EP support for SDX65
2023-05-25 4:54 ` [PATCH v6 0/5] Add PCIe EP support for SDX65 Bjorn Andersson
@ 2023-05-25 22:13 ` Bjorn Helgaas
2023-05-25 23:02 ` Bjorn Andersson
0 siblings, 1 reply; 10+ messages in thread
From: Bjorn Helgaas @ 2023-05-25 22:13 UTC (permalink / raw)
To: Bjorn Andersson
Cc: agross, Rohit Agarwal, robh, bhelgaas, lpieralisi, conor+dt, kw,
manivannan.sadhasivam, krzysztof.kozlowski+dt, mani,
konrad.dybcio, linux-kernel, linux-arm-msm, devicetree, linux-pci
On Wed, May 24, 2023 at 09:54:38PM -0700, Bjorn Andersson wrote:
> On Thu, 18 May 2023 23:17:48 +0530, Rohit Agarwal wrote:
> > Changes in v6:
> > - Rebased on top of 6.4-rc2.
> >
> > Changes in v5:
> > - Addressed some minor comments from Konrad
> > - Rebased on top of 6.3-rc5.
> >
> > [...]
>
> Applied, thanks!
>
> [1/5] dt-bindings: PCI: qcom: Add SDX65 SoC
> (no commit info)
For clarification, I guess this means you did *not* apply [1/5], and
you'd like Lorenzo to apply it?
> [2/5] ARM: dts: qcom: sdx65: Add support for PCIe PHY
> commit: 92543a1ef22d0270425a4dfe8efe4ab30c4a8a5e
> [3/5] ARM: dts: qcom: sdx65: Add support for PCIe EP
> commit: 91dfb64ba70bab4d3517f4e7cb2e4cc8f5a8f81a
> [4/5] ARM: dts: qcom: sdx65-mtp: Enable PCIe PHY
> commit: 07bb20f207cb5868a47217681e4843f566843d29
> [5/5] ARM: dts: qcom: sdx65-mtp: Enable PCIe EP
> commit: e110dea61ff3f35e6d15e8c5009fb0e876a7d8ae
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH v6 0/5] Add PCIe EP support for SDX65
2023-05-25 22:13 ` Bjorn Helgaas
@ 2023-05-25 23:02 ` Bjorn Andersson
0 siblings, 0 replies; 10+ messages in thread
From: Bjorn Andersson @ 2023-05-25 23:02 UTC (permalink / raw)
To: Bjorn Helgaas
Cc: agross, Rohit Agarwal, robh, bhelgaas, lpieralisi, conor+dt, kw,
manivannan.sadhasivam, krzysztof.kozlowski+dt, mani,
konrad.dybcio, linux-kernel, linux-arm-msm, devicetree, linux-pci
On Thu, May 25, 2023 at 05:13:27PM -0500, Bjorn Helgaas wrote:
> On Wed, May 24, 2023 at 09:54:38PM -0700, Bjorn Andersson wrote:
> > On Thu, 18 May 2023 23:17:48 +0530, Rohit Agarwal wrote:
> > > Changes in v6:
> > > - Rebased on top of 6.4-rc2.
> > >
> > > Changes in v5:
> > > - Addressed some minor comments from Konrad
> > > - Rebased on top of 6.3-rc5.
> > >
> > > [...]
> >
> > Applied, thanks!
> >
> > [1/5] dt-bindings: PCI: qcom: Add SDX65 SoC
> > (no commit info)
>
> For clarification, I guess this means you did *not* apply [1/5], and
> you'd like Lorenzo to apply it?
>
That is correct, sorry for the confusion.
Thanks,
Bjorn
> > [2/5] ARM: dts: qcom: sdx65: Add support for PCIe PHY
> > commit: 92543a1ef22d0270425a4dfe8efe4ab30c4a8a5e
> > [3/5] ARM: dts: qcom: sdx65: Add support for PCIe EP
> > commit: 91dfb64ba70bab4d3517f4e7cb2e4cc8f5a8f81a
> > [4/5] ARM: dts: qcom: sdx65-mtp: Enable PCIe PHY
> > commit: 07bb20f207cb5868a47217681e4843f566843d29
> > [5/5] ARM: dts: qcom: sdx65-mtp: Enable PCIe EP
> > commit: e110dea61ff3f35e6d15e8c5009fb0e876a7d8ae
^ permalink raw reply [flat|nested] 10+ messages in thread