From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id F2E68C7EE24 for ; Fri, 2 Jun 2023 07:07:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233445AbjFBHH5 (ORCPT ); Fri, 2 Jun 2023 03:07:57 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59406 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233879AbjFBHHz (ORCPT ); Fri, 2 Jun 2023 03:07:55 -0400 Received: from muru.com (muru.com [72.249.23.125]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id A223C1AD; Fri, 2 Jun 2023 00:07:30 -0700 (PDT) Received: from localhost (localhost [127.0.0.1]) by muru.com (Postfix) with ESMTPS id 1D9FA8111; Fri, 2 Jun 2023 07:07:26 +0000 (UTC) Date: Fri, 2 Jun 2023 10:07:24 +0300 From: Tony Lindgren To: Nishanth Menon Cc: Conor Dooley , Krzysztof Kozlowski , Rob Herring , linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Tero Kristo , Vignesh Raghavendra , Udit Kumar , Nitin Yadav , Neha Malcom Francis Subject: Re: [PATCH 1/6] arm64: dts: ti: k3-j721e: Add general purpose timers Message-ID: <20230602070724.GH14287@atomide.com> References: <20230531213215.602395-1-nm@ti.com> <20230531213215.602395-2-nm@ti.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20230531213215.602395-2-nm@ti.com> Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org * Nishanth Menon [230531 21:32]: > There are 20 general purpose timers on j721e that can be used for > things like PWM using pwm-omap-dmtimer driver. There are also > additional ten timers in the MCU domain which are meant for MCU > firmware usage and hence marked reserved by default. > > The odd numbered timers have the option of being cascaded to even > timers to create a 64 bit non-atomic counter which is racy in simple > usage, hence the clock muxes are explicitly setup to individual 32 bit > counters driven off system crystal (HFOSC) as default. > > These instantiation differs from J7200 and other SoCs with the device > IDs and clocks involved for muxing. Reviewed-by: Tony Lindgren