* [PATCH 1/6] arm64: dts: ti: k3-j721e: Add general purpose timers
2023-05-31 21:32 [PATCH 0/6] arm64: dts: ti: k3-j7*: Add general purpose timers Nishanth Menon
@ 2023-05-31 21:32 ` Nishanth Menon
2023-06-02 7:07 ` Tony Lindgren
2023-05-31 21:32 ` [PATCH 2/6] arm64: dts: ti: k3-j721e: Configure pinctrl for timer IO Nishanth Menon
` (5 subsequent siblings)
6 siblings, 1 reply; 14+ messages in thread
From: Nishanth Menon @ 2023-05-31 21:32 UTC (permalink / raw)
To: Conor Dooley, Krzysztof Kozlowski, Rob Herring
Cc: linux-kernel, devicetree, linux-arm-kernel, Tero Kristo,
Vignesh Raghavendra, Nishanth Menon, Udit Kumar, Nitin Yadav,
Neha Malcom Francis, Tony Lindgren
There are 20 general purpose timers on j721e that can be used for
things like PWM using pwm-omap-dmtimer driver. There are also
additional ten timers in the MCU domain which are meant for MCU
firmware usage and hence marked reserved by default.
The odd numbered timers have the option of being cascaded to even
timers to create a 64 bit non-atomic counter which is racy in simple
usage, hence the clock muxes are explicitly setup to individual 32 bit
counters driven off system crystal (HFOSC) as default.
These instantiation differs from J7200 and other SoCs with the device
IDs and clocks involved for muxing.
Signed-off-by: Nishanth Menon <nm@ti.com>
---
arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 240 ++++++++++++++++++
.../boot/dts/ti/k3-j721e-mcu-wakeup.dtsi | 139 ++++++++++
2 files changed, 379 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
index 91f7e5d03440..57f888c9353e 100644
--- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
@@ -1023,6 +1023,246 @@ serdes4: serdes@5050000 {
};
};
+ main_timer0: timer@2400000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x2400000 0x00 0x400>;
+ interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 49 1>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 49 1>;
+ assigned-clock-parents = <&k3_clks 49 2>;
+ power-domains = <&k3_pds 49 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_timer1: timer@2410000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x2410000 0x00 0x400>;
+ interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 50 1>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 50 1>, <&k3_clks 327 0>;
+ assigned-clock-parents = <&k3_clks 50 2>, <&k3_clks 327 1>;
+ power-domains = <&k3_pds 50 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_timer2: timer@2420000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x2420000 0x00 0x400>;
+ interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 51 1>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 51 1>;
+ assigned-clock-parents = <&k3_clks 51 2>;
+ power-domains = <&k3_pds 51 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_timer3: timer@2430000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x2430000 0x00 0x400>;
+ interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 52 1>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 52 1>, <&k3_clks 328 0>;
+ assigned-clock-parents = <&k3_clks 52 2>, <&k3_clks 328 1>;
+ power-domains = <&k3_pds 52 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_timer4: timer@2440000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x2440000 0x00 0x400>;
+ interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 53 1>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 53 1>;
+ assigned-clock-parents = <&k3_clks 53 2>;
+ power-domains = <&k3_pds 53 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_timer5: timer@2450000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x2450000 0x00 0x400>;
+ interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 54 1>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 54 1>, <&k3_clks 329 0>;
+ assigned-clock-parents = <&k3_clks 54 2>, <&k3_clks 329 1>;
+ power-domains = <&k3_pds 54 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_timer6: timer@2460000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x2460000 0x00 0x400>;
+ interrupts = <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 55 1>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 55 1>;
+ assigned-clock-parents = <&k3_clks 55 2>;
+ power-domains = <&k3_pds 55 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_timer7: timer@2470000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x2470000 0x00 0x400>;
+ interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 57 1>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 57 1>, <&k3_clks 330 0>;
+ assigned-clock-parents = <&k3_clks 57 2>, <&k3_clks 330 1>;
+ power-domains = <&k3_pds 57 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_timer8: timer@2480000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x2480000 0x00 0x400>;
+ interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 58 1>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 58 1>;
+ assigned-clock-parents = <&k3_clks 58 2>;
+ power-domains = <&k3_pds 58 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_timer9: timer@2490000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x2490000 0x00 0x400>;
+ interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 59 1>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 59 1>, <&k3_clks 331 0>;
+ assigned-clock-parents = <&k3_clks 59 2>, <&k3_clks 331 1>;
+ power-domains = <&k3_pds 59 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_timer10: timer@24a0000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x24a0000 0x00 0x400>;
+ interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 60 1>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 60 1>;
+ assigned-clock-parents = <&k3_clks 60 2>;
+ power-domains = <&k3_pds 60 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_timer11: timer@24b0000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x24b0000 0x00 0x400>;
+ interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 62 1>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 62 1>, <&k3_clks 332 0>;
+ assigned-clock-parents = <&k3_clks 62 2>, <&k3_clks 332 1>;
+ power-domains = <&k3_pds 62 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_timer12: timer@24c0000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x24c0000 0x00 0x400>;
+ interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 63 1>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 63 1>;
+ assigned-clock-parents = <&k3_clks 63 2>;
+ power-domains = <&k3_pds 63 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_timer13: timer@24d0000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x24d0000 0x00 0x400>;
+ interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 64 1>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 64 1>, <&k3_clks 333 0>;
+ assigned-clock-parents = <&k3_clks 64 2>, <&k3_clks 333 1>;
+ power-domains = <&k3_pds 64 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_timer14: timer@24e0000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x24e0000 0x00 0x400>;
+ interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 65 1>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 65 1>;
+ assigned-clock-parents = <&k3_clks 65 2>;
+ power-domains = <&k3_pds 65 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_timer15: timer@24f0000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x24f0000 0x00 0x400>;
+ interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 66 1>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 66 1>, <&k3_clks 334 0>;
+ assigned-clock-parents = <&k3_clks 66 2>, <&k3_clks 334 1>;
+ power-domains = <&k3_pds 66 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_timer16: timer@2500000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x2500000 0x00 0x400>;
+ interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 67 1>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 67 1>;
+ assigned-clock-parents = <&k3_clks 67 2>;
+ power-domains = <&k3_pds 67 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_timer17: timer@2510000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x2510000 0x00 0x400>;
+ interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 68 1>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 68 1>, <&k3_clks 335 0>;
+ assigned-clock-parents = <&k3_clks 68 2>, <&k3_clks 335 1>;
+ power-domains = <&k3_pds 68 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_timer18: timer@2520000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x2520000 0x00 0x400>;
+ interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 69 1>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 69 1>;
+ assigned-clock-parents = <&k3_clks 69 2>;
+ power-domains = <&k3_pds 69 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_timer19: timer@2530000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x2530000 0x00 0x400>;
+ interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 70 1>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 70 1>, <&k3_clks 336 0>;
+ assigned-clock-parents = <&k3_clks 70 2>, <&k3_clks 336 1>;
+ power-domains = <&k3_pds 70 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
main_uart0: serial@2800000 {
compatible = "ti,j721e-uart", "ti,am654-uart";
reg = <0x00 0x02800000 0x00 0x100>;
diff --git a/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi
index 4ea95ed5d12c..053c771129d6 100644
--- a/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi
@@ -70,6 +70,145 @@ mcu_ram: sram@41c00000 {
#size-cells = <1>;
};
+ mcu_timer0: timer@40400000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x40400000 0x00 0x400>;
+ interrupts = <GIC_SPI 816 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 35 1>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 35 1>;
+ assigned-clock-parents = <&k3_clks 35 2>;
+ power-domains = <&k3_pds 35 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ /* Non-MPU Firmware usage */
+ status = "reserved";
+ };
+
+ mcu_timer1: timer@40410000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x40410000 0x00 0x400>;
+ interrupts = <GIC_SPI 817 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 71 1>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 71 1>, <&k3_clks 322 0>;
+ assigned-clock-parents = <&k3_clks 71 2>, <&k3_clks 322 1>;
+ power-domains = <&k3_pds 71 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ /* Non-MPU Firmware usage */
+ status = "reserved";
+ };
+
+ mcu_timer2: timer@40420000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x40420000 0x00 0x400>;
+ interrupts = <GIC_SPI 818 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 72 1>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 72 1>;
+ assigned-clock-parents = <&k3_clks 72 2>;
+ power-domains = <&k3_pds 72 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ /* Non-MPU Firmware usage */
+ status = "reserved";
+ };
+
+ mcu_timer3: timer@40430000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x40430000 0x00 0x400>;
+ interrupts = <GIC_SPI 819 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 73 1>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 73 1>, <&k3_clks 323 0>;
+ assigned-clock-parents = <&k3_clks 73 2>, <&k3_clks 323 1>;
+ power-domains = <&k3_pds 73 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ /* Non-MPU Firmware usage */
+ status = "reserved";
+ };
+
+ mcu_timer4: timer@40440000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x40440000 0x00 0x400>;
+ interrupts = <GIC_SPI 820 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 74 1>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 74 1>;
+ assigned-clock-parents = <&k3_clks 74 2>;
+ power-domains = <&k3_pds 74 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ /* Non-MPU Firmware usage */
+ status = "reserved";
+ };
+
+ mcu_timer5: timer@40450000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x40450000 0x00 0x400>;
+ interrupts = <GIC_SPI 821 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 75 1>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 75 1>, <&k3_clks 324 0>;
+ assigned-clock-parents = <&k3_clks 75 2>, <&k3_clks 324 1>;
+ power-domains = <&k3_pds 75 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ /* Non-MPU Firmware usage */
+ status = "reserved";
+ };
+
+ mcu_timer6: timer@40460000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x40460000 0x00 0x400>;
+ interrupts = <GIC_SPI 822 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 76 1>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 76 1>;
+ assigned-clock-parents = <&k3_clks 76 2>;
+ power-domains = <&k3_pds 76 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ /* Non-MPU Firmware usage */
+ status = "reserved";
+ };
+
+ mcu_timer7: timer@40470000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x40470000 0x00 0x400>;
+ interrupts = <GIC_SPI 823 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 77 1>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 77 1>, <&k3_clks 325 0>;
+ assigned-clock-parents = <&k3_clks 77 2>, <&k3_clks 325 1>;
+ power-domains = <&k3_pds 77 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ /* Non-MPU Firmware usage */
+ status = "reserved";
+ };
+
+ mcu_timer8: timer@40480000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x40480000 0x00 0x400>;
+ interrupts = <GIC_SPI 824 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 78 1>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 78 1>;
+ assigned-clock-parents = <&k3_clks 78 2>;
+ power-domains = <&k3_pds 78 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ /* Non-MPU Firmware usage */
+ status = "reserved";
+ };
+
+ mcu_timer9: timer@40490000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x40490000 0x00 0x400>;
+ interrupts = <GIC_SPI 825 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 79 1>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 79 1>, <&k3_clks 326 0>;
+ assigned-clock-parents = <&k3_clks 79 2>, <&k3_clks 326 1>;
+ power-domains = <&k3_pds 79 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ /* Non-MPU Firmware usage */
+ status = "reserved";
+ };
wkup_uart0: serial@42300000 {
compatible = "ti,j721e-uart", "ti,am654-uart";
reg = <0x00 0x42300000 0x00 0x100>;
--
2.40.0
^ permalink raw reply related [flat|nested] 14+ messages in thread* Re: [PATCH 1/6] arm64: dts: ti: k3-j721e: Add general purpose timers
2023-05-31 21:32 ` [PATCH 1/6] arm64: dts: ti: k3-j721e: " Nishanth Menon
@ 2023-06-02 7:07 ` Tony Lindgren
0 siblings, 0 replies; 14+ messages in thread
From: Tony Lindgren @ 2023-06-02 7:07 UTC (permalink / raw)
To: Nishanth Menon
Cc: Conor Dooley, Krzysztof Kozlowski, Rob Herring, linux-kernel,
devicetree, linux-arm-kernel, Tero Kristo, Vignesh Raghavendra,
Udit Kumar, Nitin Yadav, Neha Malcom Francis
* Nishanth Menon <nm@ti.com> [230531 21:32]:
> There are 20 general purpose timers on j721e that can be used for
> things like PWM using pwm-omap-dmtimer driver. There are also
> additional ten timers in the MCU domain which are meant for MCU
> firmware usage and hence marked reserved by default.
>
> The odd numbered timers have the option of being cascaded to even
> timers to create a 64 bit non-atomic counter which is racy in simple
> usage, hence the clock muxes are explicitly setup to individual 32 bit
> counters driven off system crystal (HFOSC) as default.
>
> These instantiation differs from J7200 and other SoCs with the device
> IDs and clocks involved for muxing.
Reviewed-by: Tony Lindgren <tony@atomide.com>
^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH 2/6] arm64: dts: ti: k3-j721e: Configure pinctrl for timer IO
2023-05-31 21:32 [PATCH 0/6] arm64: dts: ti: k3-j7*: Add general purpose timers Nishanth Menon
2023-05-31 21:32 ` [PATCH 1/6] arm64: dts: ti: k3-j721e: " Nishanth Menon
@ 2023-05-31 21:32 ` Nishanth Menon
2023-06-02 7:08 ` Tony Lindgren
2023-05-31 21:32 ` [PATCH 3/6] arm64: dts: ti: k3-j721s2: Add general purpose timers Nishanth Menon
` (4 subsequent siblings)
6 siblings, 1 reply; 14+ messages in thread
From: Nishanth Menon @ 2023-05-31 21:32 UTC (permalink / raw)
To: Conor Dooley, Krzysztof Kozlowski, Rob Herring
Cc: linux-kernel, devicetree, linux-arm-kernel, Tero Kristo,
Vignesh Raghavendra, Nishanth Menon, Udit Kumar, Nitin Yadav,
Neha Malcom Francis, Tony Lindgren
There are timer IO pads in the MCU domain, and in the MAIN domain. These
pads can be muxed for the related timers.
There are timer IO control registers for input and output. The registers
for CTRLMMR_TIMER*_CTRL and CTRLMMR_MCU_TIMER*_CTRL are used to control
the input. The registers for CTCTRLMMR_TIMERIO*_CTRL and
CTRLMMR_MCU_TIMERIO*_CTRL the output.
The multiplexing is documented in Technical Reference Manual[1] under
"Timer IO Muxing Control Registers" and "Timer IO Muxing Control
Registers", and the "Timers Overview" chapters.
We do not expose the cascade_en bit due to the racy usage of
independent 32 bit registers in-line with the timer instantiation in
the device tree. The MCU timer controls are also marked as reserved for
usage by the MCU firmware.
[1] http://www.ti.com/lit/pdf/spruil1
Signed-off-by: Nishanth Menon <nm@ti.com>
---
arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 18 +++++++++++++++
.../boot/dts/ti/k3-j721e-mcu-wakeup.dtsi | 22 +++++++++++++++++++
2 files changed, 40 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
index 57f888c9353e..35b943e7f5c3 100644
--- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
@@ -548,6 +548,24 @@ main_pmx0: pinctrl@11c000 {
pinctrl-single,function-mask = <0xffffffff>;
};
+ /* TIMERIO pad input CTRLMMR_TIMER*_CTRL registers */
+ main_timerio_input: pinctrl@104200 {
+ compatible = "pinctrl-single";
+ reg = <0x00 0x104200 0x00 0x50>;
+ #pinctrl-cells = <1>;
+ pinctrl-single,register-width = <32>;
+ pinctrl-single,function-mask = <0x00000007>;
+ };
+
+ /* TIMERIO pad output CTCTRLMMR_TIMERIO*_CTRL registers */
+ main_timerio_output: pinctrl@104280 {
+ compatible = "pinctrl-single";
+ reg = <0x00 0x104280 0x00 0x20>;
+ #pinctrl-cells = <1>;
+ pinctrl-single,register-width = <32>;
+ pinctrl-single,function-mask = <0x0000001f>;
+ };
+
serdes_wiz0: wiz@5000000 {
compatible = "ti,j721e-wiz-16g";
#address-cells = <1>;
diff --git a/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi
index 053c771129d6..3b4295eab6f6 100644
--- a/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi
@@ -62,6 +62,28 @@ wkup_pmx0: pinctrl@4301c000 {
pinctrl-single,function-mask = <0xffffffff>;
};
+ /* MCU_TIMERIO pad input CTRLMMR_MCU_TIMER*_CTRL registers */
+ mcu_timerio_input: pinctrl@40f04200 {
+ compatible = "pinctrl-single";
+ reg = <0x00 0x40f04200 0x00 0x28>;
+ #pinctrl-cells = <1>;
+ pinctrl-single,register-width = <32>;
+ pinctrl-single,function-mask = <0x0000000f>;
+ /* Non-MPU Firmware usage */
+ status = "reserved";
+ };
+
+ /* MCU_TIMERIO pad output CTRLMMR_MCU_TIMERIO*_CTRL registers */
+ mcu_timerio_output: pinctrl@40f04280 {
+ compatible = "pinctrl-single";
+ reg = <0x00 0x40f04280 0x00 0x28>;
+ #pinctrl-cells = <1>;
+ pinctrl-single,register-width = <32>;
+ pinctrl-single,function-mask = <0x0000000f>;
+ /* Non-MPU Firmware usage */
+ status = "reserved";
+ };
+
mcu_ram: sram@41c00000 {
compatible = "mmio-sram";
reg = <0x00 0x41c00000 0x00 0x100000>;
--
2.40.0
^ permalink raw reply related [flat|nested] 14+ messages in thread* Re: [PATCH 2/6] arm64: dts: ti: k3-j721e: Configure pinctrl for timer IO
2023-05-31 21:32 ` [PATCH 2/6] arm64: dts: ti: k3-j721e: Configure pinctrl for timer IO Nishanth Menon
@ 2023-06-02 7:08 ` Tony Lindgren
0 siblings, 0 replies; 14+ messages in thread
From: Tony Lindgren @ 2023-06-02 7:08 UTC (permalink / raw)
To: Nishanth Menon
Cc: Conor Dooley, Krzysztof Kozlowski, Rob Herring, linux-kernel,
devicetree, linux-arm-kernel, Tero Kristo, Vignesh Raghavendra,
Udit Kumar, Nitin Yadav, Neha Malcom Francis
* Nishanth Menon <nm@ti.com> [230531 21:32]:
> There are timer IO pads in the MCU domain, and in the MAIN domain. These
> pads can be muxed for the related timers.
>
> There are timer IO control registers for input and output. The registers
> for CTRLMMR_TIMER*_CTRL and CTRLMMR_MCU_TIMER*_CTRL are used to control
> the input. The registers for CTCTRLMMR_TIMERIO*_CTRL and
> CTRLMMR_MCU_TIMERIO*_CTRL the output.
>
> The multiplexing is documented in Technical Reference Manual[1] under
> "Timer IO Muxing Control Registers" and "Timer IO Muxing Control
> Registers", and the "Timers Overview" chapters.
>
> We do not expose the cascade_en bit due to the racy usage of
> independent 32 bit registers in-line with the timer instantiation in
> the device tree. The MCU timer controls are also marked as reserved for
> usage by the MCU firmware.
Reviewed-by: Tony Lindgren <tony@atomide.com>
^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH 3/6] arm64: dts: ti: k3-j721s2: Add general purpose timers
2023-05-31 21:32 [PATCH 0/6] arm64: dts: ti: k3-j7*: Add general purpose timers Nishanth Menon
2023-05-31 21:32 ` [PATCH 1/6] arm64: dts: ti: k3-j721e: " Nishanth Menon
2023-05-31 21:32 ` [PATCH 2/6] arm64: dts: ti: k3-j721e: Configure pinctrl for timer IO Nishanth Menon
@ 2023-05-31 21:32 ` Nishanth Menon
2023-06-02 7:09 ` Tony Lindgren
2023-05-31 21:32 ` [PATCH 4/6] arm64: dts: ti: k3-j721s2: Configure pinctrl for timer IO Nishanth Menon
` (3 subsequent siblings)
6 siblings, 1 reply; 14+ messages in thread
From: Nishanth Menon @ 2023-05-31 21:32 UTC (permalink / raw)
To: Conor Dooley, Krzysztof Kozlowski, Rob Herring
Cc: linux-kernel, devicetree, linux-arm-kernel, Tero Kristo,
Vignesh Raghavendra, Nishanth Menon, Udit Kumar, Nitin Yadav,
Neha Malcom Francis, Tony Lindgren
There are 20 general purpose timers on j721s2 that can be used for
things like PWM using pwm-omap-dmtimer driver. There are also
additional ten timers in the MCU domain which are meant for MCU
firmware usage and hence marked reserved by default.
Though the count is similar to J721e/J7200, the device IDs and clocks
used in j721s2 are different with the option of certain clocks having
options of additional clock muxes. Since there is very minimal reuse,
it is cleaner to integrate as part of SoC files itself. The defaults
are configured for clocking the timers from system clock(HFOSC0).
Signed-off-by: Nishanth Menon <nm@ti.com>
---
arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi | 240 ++++++++++++++++++
.../boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi | 140 ++++++++++
2 files changed, 380 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
index 2dd7865f7654..3f00fa4e9780 100644
--- a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
@@ -91,6 +91,246 @@ rng: rng@4e10000 {
};
};
+ main_timer0: timer@2400000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x2400000 0x00 0x400>;
+ interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 63 1>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 63 1>;
+ assigned-clock-parents = <&k3_clks 63 2>;
+ power-domains = <&k3_pds 63 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_timer1: timer@2410000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x2410000 0x00 0x400>;
+ interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 64 1>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 64 1>;
+ assigned-clock-parents = <&k3_clks 64 2>;
+ power-domains = <&k3_pds 64 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_timer2: timer@2420000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x2420000 0x00 0x400>;
+ interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 65 1>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 65 1>;
+ assigned-clock-parents = <&k3_clks 65 2>;
+ power-domains = <&k3_pds 65 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_timer3: timer@2430000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x2430000 0x00 0x400>;
+ interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 66 1>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 66 1>;
+ assigned-clock-parents = <&k3_clks 66 2>;
+ power-domains = <&k3_pds 66 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_timer4: timer@2440000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x2440000 0x00 0x400>;
+ interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 67 1>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 67 1>;
+ assigned-clock-parents = <&k3_clks 67 2>;
+ power-domains = <&k3_pds 67 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_timer5: timer@2450000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x2450000 0x00 0x400>;
+ interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 68 1>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 68 1>;
+ assigned-clock-parents = <&k3_clks 68 2>;
+ power-domains = <&k3_pds 68 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_timer6: timer@2460000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x2460000 0x00 0x400>;
+ interrupts = <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 69 1>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 69 1>;
+ assigned-clock-parents = <&k3_clks 69 2>;
+ power-domains = <&k3_pds 69 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_timer7: timer@2470000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x2470000 0x00 0x400>;
+ interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 70 1>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 70 1>;
+ assigned-clock-parents = <&k3_clks 70 2>;
+ power-domains = <&k3_pds 70 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_timer8: timer@2480000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x2480000 0x00 0x400>;
+ interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 71 1>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 71 1>;
+ assigned-clock-parents = <&k3_clks 71 2>;
+ power-domains = <&k3_pds 71 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_timer9: timer@2490000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x2490000 0x00 0x400>;
+ interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 72 1>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 72 1>;
+ assigned-clock-parents = <&k3_clks 72 2>;
+ power-domains = <&k3_pds 72 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_timer10: timer@24a0000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x24a0000 0x00 0x400>;
+ interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 73 1>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 73 1>;
+ assigned-clock-parents = <&k3_clks 73 2>;
+ power-domains = <&k3_pds 73 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_timer11: timer@24b0000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x24b0000 0x00 0x400>;
+ interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 74 1>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 74 1>;
+ assigned-clock-parents = <&k3_clks 74 2>;
+ power-domains = <&k3_pds 74 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_timer12: timer@24c0000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x24c0000 0x00 0x400>;
+ interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 75 1>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 75 1>;
+ assigned-clock-parents = <&k3_clks 75 2>;
+ power-domains = <&k3_pds 75 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_timer13: timer@24d0000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x24d0000 0x00 0x400>;
+ interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 76 1>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 76 1>;
+ assigned-clock-parents = <&k3_clks 76 2>;
+ power-domains = <&k3_pds 76 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_timer14: timer@24e0000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x24e0000 0x00 0x400>;
+ interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 77 1>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 77 1>;
+ assigned-clock-parents = <&k3_clks 77 2>;
+ power-domains = <&k3_pds 77 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_timer15: timer@24f0000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x24f0000 0x00 0x400>;
+ interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 78 1>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 78 1>;
+ assigned-clock-parents = <&k3_clks 78 2>;
+ power-domains = <&k3_pds 78 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_timer16: timer@2500000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x2500000 0x00 0x400>;
+ interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 79 1>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 79 1>;
+ assigned-clock-parents = <&k3_clks 79 2>;
+ power-domains = <&k3_pds 79 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_timer17: timer@2510000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x2510000 0x00 0x400>;
+ interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 80 1>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 80 1>;
+ assigned-clock-parents = <&k3_clks 80 2>;
+ power-domains = <&k3_pds 80 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_timer18: timer@2520000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x2520000 0x00 0x400>;
+ interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 81 1>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 81 1>;
+ assigned-clock-parents = <&k3_clks 81 2>;
+ power-domains = <&k3_pds 81 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_timer19: timer@2530000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x2530000 0x00 0x400>;
+ interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 82 1>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 82 1>;
+ assigned-clock-parents = <&k3_clks 82 2>;
+ power-domains = <&k3_pds 82 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
main_uart0: serial@2800000 {
compatible = "ti,j721e-uart", "ti,am654-uart";
reg = <0x00 0x02800000 0x00 0x200>;
diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi
index b75057c49731..758528076014 100644
--- a/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi
@@ -98,6 +98,146 @@ phy_gmii_sel: phy@4040 {
};
+ mcu_timer0: timer@40400000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x40400000 0x00 0x400>;
+ interrupts = <GIC_SPI 816 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 35 1>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 35 1>;
+ assigned-clock-parents = <&k3_clks 35 2>;
+ power-domains = <&k3_pds 35 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ /* Non-MPU Firmware usage */
+ status = "reserved";
+ };
+
+ mcu_timer1: timer@40410000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x40410000 0x00 0x400>;
+ interrupts = <GIC_SPI 817 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 83 1>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 83 1>;
+ assigned-clock-parents = <&k3_clks 83 2>;
+ power-domains = <&k3_pds 83 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ /* Non-MPU Firmware usage */
+ status = "reserved";
+ };
+
+ mcu_timer2: timer@40420000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x40420000 0x00 0x400>;
+ interrupts = <GIC_SPI 818 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 84 1>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 84 1>;
+ assigned-clock-parents = <&k3_clks 84 2>;
+ power-domains = <&k3_pds 84 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ /* Non-MPU Firmware usage */
+ status = "reserved";
+ };
+
+ mcu_timer3: timer@40430000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x40430000 0x00 0x400>;
+ interrupts = <GIC_SPI 819 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 85 1>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 85 1>;
+ assigned-clock-parents = <&k3_clks 85 2>;
+ power-domains = <&k3_pds 85 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ /* Non-MPU Firmware usage */
+ status = "reserved";
+ };
+
+ mcu_timer4: timer@40440000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x40440000 0x00 0x400>;
+ interrupts = <GIC_SPI 820 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 86 1>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 86 1>;
+ assigned-clock-parents = <&k3_clks 86 2>;
+ power-domains = <&k3_pds 86 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ /* Non-MPU Firmware usage */
+ status = "reserved";
+ };
+
+ mcu_timer5: timer@40450000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x40450000 0x00 0x400>;
+ interrupts = <GIC_SPI 821 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 87 1>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 87 1>;
+ assigned-clock-parents = <&k3_clks 87 2>;
+ power-domains = <&k3_pds 87 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ /* Non-MPU Firmware usage */
+ status = "reserved";
+ };
+
+ mcu_timer6: timer@40460000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x40460000 0x00 0x400>;
+ interrupts = <GIC_SPI 822 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 88 1>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 88 1>;
+ assigned-clock-parents = <&k3_clks 88 2>;
+ power-domains = <&k3_pds 88 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ /* Non-MPU Firmware usage */
+ status = "reserved";
+ };
+
+ mcu_timer7: timer@40470000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x40470000 0x00 0x400>;
+ interrupts = <GIC_SPI 823 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 89 1>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 89 1>;
+ assigned-clock-parents = <&k3_clks 89 2>;
+ power-domains = <&k3_pds 89 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ /* Non-MPU Firmware usage */
+ status = "reserved";
+ };
+
+ mcu_timer8: timer@40480000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x40480000 0x00 0x400>;
+ interrupts = <GIC_SPI 824 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 90 1>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 90 1>;
+ assigned-clock-parents = <&k3_clks 90 2>;
+ power-domains = <&k3_pds 90 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ /* Non-MPU Firmware usage */
+ status = "reserved";
+ };
+
+ mcu_timer9: timer@40490000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x40490000 0x00 0x400>;
+ interrupts = <GIC_SPI 825 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 91 1>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 91 1>;
+ assigned-clock-parents = <&k3_clks 91 2>;
+ power-domains = <&k3_pds 91 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ /* Non-MPU Firmware usage */
+ status = "reserved";
+ };
+
wkup_uart0: serial@42300000 {
compatible = "ti,j721e-uart", "ti,am654-uart";
reg = <0x00 0x42300000 0x00 0x200>;
--
2.40.0
^ permalink raw reply related [flat|nested] 14+ messages in thread* Re: [PATCH 3/6] arm64: dts: ti: k3-j721s2: Add general purpose timers
2023-05-31 21:32 ` [PATCH 3/6] arm64: dts: ti: k3-j721s2: Add general purpose timers Nishanth Menon
@ 2023-06-02 7:09 ` Tony Lindgren
0 siblings, 0 replies; 14+ messages in thread
From: Tony Lindgren @ 2023-06-02 7:09 UTC (permalink / raw)
To: Nishanth Menon
Cc: Conor Dooley, Krzysztof Kozlowski, Rob Herring, linux-kernel,
devicetree, linux-arm-kernel, Tero Kristo, Vignesh Raghavendra,
Udit Kumar, Nitin Yadav, Neha Malcom Francis
* Nishanth Menon <nm@ti.com> [230531 21:32]:
> There are 20 general purpose timers on j721s2 that can be used for
> things like PWM using pwm-omap-dmtimer driver. There are also
> additional ten timers in the MCU domain which are meant for MCU
> firmware usage and hence marked reserved by default.
>
> Though the count is similar to J721e/J7200, the device IDs and clocks
> used in j721s2 are different with the option of certain clocks having
> options of additional clock muxes. Since there is very minimal reuse,
> it is cleaner to integrate as part of SoC files itself. The defaults
> are configured for clocking the timers from system clock(HFOSC0).
Reviewed-by: Tony Lindgren <tony@atomide.com>
^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH 4/6] arm64: dts: ti: k3-j721s2: Configure pinctrl for timer IO
2023-05-31 21:32 [PATCH 0/6] arm64: dts: ti: k3-j7*: Add general purpose timers Nishanth Menon
` (2 preceding siblings ...)
2023-05-31 21:32 ` [PATCH 3/6] arm64: dts: ti: k3-j721s2: Add general purpose timers Nishanth Menon
@ 2023-05-31 21:32 ` Nishanth Menon
2023-06-02 7:09 ` Tony Lindgren
2023-05-31 21:32 ` [PATCH 5/6] arm64: dts: ti: k3-j784s4: Add general purpose timers Nishanth Menon
` (2 subsequent siblings)
6 siblings, 1 reply; 14+ messages in thread
From: Nishanth Menon @ 2023-05-31 21:32 UTC (permalink / raw)
To: Conor Dooley, Krzysztof Kozlowski, Rob Herring
Cc: linux-kernel, devicetree, linux-arm-kernel, Tero Kristo,
Vignesh Raghavendra, Nishanth Menon, Udit Kumar, Nitin Yadav,
Neha Malcom Francis, Tony Lindgren
There are timer IO pads in the MCU domain, and in the MAIN domain. These
pads can be muxed for the related timers.
The details of the multiplexing can be found in the register
documentation and Technical Reference Manual[1].
These are similar to J721e/J7200, but have different mux capabilities.
[1] https://www.ti.com/lit/zip/spruj28
Signed-off-by: Nishanth Menon <nm@ti.com>
---
arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi | 18 +++++++++++++++
.../boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi | 22 +++++++++++++++++++
2 files changed, 40 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
index 3f00fa4e9780..ced187ad802d 100644
--- a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
@@ -72,6 +72,24 @@ main_pmx0: pinctrl@11c000 {
pinctrl-single,function-mask = <0xffffffff>;
};
+ /* TIMERIO pad input CTRLMMR_TIMER*_CTRL registers */
+ main_timerio_input: pinctrl@104200 {
+ compatible = "pinctrl-single";
+ reg = <0x00 0x104200 0x00 0x50>;
+ #pinctrl-cells = <1>;
+ pinctrl-single,register-width = <32>;
+ pinctrl-single,function-mask = <0x00000007>;
+ };
+
+ /* TIMERIO pad output CTCTRLMMR_TIMERIO*_CTRL registers */
+ main_timerio_output: pinctrl@104280 {
+ compatible = "pinctrl-single";
+ reg = <0x00 0x104280 0x00 0x20>;
+ #pinctrl-cells = <1>;
+ pinctrl-single,register-width = <32>;
+ pinctrl-single,function-mask = <0x0000001f>;
+ };
+
main_crypto: crypto@4e00000 {
compatible = "ti,j721e-sa2ul";
reg = <0x00 0x04e00000 0x00 0x1200>;
diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi
index 758528076014..f563dcc7b3f8 100644
--- a/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi
@@ -71,6 +71,28 @@ wkup_pmx0: pinctrl@4301c000 {
pinctrl-single,function-mask = <0xffffffff>;
};
+ /* MCU_TIMERIO pad input CTRLMMR_MCU_TIMER*_CTRL registers */
+ mcu_timerio_input: pinctrl@40f04200 {
+ compatible = "pinctrl-single";
+ reg = <0x00 0x40f04200 0x00 0x28>;
+ #pinctrl-cells = <1>;
+ pinctrl-single,register-width = <32>;
+ pinctrl-single,function-mask = <0x0000000f>;
+ /* Non-MPU Firmware usage */
+ status = "reserved";
+ };
+
+ /* MCU_TIMERIO pad output CTRLMMR_MCU_TIMERIO*_CTRL registers */
+ mcu_timerio_output: pinctrl@40f04280 {
+ compatible = "pinctrl-single";
+ reg = <0x00 0x40f04280 0x00 0x28>;
+ #pinctrl-cells = <1>;
+ pinctrl-single,register-width = <32>;
+ pinctrl-single,function-mask = <0x0000000f>;
+ /* Non-MPU Firmware usage */
+ status = "reserved";
+ };
+
wkup_gpio_intr: interrupt-controller@42200000 {
compatible = "ti,sci-intr";
reg = <0x00 0x42200000 0x00 0x400>;
--
2.40.0
^ permalink raw reply related [flat|nested] 14+ messages in thread* Re: [PATCH 4/6] arm64: dts: ti: k3-j721s2: Configure pinctrl for timer IO
2023-05-31 21:32 ` [PATCH 4/6] arm64: dts: ti: k3-j721s2: Configure pinctrl for timer IO Nishanth Menon
@ 2023-06-02 7:09 ` Tony Lindgren
0 siblings, 0 replies; 14+ messages in thread
From: Tony Lindgren @ 2023-06-02 7:09 UTC (permalink / raw)
To: Nishanth Menon
Cc: Conor Dooley, Krzysztof Kozlowski, Rob Herring, linux-kernel,
devicetree, linux-arm-kernel, Tero Kristo, Vignesh Raghavendra,
Udit Kumar, Nitin Yadav, Neha Malcom Francis
* Nishanth Menon <nm@ti.com> [230531 21:32]:
> There are timer IO pads in the MCU domain, and in the MAIN domain. These
> pads can be muxed for the related timers.
>
> The details of the multiplexing can be found in the register
> documentation and Technical Reference Manual[1].
>
> These are similar to J721e/J7200, but have different mux capabilities.
Reviewed-by: Tony Lindgren <tony@atomide.com>
^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH 5/6] arm64: dts: ti: k3-j784s4: Add general purpose timers
2023-05-31 21:32 [PATCH 0/6] arm64: dts: ti: k3-j7*: Add general purpose timers Nishanth Menon
` (3 preceding siblings ...)
2023-05-31 21:32 ` [PATCH 4/6] arm64: dts: ti: k3-j721s2: Configure pinctrl for timer IO Nishanth Menon
@ 2023-05-31 21:32 ` Nishanth Menon
2023-06-02 7:10 ` Tony Lindgren
2023-05-31 21:32 ` [PATCH 6/6] arm64: dts: ti: k3-j784s4: Configure pinctrl for timer IO Nishanth Menon
2023-06-15 13:19 ` [PATCH 0/6] arm64: dts: ti: k3-j7*: Add general purpose timers Vignesh Raghavendra
6 siblings, 1 reply; 14+ messages in thread
From: Nishanth Menon @ 2023-05-31 21:32 UTC (permalink / raw)
To: Conor Dooley, Krzysztof Kozlowski, Rob Herring
Cc: linux-kernel, devicetree, linux-arm-kernel, Tero Kristo,
Vignesh Raghavendra, Nishanth Menon, Udit Kumar, Nitin Yadav,
Neha Malcom Francis, Tony Lindgren
There are 20 general purpose timers on j784s4 that can be used for
things like PWM using pwm-omap-dmtimer driver. There are also
additional ten timers in the MCU domain which are meant for MCU
firmware usage and hence marked reserved by default.
Though the count is similar to J721e/J7200/j721s2, the device IDs
and clocks used in j784s4 are different with the option of certain
clocks having options of additional clock muxes. Since there is very
minimal reuse, it is cleaner to integrate as part of SoC files itself.
The defaults are configured for clocking the timers from system
clock(HFOSC0).
Signed-off-by: Nishanth Menon <nm@ti.com>
---
arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi | 240 ++++++++++++++++++
.../boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi | 140 ++++++++++
2 files changed, 380 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
index e9169eb358c1..f2ddd79f748d 100644
--- a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
@@ -91,6 +91,246 @@ rng: rng@4e10000 {
};
};
+ main_timer0: timer@2400000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x2400000 0x00 0x400>;
+ interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 97 2>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 97 2>;
+ assigned-clock-parents = <&k3_clks 97 3>;
+ power-domains = <&k3_pds 97 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_timer1: timer@2410000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x2410000 0x00 0x400>;
+ interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 98 2>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 98 2>;
+ assigned-clock-parents = <&k3_clks 98 3>;
+ power-domains = <&k3_pds 98 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_timer2: timer@2420000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x2420000 0x00 0x400>;
+ interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 99 2>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 99 2>;
+ assigned-clock-parents = <&k3_clks 99 3>;
+ power-domains = <&k3_pds 99 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_timer3: timer@2430000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x2430000 0x00 0x400>;
+ interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 100 2>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 100 2>;
+ assigned-clock-parents = <&k3_clks 100 3>;
+ power-domains = <&k3_pds 100 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_timer4: timer@2440000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x2440000 0x00 0x400>;
+ interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 101 2>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 101 2>;
+ assigned-clock-parents = <&k3_clks 101 3>;
+ power-domains = <&k3_pds 101 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_timer5: timer@2450000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x2450000 0x00 0x400>;
+ interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 102 2>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 102 2>;
+ assigned-clock-parents = <&k3_clks 102 3>;
+ power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_timer6: timer@2460000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x2460000 0x00 0x400>;
+ interrupts = <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 103 2>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 103 2>;
+ assigned-clock-parents = <&k3_clks 103 3>;
+ power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_timer7: timer@2470000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x2470000 0x00 0x400>;
+ interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 104 2>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 104 2>;
+ assigned-clock-parents = <&k3_clks 104 3>;
+ power-domains = <&k3_pds 104 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_timer8: timer@2480000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x2480000 0x00 0x400>;
+ interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 105 2>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 105 2>;
+ assigned-clock-parents = <&k3_clks 105 3>;
+ power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_timer9: timer@2490000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x2490000 0x00 0x400>;
+ interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 106 2>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 106 2>;
+ assigned-clock-parents = <&k3_clks 106 3>;
+ power-domains = <&k3_pds 106 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_timer10: timer@24a0000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x24a0000 0x00 0x400>;
+ interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 107 2>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 107 2>;
+ assigned-clock-parents = <&k3_clks 107 3>;
+ power-domains = <&k3_pds 107 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_timer11: timer@24b0000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x24b0000 0x00 0x400>;
+ interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 108 2>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 108 2>;
+ assigned-clock-parents = <&k3_clks 108 3>;
+ power-domains = <&k3_pds 108 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_timer12: timer@24c0000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x24c0000 0x00 0x400>;
+ interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 109 2>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 109 2>;
+ assigned-clock-parents = <&k3_clks 109 3>;
+ power-domains = <&k3_pds 109 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_timer13: timer@24d0000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x24d0000 0x00 0x400>;
+ interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 110 2>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 110 2>;
+ assigned-clock-parents = <&k3_clks 110 3>;
+ power-domains = <&k3_pds 110 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_timer14: timer@24e0000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x24e0000 0x00 0x400>;
+ interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 111 2>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 111 2>;
+ assigned-clock-parents = <&k3_clks 111 3>;
+ power-domains = <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_timer15: timer@24f0000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x24f0000 0x00 0x400>;
+ interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 112 2>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 112 2>;
+ assigned-clock-parents = <&k3_clks 112 3>;
+ power-domains = <&k3_pds 112 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_timer16: timer@2500000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x2500000 0x00 0x400>;
+ interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 113 2>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 113 2>;
+ assigned-clock-parents = <&k3_clks 113 3>;
+ power-domains = <&k3_pds 113 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_timer17: timer@2510000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x2510000 0x00 0x400>;
+ interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 114 2>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 114 2>;
+ assigned-clock-parents = <&k3_clks 114 3>;
+ power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_timer18: timer@2520000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x2520000 0x00 0x400>;
+ interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 115 2>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 115 2>;
+ assigned-clock-parents = <&k3_clks 115 3>;
+ power-domains = <&k3_pds 115 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_timer19: timer@2530000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x2530000 0x00 0x400>;
+ interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 116 2>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 116 2>;
+ assigned-clock-parents = <&k3_clks 116 3>;
+ power-domains = <&k3_pds 116 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
main_uart0: serial@2800000 {
compatible = "ti,j721e-uart", "ti,am654-uart";
reg = <0x00 0x02800000 0x00 0x200>;
diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi
index 0dc957e989fb..8623937e9506 100644
--- a/arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi
@@ -97,6 +97,146 @@ phy_gmii_sel: phy@4040 {
};
};
+ mcu_timer0: timer@40400000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x40400000 0x00 0x400>;
+ interrupts = <GIC_SPI 816 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 35 2>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 35 2>;
+ assigned-clock-parents = <&k3_clks 35 3>;
+ power-domains = <&k3_pds 35 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ /* Non-MPU Firmware usage */
+ status = "reserved";
+ };
+
+ mcu_timer1: timer@40410000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x40410000 0x00 0x400>;
+ interrupts = <GIC_SPI 817 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 117 2>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 117 2>;
+ assigned-clock-parents = <&k3_clks 117 3>;
+ power-domains = <&k3_pds 117 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ /* Non-MPU Firmware usage */
+ status = "reserved";
+ };
+
+ mcu_timer2: timer@40420000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x40420000 0x00 0x400>;
+ interrupts = <GIC_SPI 818 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 118 2>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 118 2>;
+ assigned-clock-parents = <&k3_clks 118 3>;
+ power-domains = <&k3_pds 118 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ /* Non-MPU Firmware usage */
+ status = "reserved";
+ };
+
+ mcu_timer3: timer@40430000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x40430000 0x00 0x400>;
+ interrupts = <GIC_SPI 819 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 119 2>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 119 2>;
+ assigned-clock-parents = <&k3_clks 119 3>;
+ power-domains = <&k3_pds 119 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ /* Non-MPU Firmware usage */
+ status = "reserved";
+ };
+
+ mcu_timer4: timer@40440000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x40440000 0x00 0x400>;
+ interrupts = <GIC_SPI 820 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 120 2>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 120 2>;
+ assigned-clock-parents = <&k3_clks 120 3>;
+ power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ /* Non-MPU Firmware usage */
+ status = "reserved";
+ };
+
+ mcu_timer5: timer@40450000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x40450000 0x00 0x400>;
+ interrupts = <GIC_SPI 821 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 121 2>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 121 2>;
+ assigned-clock-parents = <&k3_clks 121 3>;
+ power-domains = <&k3_pds 121 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ /* Non-MPU Firmware usage */
+ status = "reserved";
+ };
+
+ mcu_timer6: timer@40460000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x40460000 0x00 0x400>;
+ interrupts = <GIC_SPI 822 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 122 2>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 122 2>;
+ assigned-clock-parents = <&k3_clks 122 3>;
+ power-domains = <&k3_pds 122 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ /* Non-MPU Firmware usage */
+ status = "reserved";
+ };
+
+ mcu_timer7: timer@40470000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x40470000 0x00 0x400>;
+ interrupts = <GIC_SPI 823 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 123 2>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 123 2>;
+ assigned-clock-parents = <&k3_clks 123 3>;
+ power-domains = <&k3_pds 123 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ /* Non-MPU Firmware usage */
+ status = "reserved";
+ };
+
+ mcu_timer8: timer@40480000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x40480000 0x00 0x400>;
+ interrupts = <GIC_SPI 824 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 124 2>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 124 2>;
+ assigned-clock-parents = <&k3_clks 124 3>;
+ power-domains = <&k3_pds 124 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ /* Non-MPU Firmware usage */
+ status = "reserved";
+ };
+
+ mcu_timer9: timer@40490000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x40490000 0x00 0x400>;
+ interrupts = <GIC_SPI 825 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 125 2>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 125 2>;
+ assigned-clock-parents = <&k3_clks 125 3>;
+ power-domains = <&k3_pds 125 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ /* Non-MPU Firmware usage */
+ status = "reserved";
+ };
+
wkup_uart0: serial@42300000 {
compatible = "ti,j721e-uart", "ti,am654-uart";
reg = <0x00 0x42300000 0x00 0x200>;
--
2.40.0
^ permalink raw reply related [flat|nested] 14+ messages in thread* Re: [PATCH 5/6] arm64: dts: ti: k3-j784s4: Add general purpose timers
2023-05-31 21:32 ` [PATCH 5/6] arm64: dts: ti: k3-j784s4: Add general purpose timers Nishanth Menon
@ 2023-06-02 7:10 ` Tony Lindgren
0 siblings, 0 replies; 14+ messages in thread
From: Tony Lindgren @ 2023-06-02 7:10 UTC (permalink / raw)
To: Nishanth Menon
Cc: Conor Dooley, Krzysztof Kozlowski, Rob Herring, linux-kernel,
devicetree, linux-arm-kernel, Tero Kristo, Vignesh Raghavendra,
Udit Kumar, Nitin Yadav, Neha Malcom Francis
* Nishanth Menon <nm@ti.com> [230531 21:32]:
> There are 20 general purpose timers on j784s4 that can be used for
> things like PWM using pwm-omap-dmtimer driver. There are also
> additional ten timers in the MCU domain which are meant for MCU
> firmware usage and hence marked reserved by default.
>
> Though the count is similar to J721e/J7200/j721s2, the device IDs
> and clocks used in j784s4 are different with the option of certain
> clocks having options of additional clock muxes. Since there is very
> minimal reuse, it is cleaner to integrate as part of SoC files itself.
> The defaults are configured for clocking the timers from system
> clock(HFOSC0).
Reviewed-by: Tony Lindgren <tony@atomide.com>
^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH 6/6] arm64: dts: ti: k3-j784s4: Configure pinctrl for timer IO
2023-05-31 21:32 [PATCH 0/6] arm64: dts: ti: k3-j7*: Add general purpose timers Nishanth Menon
` (4 preceding siblings ...)
2023-05-31 21:32 ` [PATCH 5/6] arm64: dts: ti: k3-j784s4: Add general purpose timers Nishanth Menon
@ 2023-05-31 21:32 ` Nishanth Menon
2023-06-02 7:10 ` Tony Lindgren
2023-06-15 13:19 ` [PATCH 0/6] arm64: dts: ti: k3-j7*: Add general purpose timers Vignesh Raghavendra
6 siblings, 1 reply; 14+ messages in thread
From: Nishanth Menon @ 2023-05-31 21:32 UTC (permalink / raw)
To: Conor Dooley, Krzysztof Kozlowski, Rob Herring
Cc: linux-kernel, devicetree, linux-arm-kernel, Tero Kristo,
Vignesh Raghavendra, Nishanth Menon, Udit Kumar, Nitin Yadav,
Neha Malcom Francis, Tony Lindgren
There are timer IO pads in the MCU domain, and in the MAIN domain.
These pads can be muxed for the related timers.
The details of the multiplexing can be found in the register
documentation and Technical Reference Manual[1].
These are similar to J721e/J7200, but have different mux capabilities.
[1] http://www.ti.com/lit/zip/spruj52
Signed-off-by: Nishanth Menon <nm@ti.com>
---
arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi | 18 +++++++++++++++
.../boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi | 22 +++++++++++++++++++
2 files changed, 40 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
index f2ddd79f748d..7784278755a8 100644
--- a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
@@ -72,6 +72,24 @@ main_pmx0: pinctrl@11c000 {
pinctrl-single,function-mask = <0xffffffff>;
};
+ /* TIMERIO pad input CTRLMMR_TIMER*_CTRL registers */
+ main_timerio_input: pinctrl@104200 {
+ compatible = "pinctrl-single";
+ reg = <0x00 0x104200 0x00 0x50>;
+ #pinctrl-cells = <1>;
+ pinctrl-single,register-width = <32>;
+ pinctrl-single,function-mask = <0x00000007>;
+ };
+
+ /* TIMERIO pad output CTCTRLMMR_TIMERIO*_CTRL registers */
+ main_timerio_output: pinctrl@104280 {
+ compatible = "pinctrl-single";
+ reg = <0x00 0x104280 0x00 0x20>;
+ #pinctrl-cells = <1>;
+ pinctrl-single,register-width = <32>;
+ pinctrl-single,function-mask = <0x0000001f>;
+ };
+
main_crypto: crypto@4e00000 {
compatible = "ti,j721e-sa2ul";
reg = <0x00 0x4e00000 0x00 0x1200>;
diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi
index 8623937e9506..4720d89ab4d7 100644
--- a/arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi
@@ -83,6 +83,28 @@ wkup_gpio_intr: interrupt-controller@42200000 {
ti,interrupt-ranges = <16 928 16>;
};
+ /* MCU_TIMERIO pad input CTRLMMR_MCU_TIMER*_CTRL registers */
+ mcu_timerio_input: pinctrl@40f04200 {
+ compatible = "pinctrl-single";
+ reg = <0x00 0x40f04200 0x00 0x28>;
+ #pinctrl-cells = <1>;
+ pinctrl-single,register-width = <32>;
+ pinctrl-single,function-mask = <0x0000000f>;
+ /* Non-MPU Firmware usage */
+ status = "reserved";
+ };
+
+ /* MCU_TIMERIO pad output CTRLMMR_MCU_TIMERIO*_CTRL registers */
+ mcu_timerio_output: pinctrl@40f04280 {
+ compatible = "pinctrl-single";
+ reg = <0x00 0x40f04280 0x00 0x28>;
+ #pinctrl-cells = <1>;
+ pinctrl-single,register-width = <32>;
+ pinctrl-single,function-mask = <0x0000000f>;
+ /* Non-MPU Firmware usage */
+ status = "reserved";
+ };
+
mcu_conf: syscon@40f00000 {
compatible = "ti,j721e-system-controller", "syscon", "simple-mfd";
reg = <0x00 0x40f00000 0x00 0x20000>;
--
2.40.0
^ permalink raw reply related [flat|nested] 14+ messages in thread* Re: [PATCH 6/6] arm64: dts: ti: k3-j784s4: Configure pinctrl for timer IO
2023-05-31 21:32 ` [PATCH 6/6] arm64: dts: ti: k3-j784s4: Configure pinctrl for timer IO Nishanth Menon
@ 2023-06-02 7:10 ` Tony Lindgren
0 siblings, 0 replies; 14+ messages in thread
From: Tony Lindgren @ 2023-06-02 7:10 UTC (permalink / raw)
To: Nishanth Menon
Cc: Conor Dooley, Krzysztof Kozlowski, Rob Herring, linux-kernel,
devicetree, linux-arm-kernel, Tero Kristo, Vignesh Raghavendra,
Udit Kumar, Nitin Yadav, Neha Malcom Francis
* Nishanth Menon <nm@ti.com> [230531 21:32]:
> There are timer IO pads in the MCU domain, and in the MAIN domain.
> These pads can be muxed for the related timers.
>
> The details of the multiplexing can be found in the register
> documentation and Technical Reference Manual[1].
>
> These are similar to J721e/J7200, but have different mux capabilities.
Reviewed-by: Tony Lindgren <tony@atomide.com>
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH 0/6] arm64: dts: ti: k3-j7*: Add general purpose timers
2023-05-31 21:32 [PATCH 0/6] arm64: dts: ti: k3-j7*: Add general purpose timers Nishanth Menon
` (5 preceding siblings ...)
2023-05-31 21:32 ` [PATCH 6/6] arm64: dts: ti: k3-j784s4: Configure pinctrl for timer IO Nishanth Menon
@ 2023-06-15 13:19 ` Vignesh Raghavendra
6 siblings, 0 replies; 14+ messages in thread
From: Vignesh Raghavendra @ 2023-06-15 13:19 UTC (permalink / raw)
To: Conor Dooley, Krzysztof Kozlowski, Rob Herring, Nishanth Menon
Cc: Vignesh Raghavendra, linux-kernel, devicetree, linux-arm-kernel,
Tero Kristo, Udit Kumar, Nitin Yadav, Neha Malcom Francis,
Tony Lindgren
Hi Nishanth Menon,
On Wed, 31 May 2023 16:32:09 -0500, Nishanth Menon wrote:
> Add pending general purpose timer support for various J7 family
>
> Full list of K3 SoCs:
> * AM625: already merged
> * AM62A7: https://lore.kernel.org/all/20230418012717.1230882-2-nm@ti.com/
> * AM64: https://lore.kernel.org/all/20230414073328.381336-2-nm@ti.com/
> * AM65: already merged
> * J7200: https://lore.kernel.org/all/20230426103219.1565266-1-u-kumar1@ti.com/ (needs a respin)
>
> [...]
I have applied the following to branch ti-k3-dts-next on [1].
Thank you!
[1/6] arm64: dts: ti: k3-j721e: Add general purpose timers
commit: 7f209dd1267ce2a4a5f6a9e4571858fa2d2e588c
[2/6] arm64: dts: ti: k3-j721e: Configure pinctrl for timer IO
commit: 72a44d1c473486582d1d6177404e2fa7adf531ac
[3/6] arm64: dts: ti: k3-j721s2: Add general purpose timers
commit: 835d04422f9d4c232c060150e696075cd34e081a
[4/6] arm64: dts: ti: k3-j721s2: Configure pinctrl for timer IO
commit: 1ecc75be7bc522941261b5eb0c315b09098a47f4
[5/6] arm64: dts: ti: k3-j784s4: Add general purpose timers
commit: 833377cf858b24d45e658454bcb683dd9076b576
[6/6] arm64: dts: ti: k3-j784s4: Configure pinctrl for timer IO
commit: 5a41bcff08f9c0705f4e6c576d168051a7b323be
All being well this means that it will be integrated into the linux-next
tree (usually sometime in the next 24 hours) and sent up the chain during
the next merge window (or sooner if it is a relevant bug fix), however if
problems are discovered then the patch may be dropped or reverted.
You may get further e-mails resulting from automated or manual testing
and review of the tree, please engage with people reporting problems and
send followup patches addressing any issues that are reported if needed.
If any updates are required or you are submitting further changes they
should be sent as incremental updates against current git, existing
patches will not be replaced.
Please add any relevant lists and maintainers to the CCs when replying
to this mail.
[1] https://git.kernel.org/pub/scm/linux/kernel/git/ti/linux.git
--
Vignesh
^ permalink raw reply [flat|nested] 14+ messages in thread