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From: Bjorn Andersson <andersson@kernel.org>
To: Komal Bajaj <quic_kbajaj@quicinc.com>
Cc: Andy Gross <agross@kernel.org>,
	Konrad Dybcio <konrad.dybcio@linaro.org>,
	Rob Herring <robh+dt@kernel.org>,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
	Srinivas Kandagatla <srinivas.kandagatla@linaro.org>,
	Conor Dooley <conor+dt@kernel.org>,
	linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org,
	devicetree@vger.kernel.org
Subject: Re: [PATCH v3 06/10] soc: qcom: Add LLCC support for multi channel DDR
Date: Tue, 13 Jun 2023 10:11:10 -0700	[thread overview]
Message-ID: <20230613171110.ud2ybjpoxnwwflce@ripper> (raw)
In-Reply-To: <20230512122134.24339-7-quic_kbajaj@quicinc.com>

On Fri, May 12, 2023 at 05:51:30PM +0530, Komal Bajaj wrote:
> Add LLCC support for multi channel DDR configuration
> based on a feature register.
> 
> Signed-off-by: Komal Bajaj <quic_kbajaj@quicinc.com>
> ---
>  drivers/soc/qcom/llcc-qcom.c | 32 +++++++++++++++++++++++++++++---
>  1 file changed, 29 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/soc/qcom/llcc-qcom.c b/drivers/soc/qcom/llcc-qcom.c
> index 6cf373da5df9..1da337e7a378 100644
> --- a/drivers/soc/qcom/llcc-qcom.c
> +++ b/drivers/soc/qcom/llcc-qcom.c
> @@ -12,6 +12,7 @@
>  #include <linux/kernel.h>
>  #include <linux/module.h>
>  #include <linux/mutex.h>
> +#include <linux/nvmem-consumer.h>
>  #include <linux/of.h>
>  #include <linux/of_device.h>
>  #include <linux/regmap.h>
> @@ -943,6 +944,19 @@ static int qcom_llcc_cfg_program(struct platform_device *pdev,
>  	return ret;
>  }
> 
> +static int qcom_llcc_get_cfg_index(struct platform_device *pdev, u8 *cfg_index)
> +{
> +	int ret = 0;

First use is an assignment, no need to initialize here.

> +
> +	ret = nvmem_cell_read_u8(&pdev->dev, "multi_chan_ddr", cfg_index);
> +	if (ret == -ENOENT) {
> +		*cfg_index = 0;

Does nvmem_cell_read_u8() cahnge cfg_index when it fails with -ENOENT?

> +		return 0;
> +	}
> +
> +	return ret;
> +}
> +
>  static int qcom_llcc_remove(struct platform_device *pdev)
>  {
>  	/* Set the global pointer to a error code to avoid referencing it */
> @@ -975,11 +989,13 @@ static int qcom_llcc_probe(struct platform_device *pdev)
>  	struct device *dev = &pdev->dev;
>  	int ret, i;
>  	struct platform_device *llcc_edac;
> -	const struct qcom_llcc_config *cfg;
> +	const struct qcom_llcc_config *cfg, *entry;
>  	const struct llcc_slice_config *llcc_cfg;
>  	u32 sz;
> +	u8 cfg_index;
>  	u32 version;
>  	struct regmap *regmap;
> +	u32 num_entries = 0;
> 
>  	drv_data = devm_kzalloc(dev, sizeof(*drv_data), GFP_KERNEL);
>  	if (!drv_data) {
> @@ -1040,8 +1056,18 @@ static int qcom_llcc_probe(struct platform_device *pdev)
> 
>  	drv_data->version = version;
> 
> -	llcc_cfg = cfg[0]->sct_data;
> -	sz = cfg[0]->size;
> +	ret = qcom_llcc_get_cfg_index(pdev, &cfg_index);
> +	if (ret)
> +		goto err;
> +
> +	for (entry = cfg; entry->sct_data; entry++, num_entries++);

This is not readable, move the increment of num_entries out of there.

> +	if (cfg_index >= num_entries || cfg_index < 0) {

How can cfg_index be negative?

Regards,
Bjorn

> +		ret = -EINVAL;
> +		goto err;
> +	}
> +
> +	llcc_cfg = cfg[cfg_index].sct_data;
> +	sz = cfg[cfg_index].size;
> 
>  	for (i = 0; i < sz; i++)
>  		if (llcc_cfg[i].slice_id > drv_data->max_slices)
> --
> 2.17.1
> 

  parent reply	other threads:[~2023-06-13 17:07 UTC|newest]

Thread overview: 31+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-05-12 12:21 [PATCH v3 00/10] soc: qcom: llcc: Add support for QDU1000/QRU1000 Komal Bajaj
2023-05-12 12:21 ` [PATCH v3 01/10] nvmem: qfprom: Add support for secure reading Komal Bajaj
2023-05-27 20:50   ` Bjorn Andersson
2023-06-01 11:30     ` Komal Bajaj
2023-05-12 12:21 ` [PATCH v3 02/10] dt-bindings: nvmem: qfprom: Add compatible for QDU1000/QRU1000 Komal Bajaj
2023-05-12 16:56   ` Krzysztof Kozlowski
2023-05-15  7:08     ` Komal Bajaj
2023-05-15  9:04       ` Krzysztof Kozlowski
2023-05-15  9:05   ` Krzysztof Kozlowski
2023-05-12 12:21 ` [PATCH v3 03/10] arm64: dts: qcom: qdu1000: Add properties to qfprom for multi channel DDR Komal Bajaj
2023-05-12 16:58   ` Krzysztof Kozlowski
2023-05-12 12:21 ` [PATCH v3 04/10] nvmem: qfprom: Add support for secure reading on QDU1000/QRU1000 Komal Bajaj
2023-05-12 17:01   ` Krzysztof Kozlowski
2023-05-12 17:31     ` Dmitry Baryshkov
2023-05-15  8:32       ` Komal Bajaj
2023-05-27 21:08         ` Bjorn Andersson
2023-05-12 12:21 ` [PATCH v3 05/10] soc: qcom: llcc: Refactor llcc driver to support multiple configuration Komal Bajaj
2023-05-12 12:21 ` [PATCH v3 06/10] soc: qcom: Add LLCC support for multi channel DDR Komal Bajaj
2023-05-12 19:39   ` kernel test robot
2023-05-12 19:39   ` kernel test robot
2023-06-13 17:11   ` Bjorn Andersson [this message]
2023-06-14  6:30     ` Komal Bajaj
2023-05-12 12:21 ` [PATCH v3 07/10] dt-bindings: arm: msm: Add LLCC compatible for QDU1000/QRU1000 Komal Bajaj
2023-05-13  9:29   ` Krzysztof Kozlowski
2023-05-15  8:38     ` Komal Bajaj
2023-05-12 12:21 ` [PATCH v3 08/10] Revert "arm64: dts: qcom: qdu1000: Add LLCC/system-cache-controller" Komal Bajaj
2023-05-13  9:30   ` Krzysztof Kozlowski
2023-05-12 12:21 ` [PATCH v3 09/10] arm64: dts: qcom: qdu1000: Add LLCC/system-cache-controller Komal Bajaj
2023-05-13  9:30   ` Krzysztof Kozlowski
2023-05-12 12:21 ` [PATCH v3 10/10] soc: qcom: llcc: Add QDU1000 and QRU1000 LLCC support Komal Bajaj
2023-05-12 16:56 ` [PATCH v3 00/10] soc: qcom: llcc: Add support for QDU1000/QRU1000 Krzysztof Kozlowski

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