From: Devi Priya <quic_devipriy@quicinc.com>
To: <agross@kernel.org>, <andersson@kernel.org>,
<konrad.dybcio@linaro.org>, <robh+dt@kernel.org>,
<krzysztof.kozlowski+dt@linaro.org>, <conor+dt@kernel.org>,
<linux-arm-msm@vger.kernel.org>, <devicetree@vger.kernel.org>,
<linux-kernel@vger.kernel.org>
Cc: <quic_srichara@quicinc.com>, <quic_sjaganat@quicinc.com>,
<quic_kathirav@quicinc.com>, <quic_anusha@quicinc.com>
Subject: [PATCH] arm64: dts: qcom: ipq9574: Use assigned-clock-rates for QUP I2C core clks
Date: Thu, 15 Jun 2023 14:18:41 +0530 [thread overview]
Message-ID: <20230615084841.12375-1-quic_devipriy@quicinc.com> (raw)
Use assigned-clock-rates property for configuring the QUP I2C core clocks
to operate at nominal frequency.
Signed-off-by: Devi Priya <quic_devipriy@quicinc.com>
---
arch/arm64/boot/dts/qcom/ipq9574.dtsi | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
index 0baeb10bbdae..78bf7f9c455a 100644
--- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
@@ -361,6 +361,8 @@
clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>,
<&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "core", "iface";
+ assigned-clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;
+ assigned-clock-rates = <50000000>;
dmas = <&blsp_dma 14>, <&blsp_dma 15>;
dma-names = "tx", "rx";
status = "disabled";
@@ -389,6 +391,8 @@
clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>,
<&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "core", "iface";
+ assigned-clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>;
+ assigned-clock-rates = <50000000>;
dmas = <&blsp_dma 16>, <&blsp_dma 17>;
dma-names = "tx", "rx";
status = "disabled";
@@ -417,6 +421,8 @@
clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>,
<&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "core", "iface";
+ assigned-clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>;
+ assigned-clock-rates = <50000000>;
dmas = <&blsp_dma 18>, <&blsp_dma 19>;
dma-names = "tx", "rx";
status = "disabled";
@@ -446,6 +452,8 @@
clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>,
<&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "core", "iface";
+ assigned-clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>;
+ assigned-clock-rates = <50000000>;
dmas = <&blsp_dma 20>, <&blsp_dma 21>;
dma-names = "tx", "rx";
status = "disabled";
--
2.17.1
next reply other threads:[~2023-06-15 8:50 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-06-15 8:48 Devi Priya [this message]
2023-06-15 8:51 ` [PATCH] arm64: dts: qcom: ipq9574: Use assigned-clock-rates for QUP I2C core clks Konrad Dybcio
2023-06-22 6:25 ` Devi Priya
2023-06-22 8:53 ` Konrad Dybcio
2023-07-22 5:17 ` Bjorn Andersson
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