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[94.181.180.60]) by smtp.gmail.com with ESMTPSA id h7-20020ac25967000000b004f13f4ec267sm244451lfp.186.2023.06.15.07.44.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 Jun 2023 07:44:51 -0700 (PDT) From: Aleksandr Shubin To: linux-kernel@vger.kernel.org Cc: Aleksandr Shubin , Thierry Reding , =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Paul Walmsley , Palmer Dabbelt , Albert Ou , Philipp Zabel , Cristian Ciocaltea , Maxime Ripard , linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-riscv@lists.infradead.org Subject: [PATCH v1 1/3] dt-bindings: pwm: Add binding for Allwinner D1/T113-S3/R329 PWM controller Date: Thu, 15 Jun 2023 17:43:56 +0300 Message-Id: <20230615144423.828698-2-privatesub2@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230615144423.828698-1-privatesub2@gmail.com> References: <20230615144423.828698-1-privatesub2@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Allwinner's D1, T113-S3 and R329 SoCs have a new pwm controller witch is different from the previous pwm-sun4i. D1 and T113s SoCs have one PWM controller with 8 channels. R329 SoC has two PWM controllers in both power domains, one of them has 9 channels (CPUX one) and the other has 6 (CPUS one). Add a device tree binding for them. Signed-off-by: Aleksandr Shubin --- .../bindings/pwm/allwinner,sun20i-pwm.yaml | 70 +++++++++++++++++++ 1 file changed, 70 insertions(+) create mode 100644 Documentation/devicetree/bindings/pwm/allwinner,sun20i-pwm.yaml diff --git a/Documentation/devicetree/bindings/pwm/allwinner,sun20i-pwm.yaml b/Documentation/devicetree/bindings/pwm/allwinner,sun20i-pwm.yaml new file mode 100644 index 000000000000..e5f9cb2d5c4f --- /dev/null +++ b/Documentation/devicetree/bindings/pwm/allwinner,sun20i-pwm.yaml @@ -0,0 +1,70 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pwm/allwinner,sun20i-pwm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Allwinner D1, T113-S3 and R329 PWM + +maintainers: + - Chen-Yu Tsai + - Maxime Ripard + +allOf: + - $ref: pwm.yaml# + +properties: + compatible: + const: allwinner,sun20i-d1-pwm + + reg: + maxItems: 1 + + "#pwm-cells": + const: 3 + + clocks: + items: + - description: 24 MHz oscillator + - description: Bus Clock + + clock-names: + items: + - const: hosc + - const: bus + + resets: + items: + - description: module reset + + allwinner,pwm-channels: + $ref: /schemas/types.yaml#/definitions/uint32 + description: The number of PWM channels configured for this instance + +required: + - compatible + - reg + - "#pwm-cells" + - clocks + - clock-names + - resets + - allwinner,pwm-channels + +additionalProperties: false + +examples: + - | + #include + #include + + pwm: pwm@2000c00 { + compatible = "allwinner,sun20i-d1-pwm"; + reg = <0x02000c00 0x400>; + clocks = <&dcxo>, <&ccu CLK_BUS_PWM>; + clock-names = "hosc", "bus"; + resets = <&ccu RST_BUS_PWM>; + allwinner,pwm-channels = <8>; + #pwm-cells = <0x3>; + }; + +... -- 2.25.1