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[59.124.168.89]) by smtp.gmail.com with ESMTPSA id u11-20020a17090a410b00b0025023726fc4sm617596pjf.26.2023.06.15.23.33.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 Jun 2023 23:33:20 -0700 (PDT) From: Eric Lin To: conor@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, palmer@dabbelt.com, paul.walmsley@sifive.com, aou@eecs.berkeley.edu, maz@kernel.org, chenhuacai@kernel.org, baolu.lu@linux.intel.com, will@kernel.org, kan.liang@linux.intel.com, nnac123@linux.ibm.com, pierre.gondois@arm.com, huangguangbin2@huawei.com, jgross@suse.com, chao.gao@intel.com, maobibo@loongson.cn, linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dslin1010@gmail.com Cc: Eric Lin , Zong Li , Nick Hu Subject: [PATCH 3/3] dt-bindings: riscv: sifive: Add SiFive Private L2 cache controller Date: Fri, 16 Jun 2023 14:32:10 +0800 Message-Id: <20230616063210.19063-4-eric.lin@sifive.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230616063210.19063-1-eric.lin@sifive.com> References: <20230616063210.19063-1-eric.lin@sifive.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This add YAML DT binding documentation for SiFive Private L2 cache controller Signed-off-by: Eric Lin Reviewed-by: Zong Li Reviewed-by: Nick Hu --- .../bindings/riscv/sifive,pL2Cache0.yaml | 81 +++++++++++++++++++ 1 file changed, 81 insertions(+) create mode 100644 Documentation/devicetree/bindings/riscv/sifive,pL2Cache0.yaml diff --git a/Documentation/devicetree/bindings/riscv/sifive,pL2Cache0.yaml b/Documentation/devicetree/bindings/riscv/sifive,pL2Cache0.yaml new file mode 100644 index 000000000000..b5d8d4a39dde --- /dev/null +++ b/Documentation/devicetree/bindings/riscv/sifive,pL2Cache0.yaml @@ -0,0 +1,81 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +# Copyright (C) 2023 SiFive, Inc. +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/riscv/sifive,pL2Cache0.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: SiFive Private L2 Cache Controller + +maintainers: + - Greentime Hu + - Eric Lin + +description: + The SiFive Private L2 Cache Controller is per hart and communicates with both the upstream + L1 caches and downstream L3 cache or memory, enabling a high-performance cache subsystem. + All the properties in ePAPR/DeviceTree specification applies for this platform. + +allOf: + - $ref: /schemas/cache-controller.yaml# + +select: + properties: + compatible: + contains: + enum: + - sifive,pL2Cache0 + - sifive,pL2Cache1 + + required: + - compatible + +properties: + compatible: + items: + - enum: + - sifive,pL2Cache0 + - sifive,pL2Cache1 + + cache-block-size: + const: 64 + + cache-level: + const: 2 + + cache-sets: + const: 512 + + cache-size: + const: 262144 + + cache-unified: true + + reg: + maxItems: 1 + + next-level-cache: true + +additionalProperties: false + +required: + - compatible + - cache-block-size + - cache-level + - cache-sets + - cache-size + - cache-unified + - reg + +examples: + - | + pl2@10104000 { + compatible = "sifive,pL2Cache0"; + cache-block-size = <64>; + cache-level = <2>; + cache-sets = <512>; + cache-size = <262144>; + cache-unified; + reg = <0x10104000 0x4000>; + next-level-cache = <&L4>; + }; -- 2.40.1