[PATCH v2 0/2] mtd: spi-nor: Avoid setting SRWD bit in SR

[PATCH v2 0/2] mtd: spi-nor: Avoid setting SRWD bit in SR

[Amit Kumar Mahapatra]

Setting the status register write disable (SRWD) bit in the status
register (SR) with WP signal of the flash not connected will configure the
SR permanently as read-only. To avoid this a boolean type DT property
"broken-wp" is introduced. If this property is defined, the spi-nor doesn't
set the SRWD bit in SR while performing flash protection operation.
---
BRANCH: for-next

Changes in v2:
- Modified DT property description to add information about a
  valid use case.
- Added Reviewed-by tag in 1/2.
- Updated comment description in 2/2.    
---
Amit Kumar Mahapatra (2):
  dt-bindings: mtd: jedec, spi-nor: Add DT property to avoid setting
    SRWD bit in status register
  mtd: spi-nor: Avoid setting SRWD bit in SR if WP signal not connected

 .../devicetree/bindings/mtd/jedec,spi-nor.yaml    | 15 +++++++++++++++
 drivers/mtd/spi-nor/core.c                        |  3 +++
 drivers/mtd/spi-nor/core.h                        |  1 +
 drivers/mtd/spi-nor/swp.c                         |  9 +++++++--
 4 files changed, 26 insertions(+), 2 deletions(-)

-- 
2.17.1

[PATCH v2 1/2] dt-bindings: mtd: jedec, spi-nor: Add DT property to avoid setting SRWD bit in status register

[Amit Kumar Mahapatra]

If the WP signal of the flash device is not connected and the software sets
the status register write disable (SRWD) bit in the status register then
thestatus register permanently becomes read-only. To avoid this added a new
boolean DT property "broken-wp". If WP signal is not connected, then this
property should be set in the DT to avoid setting the SRWD during status
register write operation.

Signed-off-by: Amit Kumar Mahapatra <amit.kumar-mahapatra@amd.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
---
 .../devicetree/bindings/mtd/jedec,spi-nor.yaml    | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

diff --git a/Documentation/devicetree/bindings/mtd/jedec,spi-nor.yaml b/Documentation/devicetree/bindings/mtd/jedec,spi-nor.yaml
index 89959e5c47ba..10a6df752f6f 100644
--- a/Documentation/devicetree/bindings/mtd/jedec,spi-nor.yaml
+++ b/Documentation/devicetree/bindings/mtd/jedec,spi-nor.yaml
@@ -70,6 +70,21 @@ properties:
       be used on such systems, to denote the absence of a reliable reset
       mechanism.
 
+  broken-wp:
+    type: boolean
+    description:
+      The status register write disable (SRWD) bit in status register, combined
+      with the WP signal, provides hardware data protection for the device. When
+      the SRWD bit is set to 1, and the WP signal is either driven LOW or hard
+      strapped to LOW, the status register nonvolatile bits become read-only and
+      the WRITE STATUS REGISTER operation will not execute. The only way to exit
+      this hardware-protected mode is to drive WP HIGH. If the WP signal of the
+      flash device is not connected then status register permanently becomes
+      read-only as the SRWD bit cannot be reset. This boolean flag can be used
+      on systems in which WP signal is not connected, to avoid setting the SRWD
+      bit while writing the status register. If the WP signal is hard strapped
+      to LOW then it is not broken as it can be a valid use case.
+
   reset-gpios:
     description:
       A GPIO line connected to the RESET (active low) signal of the device.
-- 
2.17.1

[PATCH v2 2/2] mtd: spi-nor: Avoid setting SRWD bit in SR if WP signal not connected

[Amit Kumar Mahapatra]

Setting the status register write disable (SRWD) bit in the status
register (SR) with WP signal of the flash not connected will configure the
SR permanently as read-only. If WP signal is not connected, avoid setting
SRWD bit while writing the SR during flash protection.

Signed-off-by: Amit Kumar Mahapatra <amit.kumar-mahapatra@amd.com>
---
 drivers/mtd/spi-nor/core.c | 3 +++
 drivers/mtd/spi-nor/core.h | 1 +
 drivers/mtd/spi-nor/swp.c  | 9 +++++++--
 3 files changed, 11 insertions(+), 2 deletions(-)

diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c
index 0bb0ad14a2fc..81b57c51f41c 100644
--- a/drivers/mtd/spi-nor/core.c
+++ b/drivers/mtd/spi-nor/core.c
@@ -2864,6 +2864,9 @@ static void spi_nor_init_flags(struct spi_nor *nor)
 	if (flags & NO_CHIP_ERASE)
 		nor->flags |= SNOR_F_NO_OP_CHIP_ERASE;
 
+	if (of_property_read_bool(np, "broken-wp"))
+		nor->flags |= SNOR_F_BROKEN_WP;
+
 	if (flags & SPI_NOR_RWW && nor->info->n_banks > 1 &&
 	    !nor->controller_ops)
 		nor->flags |= SNOR_F_RWW;
diff --git a/drivers/mtd/spi-nor/core.h b/drivers/mtd/spi-nor/core.h
index 4fb5ff09c63a..6ac932eba913 100644
--- a/drivers/mtd/spi-nor/core.h
+++ b/drivers/mtd/spi-nor/core.h
@@ -132,6 +132,7 @@ enum spi_nor_option_flags {
 	SNOR_F_SWP_IS_VOLATILE	= BIT(13),
 	SNOR_F_RWW		= BIT(14),
 	SNOR_F_ECC		= BIT(15),
+	SNOR_F_BROKEN_WP	= BIT(16),
 };
 
 struct spi_nor_read_command {
diff --git a/drivers/mtd/spi-nor/swp.c b/drivers/mtd/spi-nor/swp.c
index 0ba716e84377..5d91f152c2cc 100644
--- a/drivers/mtd/spi-nor/swp.c
+++ b/drivers/mtd/spi-nor/swp.c
@@ -214,8 +214,13 @@ static int spi_nor_sr_lock(struct spi_nor *nor, loff_t ofs, uint64_t len)
 
 	status_new = (status_old & ~mask & ~tb_mask) | val;
 
-	/* Disallow further writes if WP pin is asserted */
-	status_new |= SR_SRWD;
+	/*
+	 * Disallow further writes if WP pin is not broken. WP pin is
+	 * considered broken only if the WP signal of the flash device
+	 * is not connected.
+	 */
+	if (!(nor->flags & SNOR_F_BROKEN_WP))
+		status_new |= SR_SRWD;
 
 	if (!use_top)
 		status_new |= tb_mask;
-- 
2.17.1

Re: [PATCH v2 1/2] dt-bindings: mtd: jedec, spi-nor: Add DT property to avoid setting SRWD bit in status register

[Michael Walle]

Am 2023-06-16 10:55, schrieb Amit Kumar Mahapatra:
> If the WP signal of the flash device is not connected and the software 
> sets
> the status register write disable (SRWD) bit in the status register 
> then
> thestatus register permanently becomes read-only. To avoid this added a 
> new
> boolean DT property "broken-wp". If WP signal is not connected, then 
> this
> property should be set in the DT to avoid setting the SRWD during 
> status
> register write operation.
> 
> Signed-off-by: Amit Kumar Mahapatra <amit.kumar-mahapatra@amd.com>
> Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
> ---
>  .../devicetree/bindings/mtd/jedec,spi-nor.yaml    | 15 +++++++++++++++
>  1 file changed, 15 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/mtd/jedec,spi-nor.yaml
> b/Documentation/devicetree/bindings/mtd/jedec,spi-nor.yaml
> index 89959e5c47ba..10a6df752f6f 100644
> --- a/Documentation/devicetree/bindings/mtd/jedec,spi-nor.yaml
> +++ b/Documentation/devicetree/bindings/mtd/jedec,spi-nor.yaml
> @@ -70,6 +70,21 @@ properties:
>        be used on such systems, to denote the absence of a reliable 
> reset
>        mechanism.
> 
> +  broken-wp:
> +    type: boolean
> +    description:
> +      The status register write disable (SRWD) bit in status register, 
> combined
> +      with the WP signal, provides hardware data protection for the
> device. When
> +      the SRWD bit is set to 1, and the WP signal is either driven LOW 
> or hard
> +      strapped to LOW, the status register nonvolatile bits become
> read-only and
> +      the WRITE STATUS REGISTER operation will not execute. The only
> way to exit
> +      this hardware-protected mode is to drive WP HIGH. If the WP 
> signal of the
> +      flash device is not connected then status register permanently 
> becomes
> +      read-only as the SRWD bit cannot be reset. This boolean flag can 
> be used
> +      on systems in which WP signal is not connected, to avoid setting 
> the SRWD
> +      bit while writing the status register.

This is not true for all flashes, for example, Macronix flashes seem to 
have
an internal pull-up, so if the pin is unconnected H/W write protection 
is
disabled.

So maybe only mention that "if the pin is wrongly tied to GND (that 
includes
internal pull-downs) or it is left floating".

Same goes for your comment in the driver code. Sorry for nitpicking, but
I fear some misuse of this property to disable the locking of the status
register.

> If the WP signal is hard strapped
> +      to LOW then it is not broken as it can be a valid use case.
> +

I'm not sure it the bindings use negative notion of pins, because that
signal is usually called WP#.

-michael

Re: [PATCH v2 1/2] dt-bindings: mtd: jedec, spi-nor: Add DT property to avoid setting SRWD bit in status register

[Rob Herring]

On Fri, Jun 16, 2023 at 02:25:12PM +0530, Amit Kumar Mahapatra wrote:
> If the WP signal of the flash device is not connected and the software sets
> the status register write disable (SRWD) bit in the status register then
> thestatus register permanently becomes read-only. To avoid this added a new
> boolean DT property "broken-wp". If WP signal is not connected, then this
> property should be set in the DT to avoid setting the SRWD during status
> register write operation.
> 
> Signed-off-by: Amit Kumar Mahapatra <amit.kumar-mahapatra@amd.com>
> Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
> ---
>  .../devicetree/bindings/mtd/jedec,spi-nor.yaml    | 15 +++++++++++++++
>  1 file changed, 15 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/mtd/jedec,spi-nor.yaml b/Documentation/devicetree/bindings/mtd/jedec,spi-nor.yaml
> index 89959e5c47ba..10a6df752f6f 100644
> --- a/Documentation/devicetree/bindings/mtd/jedec,spi-nor.yaml
> +++ b/Documentation/devicetree/bindings/mtd/jedec,spi-nor.yaml
> @@ -70,6 +70,21 @@ properties:
>        be used on such systems, to denote the absence of a reliable reset
>        mechanism.
>  
> +  broken-wp:

In the tied low case, that's designed behavior rather than broken. The 
name should reflect that.

> +    type: boolean
> +    description:
> +      The status register write disable (SRWD) bit in status register, combined
> +      with the WP signal, provides hardware data protection for the device. When
> +      the SRWD bit is set to 1, and the WP signal is either driven LOW or hard
> +      strapped to LOW, the status register nonvolatile bits become read-only and
> +      the WRITE STATUS REGISTER operation will not execute. The only way to exit
> +      this hardware-protected mode is to drive WP HIGH. If the WP signal of the
> +      flash device is not connected then status register permanently becomes
> +      read-only as the SRWD bit cannot be reset. This boolean flag can be used
> +      on systems in which WP signal is not connected, to avoid setting the SRWD
> +      bit while writing the status register. If the WP signal is hard strapped
> +      to LOW then it is not broken as it can be a valid use case.
> +
>    reset-gpios:
>      description:
>        A GPIO line connected to the RESET (active low) signal of the device.
> -- 
> 2.17.1
> 

RE: [PATCH v2 1/2] dt-bindings: mtd: jedec, spi-nor: Add DT property to avoid setting SRWD bit in status register

[Mahapatra, Amit Kumar]

Hello Rob,

> -----Original Message-----
> From: Rob Herring <robh@kernel.org>
> Sent: Friday, June 16, 2023 8:56 PM
> To: Mahapatra, Amit Kumar <amit.kumar-mahapatra@amd.com>
> Cc: tudor.ambarus@linaro.org; pratyush@kernel.org;
> miquel.raynal@bootlin.com; richard@nod.at; vigneshr@ti.com;
> krzysztof.kozlowski+dt@linaro.org; conor+dt@kernel.org; git (AMD-Xilinx)
> <git@amd.com>; michael@walle.cc; linux-mtd@lists.infradead.org;
> devicetree@vger.kernel.org; linux-kernel@vger.kernel.org;
> amitrkcian2002@gmail.com
> Subject: Re: [PATCH v2 1/2] dt-bindings: mtd: jedec, spi-nor: Add DT property
> to avoid setting SRWD bit in status register
> 
> On Fri, Jun 16, 2023 at 02:25:12PM +0530, Amit Kumar Mahapatra wrote:
> > If the WP signal of the flash device is not connected and the software
> > sets the status register write disable (SRWD) bit in the status
> > register then thestatus register permanently becomes read-only. To
> > avoid this added a new boolean DT property "broken-wp". If WP signal
> > is not connected, then this property should be set in the DT to avoid
> > setting the SRWD during status register write operation.
> >
> > Signed-off-by: Amit Kumar Mahapatra <amit.kumar-mahapatra@amd.com>
> > Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
> > ---
> >  .../devicetree/bindings/mtd/jedec,spi-nor.yaml    | 15 +++++++++++++++
> >  1 file changed, 15 insertions(+)
> >
> > diff --git a/Documentation/devicetree/bindings/mtd/jedec,spi-nor.yaml
> > b/Documentation/devicetree/bindings/mtd/jedec,spi-nor.yaml
> > index 89959e5c47ba..10a6df752f6f 100644
> > --- a/Documentation/devicetree/bindings/mtd/jedec,spi-nor.yaml
> > +++ b/Documentation/devicetree/bindings/mtd/jedec,spi-nor.yaml
> > @@ -70,6 +70,21 @@ properties:
> >        be used on such systems, to denote the absence of a reliable reset
> >        mechanism.
> >
> > +  broken-wp:
> 
> In the tied low case, that's designed behavior rather than broken. The name
> should reflect that.

In that case will it be ok to change it to "no-wp". Please let me know if
you have any other suitable name.

Regards,
Amit
> 
> > +    type: boolean
> > +    description:
> > +      The status register write disable (SRWD) bit in status register, combined
> > +      with the WP signal, provides hardware data protection for the device.
> When
> > +      the SRWD bit is set to 1, and the WP signal is either driven LOW or hard
> > +      strapped to LOW, the status register nonvolatile bits become read-only
> and
> > +      the WRITE STATUS REGISTER operation will not execute. The only way
> to exit
> > +      this hardware-protected mode is to drive WP HIGH. If the WP signal of
> the
> > +      flash device is not connected then status register permanently becomes
> > +      read-only as the SRWD bit cannot be reset. This boolean flag can be
> used
> > +      on systems in which WP signal is not connected, to avoid setting the
> SRWD
> > +      bit while writing the status register. If the WP signal is hard strapped
> > +      to LOW then it is not broken as it can be a valid use case.
> > +
> >    reset-gpios:
> >      description:
> >        A GPIO line connected to the RESET (active low) signal of the device.
> > --
> > 2.17.1
> >