From: niravkumar.l.rabara@intel.com
To: krzysztof.kozlowski@linaro.org
Cc: adrian.ho.yin.ng@intel.com, andrew@lunn.ch, conor+dt@kernel.org,
devicetree@vger.kernel.org, dinguyen@kernel.org,
krzysztof.kozlowski+dt@linaro.org, linux-clk@vger.kernel.org,
linux-kernel@vger.kernel.org, mturquette@baylibre.com,
netdev@vger.kernel.org, niravkumar.l.rabara@intel.com,
p.zabel@pengutronix.de, richardcochran@gmail.com,
robh+dt@kernel.org, sboyd@kernel.org, wen.ping.teh@intel.com
Subject: Re: [PATCH 1/4] dt-bindings: intel: Add Intel Agilex5 compatible
Date: Tue, 20 Jun 2023 22:12:12 +0800 [thread overview]
Message-ID: <20230620141212.2469148-1-niravkumar.l.rabara@intel.com> (raw)
In-Reply-To: <254978f3-3bf3-7cf5-e2b7-69d413acf092@linaro.org>
>> diff --git a/Documentation/devicetree/bindings/arm/intel,socfpga.yaml
>> b/Documentation/devicetree/bindings/arm/intel,socfpga.yaml
>> index 4b4dcf551eb6..28849c720314 100644
>> --- a/Documentation/devicetree/bindings/arm/intel,socfpga.yaml
>> +++ b/Documentation/devicetree/bindings/arm/intel,socfpga.yaml
>> @@ -20,6 +20,7 @@ properties:
>> - intel,n5x-socdk
>> - intel,socfpga-agilex-n6000
>> - intel,socfpga-agilex-socdk
>> + - intel,socfpga-agilex5-socdk
>> - const: intel,socfpga-agilex
>
>This is agilex5, not agilex. Why are you using the same SoC compatible?
>You have entire commit msg to explain your hardware and avoid such questions...
Yes, better to use different SoC compatible for Agilex5,
will add new description and item for Agilex5 board in v2 patch.
next prev parent reply other threads:[~2023-06-20 14:13 UTC|newest]
Thread overview: 39+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-06-18 13:22 [PATCH 0/4] Add support for Agilex5 SoCFPGA platform niravkumar.l.rabara
2023-06-18 13:22 ` [PATCH 1/4] dt-bindings: intel: Add Intel Agilex5 compatible niravkumar.l.rabara
2023-06-18 18:47 ` Krzysztof Kozlowski
2023-06-20 14:12 ` niravkumar.l.rabara [this message]
2023-06-18 13:22 ` [PATCH 2/4] dt-bindings: clock: Add Intel Agilex5 clocks and resets niravkumar.l.rabara
2023-06-18 18:49 ` Krzysztof Kozlowski
2023-06-20 10:39 ` wen.ping.teh
2023-06-20 11:06 ` Krzysztof Kozlowski
2023-06-21 10:45 ` wen.ping.teh
2023-06-19 2:15 ` Rob Herring
2023-06-18 13:22 ` [PATCH 3/4] clk: socfpga: agilex5: Add clock driver for Agilex5 platform niravkumar.l.rabara
2023-06-20 14:42 ` Dinh Nguyen
2023-06-18 13:22 ` [PATCH 4/4] arm64: dts: agilex5: Add initial support for Intel's Agilex5 SoCFPGA niravkumar.l.rabara
2023-06-18 18:56 ` Krzysztof Kozlowski
2023-06-20 14:07 ` niravkumar.l.rabara
2023-08-01 1:02 ` [PATCH v2 0/5] Add support for Agilex5 SoCFPGA platform niravkumar.l.rabara
2023-08-01 1:02 ` [PATCH v2 1/5] dt-bindings: intel: Add Intel Agilex5 compatible niravkumar.l.rabara
2023-08-01 20:53 ` Conor Dooley
2023-08-01 1:02 ` [PATCH v2 2/5] dt-bindings: reset: add reset IDs for Agilex5 niravkumar.l.rabara
2023-08-01 20:55 ` Conor Dooley
2023-08-01 1:02 ` [PATCH v2 3/5] dt-bindings: clock: add Intel Agilex5 clock manager niravkumar.l.rabara
2023-08-01 20:57 ` Conor Dooley
2023-08-02 3:06 ` Rabara, Niravkumar L
2023-08-02 6:58 ` Conor Dooley
2023-08-02 2:58 ` [PATCH v3 " niravkumar.l.rabara
2023-08-02 7:02 ` Conor Dooley
2023-08-02 7:14 ` Rabara, Niravkumar L
2023-08-06 17:53 ` Dinh Nguyen
2023-08-06 19:35 ` [PATCH v2 " Krzysztof Kozlowski
2023-08-07 3:56 ` Rabara, Niravkumar L
2023-08-01 1:02 ` [PATCH v2 4/5] clk: socfpga: agilex: add clock driver for the Agilex5 niravkumar.l.rabara
2023-08-08 11:03 ` Dinh Nguyen
2023-08-09 21:28 ` Stephen Boyd
2023-08-10 10:56 ` Dinh Nguyen
2023-08-09 21:26 ` Stephen Boyd
2023-08-13 12:53 ` Rabara, Niravkumar L
2023-08-14 2:48 ` Dinh Nguyen
2023-08-14 2:59 ` Rabara, Niravkumar L
2023-08-01 1:02 ` [PATCH v2 5/5] arm64: dts: agilex5: add initial support for Intel Agilex5 SoCFPGA niravkumar.l.rabara
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