[PATCH v2 00/26] ARM: qcom: apq8064: support CPU frequency scaling

[PATCH v2 00/26] ARM: qcom: apq8064: support CPU frequency scaling

[Dmitry Baryshkov]

Implement CPUFreq support for one of the oldest supported Qualcomm
platforms, APQ8064. Each core has independent power and frequency
control. Additionally the L2 cache is scaled to follow the CPU
frequencies (failure to do so results in strange semi-random crashes).

Core voltage is controlled through the SAW2 devices, one for each core.
The L2 has two regulators, vdd-mem and vdd-dig.

Changes since v1:
- Added separate Krait L2 cache device driver
- Moved vdd-mem and vdd-dig scaling to the L2 cache device (Christian,
  Stephen Gerhold)
- Fixed the 'INTERCONNECT' in the guarding define for krait-cc bindings
  (Stephen Boyd)
- Made SAW2's regulator property -> node handling clear (Krzysztof)
- Dropped the 'regulator' property from all SAW2 devices.

Dmitry Baryshkov (26):
  dt-bindings: opp: opp-v2-kryo-cpu: support Qualcomm Krait SoCs
  dt-bindings: soc: qcom: merge qcom,saw2.txt into qcom,spm.yaml
  dt-bindings: soc: qcom: qcom,saw2: define optional regulator node
  dt-bindings: clock: qcom,krait-cc: Krait core clock controller
  dt-bindings: cache: describe L2 cache on Qualcomm Krait platforms
  interconnect: icc-clk: add support for scaling using OPP
  clk: qcom: krait-cc: rewrite driver to use clk_hw instead of clk
  soc: qcom: spm: add support for voltage regulator
  cpufreq: qcom-nvmem: create L2 cache device
  cpufreq: qcom-nvmem: also accept operating-points-v2-krait-cpu
  cpufreq: qcom-nvmem: drop pvs_ver for format a fuses
  cpufreq: qcom-nvmem: provide separate configuration data for apq8064
  soc: qcom: Add driver for Qualcomm Krait L2 cache scaling
  ARM: dts: qcom: apq8064: rename SAW nodes to power-manager
  ARM: dts: qcom: apq8064: declare SAW2 regulators
  ARM: dts: qcom: apq8064: add L2 cache scaling
  ARM: dts: qcom: apq8064: add simple CPUFreq support
  ARM: dts: qcom: apq8064: provide voltage scaling tables
  ARM: dts: qcom: apq8064: enable passive CPU cooling
  ARM: dts: qcom: apq8064-asus-nexus7-flo: constraint cpufreq regulators
  ARM: dts: qcom: apq8064-ifc6410: constraint cpufreq regulators
  ARM: dts: qcom: msm8960: declare SAW2 regulators
  ARM: dts: qcom: apq8084: drop 'regulator' property from SAW2 device
  ARM: dts: qcom: msm8974: drop 'regulator' property from SAW2 device
  ARM: dts: qcom: ipq4019: drop 'regulator' property from SAW2 devices
  ARM: dts: qcom: ipq8064: drop 'regulator' property from SAW2 devices

 .../devicetree/bindings/arm/msm/qcom,saw2.txt |  58 --
 .../bindings/cache/qcom,krait-l2-cache.yaml   |  75 ++
 .../bindings/opp/opp-v2-kryo-cpu.yaml         |  12 +-
 .../qcom/{qcom,spm.yaml => qcom,saw2.yaml}    |  39 +-
 .../dts/qcom/qcom-apq8064-asus-nexus7-flo.dts |  14 +-
 .../boot/dts/qcom/qcom-apq8064-ifc6410.dts    |  18 +-
 arch/arm/boot/dts/qcom/qcom-apq8064.dtsi      | 671 +++++++++++++++++-
 arch/arm/boot/dts/qcom/qcom-apq8084.dtsi      |   1 -
 arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi      |   5 -
 arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi      |   2 -
 arch/arm/boot/dts/qcom/qcom-msm8960.dtsi      |  12 +-
 arch/arm/boot/dts/qcom/qcom-msm8974.dtsi      |   1 -
 drivers/clk/qcom/krait-cc.c                   | 141 ++--
 drivers/cpufreq/qcom-cpufreq-nvmem.c          |  76 +-
 drivers/interconnect/icc-clk.c                |  13 +-
 drivers/soc/qcom/Kconfig                      |   9 +
 drivers/soc/qcom/Makefile                     |   1 +
 drivers/soc/qcom/krait-l2-cache.c             | 190 +++++
 drivers/soc/qcom/spm.c                        | 205 +++++-
 include/dt-bindings/clock/qcom,krait-cc.h     |  17 +
 include/dt-bindings/soc/qcom,krait-l2-cache.h |  12 +
 include/linux/interconnect-clk.h              |   1 +
 include/soc/qcom/spm.h                        |   9 +
 23 files changed, 1403 insertions(+), 179 deletions(-)
 delete mode 100644 Documentation/devicetree/bindings/arm/msm/qcom,saw2.txt
 create mode 100644 Documentation/devicetree/bindings/cache/qcom,krait-l2-cache.yaml
 rename Documentation/devicetree/bindings/soc/qcom/{qcom,spm.yaml => qcom,saw2.yaml} (57%)
 create mode 100644 drivers/soc/qcom/krait-l2-cache.c
 create mode 100644 include/dt-bindings/clock/qcom,krait-cc.h
 create mode 100644 include/dt-bindings/soc/qcom,krait-l2-cache.h

-- 
2.39.2

[PATCH v2 01/26] dt-bindings: opp: opp-v2-kryo-cpu: support Qualcomm Krait SoCs

[Dmitry Baryshkov]

Exted the opp-v2-kryo-cpu.yaml to support defining OPP tables for the
previous generation of Qualcomm CPUs, 32-bit Krait-based platforms.

It makes no sense to use 'operating-points-v2-kryo-cpu' compatibility
node for the Krait cores. Add support for the Krait-specific
'operating-points-v2-krait-cpu' compatibility string and the relevant
opp-microvolt subclasses properties.

The listed opp-supported-hw values are applicable only to msm8996 /
msm8996pro platforms. Remove the enum as other platforms will use other
bit values. It makes little sense to list all possible values for all
the platforms here.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
 .../devicetree/bindings/opp/opp-v2-kryo-cpu.yaml     | 12 ++++++++----
 1 file changed, 8 insertions(+), 4 deletions(-)

diff --git a/Documentation/devicetree/bindings/opp/opp-v2-kryo-cpu.yaml b/Documentation/devicetree/bindings/opp/opp-v2-kryo-cpu.yaml
index bbbad31ae4ca..4e84d06d5ff9 100644
--- a/Documentation/devicetree/bindings/opp/opp-v2-kryo-cpu.yaml
+++ b/Documentation/devicetree/bindings/opp/opp-v2-kryo-cpu.yaml
@@ -26,7 +26,9 @@ description: |
 
 properties:
   compatible:
-    const: operating-points-v2-kryo-cpu
+    enum:
+      - operating-points-v2-krait-cpu
+      - operating-points-v2-kryo-cpu
 
   nvmem-cells:
     description: |
@@ -63,14 +65,16 @@ patternProperties:
           5:  MSM8996SG, speedbin 1
           6:  MSM8996SG, speedbin 2
           7-31:  unused
-        enum: [0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7,
-               0x9, 0xd, 0xe, 0xf,
-               0x10, 0x20, 0x30, 0x70]
+
+          Other platforms use bits directly corresponding to speedbin index.
 
       clock-latency-ns: true
 
       required-opps: true
 
+    patternProperties:
+      '^opp-microvolt-speed[0-9]+-pvs[0-9]+$': true
+
     required:
       - opp-hz
 
-- 
2.39.2

[PATCH v2 02/26] dt-bindings: soc: qcom: merge qcom,saw2.txt into qcom,spm.yaml

[Dmitry Baryshkov]

The Qualcomm SPM / SAW2 device is described in two bindigns files:
arm/msm/qcom,saw2.txt and soc/qcom/qcom,spm.yaml. Merge the former into
the latter, adding detailed device node description. While we are at it,
also rename qcom,spm.yaml to qcom,saw2.yaml to follow the actual
compatible used for these devices.

The regulator property is retained as is. It will be changed in the
later patches.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
 .../devicetree/bindings/arm/msm/qcom,saw2.txt | 58 -------------------
 .../qcom/{qcom,spm.yaml => qcom,saw2.yaml}    | 26 +++++++--
 2 files changed, 20 insertions(+), 64 deletions(-)
 delete mode 100644 Documentation/devicetree/bindings/arm/msm/qcom,saw2.txt
 rename Documentation/devicetree/bindings/soc/qcom/{qcom,spm.yaml => qcom,saw2.yaml} (64%)

diff --git a/Documentation/devicetree/bindings/arm/msm/qcom,saw2.txt b/Documentation/devicetree/bindings/arm/msm/qcom,saw2.txt
deleted file mode 100644
index c0e3c3a42bea..000000000000
--- a/Documentation/devicetree/bindings/arm/msm/qcom,saw2.txt
+++ /dev/null
@@ -1,58 +0,0 @@
-SPM AVS Wrapper 2 (SAW2)
-
-The SAW2 is a wrapper around the Subsystem Power Manager (SPM) and the
-Adaptive Voltage Scaling (AVS) hardware. The SPM is a programmable
-power-controller that transitions a piece of hardware (like a processor or
-subsystem) into and out of low power modes via a direct connection to
-the PMIC. It can also be wired up to interact with other processors in the
-system, notifying them when a low power state is entered or exited.
-
-Multiple revisions of the SAW hardware are supported using these Device Nodes.
-SAW2 revisions differ in the register offset and configuration data. Also, the
-same revision of the SAW in different SoCs may have different configuration
-data due the differences in hardware capabilities. Hence the SoC name, the
-version of the SAW hardware in that SoC and the distinction between cpu (big
-or Little) or cache, may be needed to uniquely identify the SAW register
-configuration and initialization data. The compatible string is used to
-indicate this parameter.
-
-PROPERTIES
-
-- compatible:
-	Usage: required
-	Value type: <string>
-	Definition: Must have
-			"qcom,saw2"
-		    A more specific value could be one of:
-			"qcom,apq8064-saw2-v1.1-cpu"
-			"qcom,msm8226-saw2-v2.1-cpu"
-			"qcom,msm8974-saw2-v2.1-cpu"
-			"qcom,apq8084-saw2-v2.1-cpu"
-
-- reg:
-	Usage: required
-	Value type: <prop-encoded-array>
-	Definition: the first element specifies the base address and size of
-		    the register region. An optional second element specifies
-		    the base address and size of the alias register region.
-
-- regulator:
-	Usage: optional
-	Value type: boolean
-	Definition: Indicates that this SPM device acts as a regulator device
-			device for the core (CPU or Cache) the SPM is attached
-			to.
-
-Example 1:
-
-	power-controller@2099000 {
-		compatible = "qcom,saw2";
-		reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
-		regulator;
-	};
-
-Example 2:
-	saw0: power-controller@f9089000 {
-		compatible = "qcom,apq8084-saw2-v2.1-cpu", "qcom,saw2";
-		reg = <0xf9089000 0x1000>, <0xf9009000 0x1000>;
-	};
diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,spm.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom,saw2.yaml
similarity index 64%
rename from Documentation/devicetree/bindings/soc/qcom/qcom,spm.yaml
rename to Documentation/devicetree/bindings/soc/qcom/qcom,saw2.yaml
index 20c8cd38ff0d..84b3f01d590c 100644
--- a/Documentation/devicetree/bindings/soc/qcom/qcom,spm.yaml
+++ b/Documentation/devicetree/bindings/soc/qcom/qcom,saw2.yaml
@@ -1,18 +1,25 @@
 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
 %YAML 1.2
 ---
-$id: http://devicetree.org/schemas/soc/qcom/qcom,spm.yaml#
+$id: http://devicetree.org/schemas/soc/qcom/qcom,saw2.yaml#
 $schema: http://devicetree.org/meta-schemas/core.yaml#
 
-title: Qualcomm Subsystem Power Manager
+title: Qualcomm Subsystem Power Manager / SPM AVS Wrapper 2 (SAW2)
 
 maintainers:
   - Andy Gross <agross@kernel.org>
   - Bjorn Andersson <bjorn.andersson@linaro.org>
 
 description: |
-  This binding describes the Qualcomm Subsystem Power Manager, used to control
-  the peripheral logic surrounding the application cores in Qualcomm platforms.
+  The Qualcomm Subsystem Power Manager is used to control the peripheral logic
+  surrounding the application cores in Qualcomm platforms.
+
+  The SAW2 is a wrapper around the Subsystem Power Manager (SPM) and the
+  Adaptive Voltage Scaling (AVS) hardware. The SPM is a programmable
+  power-controller that transitions a piece of hardware (like a processor or
+  subsystem) into and out of low power modes via a direct connection to
+  the PMIC. It can also be wired up to interact with other processors in the
+  system, notifying them when a low power state is entered or exited.
 
 properties:
   compatible:
@@ -34,8 +41,15 @@ properties:
       - const: qcom,saw2
 
   reg:
-    description: Base address and size of the SPM register region
-    maxItems: 1
+    items:
+      - description: Base address and size of the SPM register region
+      - description: Base address and size of the alias register region
+    minItems: 1
+
+  regulator:
+    type: boolean
+    description: Indicates that this SPM device acts as a regulator device
+      device for the core (CPU or Cache) the SPM is attached to.
 
 required:
   - compatible
-- 
2.39.2

[PATCH v2 03/26] dt-bindings: soc: qcom: qcom,saw2: define optional regulator node

[Dmitry Baryshkov]

The SAW2 device can optionally provide a voltage regulator supplying the
CPU core, cluster or L2 cache. Change the boolean 'regulator' property
into a proper regulator description. This breaks schema compatibility
for the sake of properly describing the regulator.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
 .../devicetree/bindings/soc/qcom/qcom,saw2.yaml   | 15 ++++++++++++++-
 1 file changed, 14 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,saw2.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom,saw2.yaml
index 84b3f01d590c..a2d871ba8c45 100644
--- a/Documentation/devicetree/bindings/soc/qcom/qcom,saw2.yaml
+++ b/Documentation/devicetree/bindings/soc/qcom/qcom,saw2.yaml
@@ -47,7 +47,7 @@ properties:
     minItems: 1
 
   regulator:
-    type: boolean
+    $ref: /schemas/regulator/regulator.yaml#
     description: Indicates that this SPM device acts as a regulator device
       device for the core (CPU or Cache) the SPM is attached to.
 
@@ -96,4 +96,17 @@ examples:
         reg = <0x17912000 0x1000>;
     };
 
+  - |
+    /*
+     * Example 3: SAW2 with the bundled regulator definition.
+     */
+    power-manager@2089000 {
+        compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
+        reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
+
+        regulator {
+            regulator-min-microvolt = <850000>;
+            regulator-max-microvolt = <1300000>;
+        };
+    };
 ...
-- 
2.39.2

[PATCH v2 04/26] dt-bindings: clock: qcom,krait-cc: Krait core clock controller

[Dmitry Baryshkov]

Define bindings for the Qualcomm Krait CPU and L2 clock controller. This
device is used on old Qualcomm SoCs (APQ8064, MSM8960) and supports up
to 4 core clocks and a separate L2 clock. Furthermore, L2 clock is
represented as the interconnect to facilitate L2 frequency scaling
together with scaling the CPU frequencies.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
 include/dt-bindings/clock/qcom,krait-cc.h | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)
 create mode 100644 include/dt-bindings/clock/qcom,krait-cc.h

diff --git a/include/dt-bindings/clock/qcom,krait-cc.h b/include/dt-bindings/clock/qcom,krait-cc.h
new file mode 100644
index 000000000000..ff69a0a968d8
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,krait-cc.h
@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (C) 2023 Linaro Ltd. All rights reserved.
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_QCOM_KRAIT_CC_H
+#define __DT_BINDINGS_CLOCK_QCOM_KRAIT_CC_H
+
+#define KRAIT_CPU_0		0
+#define KRAIT_CPU_1		1
+#define KRAIT_CPU_2		2
+#define KRAIT_CPU_3		3
+#define KRAIT_L2		4
+
+#define KRAIT_NUM_CLOCKS	5
+
+#endif
-- 
2.39.2

[PATCH v2 05/26] dt-bindings: cache: describe L2 cache on Qualcomm Krait platforms

[Dmitry Baryshkov]

The L2 cache device on Qualcomm Krait platforms controls the supplying
voltages and the cache frequency. Add corresponding bindings for this
device.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
 .../bindings/cache/qcom,krait-l2-cache.yaml   | 75 +++++++++++++++++++
 include/dt-bindings/soc/qcom,krait-l2-cache.h | 12 +++
 2 files changed, 87 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/cache/qcom,krait-l2-cache.yaml
 create mode 100644 include/dt-bindings/soc/qcom,krait-l2-cache.h

diff --git a/Documentation/devicetree/bindings/cache/qcom,krait-l2-cache.yaml b/Documentation/devicetree/bindings/cache/qcom,krait-l2-cache.yaml
new file mode 100644
index 000000000000..1dcf8165135b
--- /dev/null
+++ b/Documentation/devicetree/bindings/cache/qcom,krait-l2-cache.yaml
@@ -0,0 +1,75 @@
+# SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/cache/qcom,krait-l2-cache.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Krait L2 Cache
+
+maintainers:
+  - Bjorn Andersson <andersson@kernel.org>
+
+description:
+  L2 cache on Qualcomm Krait platforms is shared between all CPU cores. L2
+  cache frequency and voltages should be scaled according to the needs of the
+  cores.
+
+allOf:
+  - $ref: ../cache-controller.yaml#
+
+properties:
+  compatible:
+    items:
+      - const: qcom,krait-l2-cache
+      - const: cache
+
+  clocks:
+    maxItems: 1
+
+  '#interconnect-cells':
+    const: 1
+
+  vdd-mem-supply:
+    description: suppling regulator for the memory cells of the cache
+
+  vdd-dig-supply:
+    description: suppling regulator for the digital logic of the cache
+
+  operating-points-v2: true
+  opp-table-l2: true
+
+required:
+  - compatible
+  - cache-level
+  - cache-unified
+  - clocks
+  - '#interconnect-cells'
+
+unevaluatedProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/soc/qcom,krait-l2-cache.h>
+
+    l2-cache {
+        compatible = "qcom,krait-l2-cache", "cache";
+        cache-level = <2>;
+        cache-unified;
+        vdd-mem-supply = <&pm8921_l24>;
+        vdd-dig-supply = <&pm8921_s3>;
+        clocks = <&kraitcc 4>;
+        #interconnect-cells = <1>;
+        operating-points-v2 = <&l2_opp_table>;
+
+        l2_opp_table: opp-table-l2 {
+            compatible = "operating-points-v2";
+
+            opp-384000000 {
+                opp-hz = /bits/ 64 <384000000>;
+                opp-microvolt = <1050000 1050000 1150000>,
+                                <950000 950000 1150000>;
+            };
+        };
+    };
+...
+
diff --git a/include/dt-bindings/soc/qcom,krait-l2-cache.h b/include/dt-bindings/soc/qcom,krait-l2-cache.h
new file mode 100644
index 000000000000..c9a38d368111
--- /dev/null
+++ b/include/dt-bindings/soc/qcom,krait-l2-cache.h
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (C) 2023 Linaro Ltd. All rights reserved.
+ */
+
+#ifndef __DT_BINDINGS_SOC_QCOM_KRAIT_L2_CACHE_H
+#define __DT_BINDINGS_SOC_QCOM_KRAIT_L2_CACHE_H
+
+#define MASTER_KRAIT_L2		0
+#define SLAVE_KRAIT_L2		1
+
+#endif
-- 
2.39.2

[PATCH v2 06/26] interconnect: icc-clk: add support for scaling using OPP

[Dmitry Baryshkov]

Sometimes it might be required to scale the clock using the OPP
framework (e.g. to scale regulators following the required clock rate).
Extend the interconnec-clk framework to handle OPP case in addition to
scaling the clock.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
 drivers/interconnect/icc-clk.c   | 13 +++++++++++--
 include/linux/interconnect-clk.h |  1 +
 2 files changed, 12 insertions(+), 2 deletions(-)

diff --git a/drivers/interconnect/icc-clk.c b/drivers/interconnect/icc-clk.c
index 4d43ebff4257..c7962acdcee7 100644
--- a/drivers/interconnect/icc-clk.c
+++ b/drivers/interconnect/icc-clk.c
@@ -7,10 +7,13 @@
 #include <linux/device.h>
 #include <linux/interconnect-clk.h>
 #include <linux/interconnect-provider.h>
+#include <linux/pm_opp.h>
 
 struct icc_clk_node {
+	struct device *dev;
 	struct clk *clk;
 	bool enabled;
+	bool opp;
 };
 
 struct icc_clk_provider {
@@ -25,12 +28,16 @@ struct icc_clk_provider {
 static int icc_clk_set(struct icc_node *src, struct icc_node *dst)
 {
 	struct icc_clk_node *qn = src->data;
+	unsigned long rate = icc_units_to_bps(src->peak_bw);
 	int ret;
 
 	if (!qn || !qn->clk)
 		return 0;
 
-	if (!src->peak_bw) {
+	if (qn->opp)
+		return dev_pm_opp_set_rate(qn->dev, rate);
+
+	if (!rate) {
 		if (qn->enabled)
 			clk_disable_unprepare(qn->clk);
 		qn->enabled = false;
@@ -45,7 +52,7 @@ static int icc_clk_set(struct icc_node *src, struct icc_node *dst)
 		qn->enabled = true;
 	}
 
-	return clk_set_rate(qn->clk, icc_units_to_bps(src->peak_bw));
+	return clk_set_rate(qn->clk, rate);
 }
 
 static int icc_clk_get_bw(struct icc_node *node, u32 *avg, u32 *peak)
@@ -106,7 +113,9 @@ struct icc_provider *icc_clk_register(struct device *dev,
 	icc_provider_init(provider);
 
 	for (i = 0, j = 0; i < num_clocks; i++) {
+		qp->clocks[i].dev = dev;
 		qp->clocks[i].clk = data[i].clk;
+		qp->clocks[i].opp = data[i].opp;
 
 		node = icc_node_create(first_id + j);
 		if (IS_ERR(node)) {
diff --git a/include/linux/interconnect-clk.h b/include/linux/interconnect-clk.h
index 0cd80112bea5..c695e5099901 100644
--- a/include/linux/interconnect-clk.h
+++ b/include/linux/interconnect-clk.h
@@ -11,6 +11,7 @@ struct device;
 struct icc_clk_data {
 	struct clk *clk;
 	const char *name;
+	bool opp;
 };
 
 struct icc_provider *icc_clk_register(struct device *dev,
-- 
2.39.2

[PATCH v2 07/26] clk: qcom: krait-cc: rewrite driver to use clk_hw instead of clk

[Dmitry Baryshkov]

The krait-cc driver still uses struct clk internally. Rewrite it to
allocate and register struct clk_hw instead.

Reviewed-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
 drivers/clk/qcom/krait-cc.c | 141 ++++++++++++++++--------------------
 1 file changed, 63 insertions(+), 78 deletions(-)

diff --git a/drivers/clk/qcom/krait-cc.c b/drivers/clk/qcom/krait-cc.c
index 410ae8390f1c..a37abbd31f50 100644
--- a/drivers/clk/qcom/krait-cc.c
+++ b/drivers/clk/qcom/krait-cc.c
@@ -13,17 +13,9 @@
 #include <linux/clk-provider.h>
 #include <linux/slab.h>
 
-#include "clk-krait.h"
-
-enum {
-	cpu0_mux = 0,
-	cpu1_mux,
-	cpu2_mux,
-	cpu3_mux,
-	l2_mux,
+#include <dt-bindings/clock/qcom,krait-cc.h>
 
-	clks_max,
-};
+#include "clk-krait.h"
 
 static unsigned int sec_mux_map[] = {
 	2,
@@ -235,7 +227,7 @@ krait_add_pri_mux(struct device *dev, struct clk_hw *hfpll_div, struct clk_hw *s
 		.parent_data = p_data,
 		.num_parents = ARRAY_SIZE(p_data),
 		.ops = &krait_mux_clk_ops,
-		.flags = CLK_SET_RATE_PARENT,
+		.flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
 	};
 	struct clk_hw *clk;
 	char *hfpll_name;
@@ -324,19 +316,6 @@ static struct clk_hw *krait_add_clks(struct device *dev, int id, bool unique_aux
 	return pri_mux;
 }
 
-static struct clk *krait_of_get(struct of_phandle_args *clkspec, void *data)
-{
-	unsigned int idx = clkspec->args[0];
-	struct clk **clks = data;
-
-	if (idx >= clks_max) {
-		pr_err("%s: invalid clock index %d\n", __func__, idx);
-		return ERR_PTR(-EINVAL);
-	}
-
-	return clks[idx] ? : ERR_PTR(-ENODEV);
-}
-
 static const struct of_device_id krait_cc_match_table[] = {
 	{ .compatible = "qcom,krait-cc-v1", (void *)1UL },
 	{ .compatible = "qcom,krait-cc-v2" },
@@ -344,60 +323,84 @@ static const struct of_device_id krait_cc_match_table[] = {
 };
 MODULE_DEVICE_TABLE(of, krait_cc_match_table);
 
+static int krait_clk_reinit(struct clk_hw *hw, int cpu)
+{
+	struct clk *clk;
+	unsigned long cur_rate, aux_rate;
+	char name[5]; /* CPUn */
+
+	if (cpu == -1)
+		strcpy(name, "L2");
+	else
+		snprintf(name, sizeof(name), "CPU%d", cpu);
+
+	clk = clk_hw_get_clk(hw, clk_hw_get_name(hw));
+	if (IS_ERR(clk))
+		return PTR_ERR(clk);
+
+	aux_rate = 384000000;
+
+	cur_rate = clk_get_rate(clk);
+	if (cur_rate < aux_rate) {
+		pr_info("%s @ Undefined rate %lu. Forcing new rate.\n",
+			name, cur_rate / 1000);
+		cur_rate = aux_rate;
+	}
+
+	clk_set_rate(clk, aux_rate);
+	clk_set_rate(clk, 2);
+	clk_set_rate(clk, cur_rate);
+	pr_info("%s @ %lu KHz\n", name, clk_get_rate(clk) / 1000);
+
+	clk_put(clk);
+
+	return 0;
+}
+
+/* Krait configurations have at most 4 CPUs and one L2 */
+#define KRAIT_NUM_CLOCKS 5
+
 static int krait_cc_probe(struct platform_device *pdev)
 {
 	struct device *dev = &pdev->dev;
 	const struct of_device_id *id;
-	unsigned long cur_rate, aux_rate;
-	int cpu;
-	struct clk_hw *mux, *l2_pri_mux;
-	struct clk *clk, **clks;
+	int cpu, ret;
+	struct clk_hw *clk;
+	struct clk_hw_onecell_data *clks;
 
 	id = of_match_device(krait_cc_match_table, dev);
 	if (!id)
 		return -ENODEV;
 
 	/* Rate is 1 because 0 causes problems for __clk_mux_determine_rate */
-	clk = clk_register_fixed_rate(dev, "qsb", NULL, 0, 1);
+	clk = clk_hw_register_fixed_rate(dev, "qsb", NULL, 0, 1);
 	if (IS_ERR(clk))
 		return PTR_ERR(clk);
 
 	if (!id->data) {
-		clk = clk_register_fixed_factor(dev, "acpu_aux",
-						"gpll0_vote", 0, 1, 2);
+		clk = clk_hw_register_fixed_factor(dev, "acpu_aux", "gpll0_vote", 0, 1, 2);
 		if (IS_ERR(clk))
 			return PTR_ERR(clk);
 	}
 
-	/* Krait configurations have at most 4 CPUs and one L2 */
-	clks = devm_kcalloc(dev, clks_max, sizeof(*clks), GFP_KERNEL);
+	clks = devm_kzalloc(dev, struct_size(clks, hws, KRAIT_NUM_CLOCKS), GFP_KERNEL);
 	if (!clks)
 		return -ENOMEM;
 
+	clks->num = KRAIT_NUM_CLOCKS;
+	BUILD_BUG_ON(KRAIT_L2 >= KRAIT_NUM_CLOCKS);
+
 	for_each_possible_cpu(cpu) {
-		mux = krait_add_clks(dev, cpu, id->data);
-		if (IS_ERR(mux))
-			return PTR_ERR(mux);
-		clks[cpu] = mux->clk;
+		clk = krait_add_clks(dev, cpu, id->data);
+		if (IS_ERR(clk))
+			return PTR_ERR(clk);
+		clks->hws[cpu] = clk;
 	}
 
-	l2_pri_mux = krait_add_clks(dev, -1, id->data);
-	if (IS_ERR(l2_pri_mux))
-		return PTR_ERR(l2_pri_mux);
-	clks[l2_mux] = l2_pri_mux->clk;
-
-	/*
-	 * We don't want the CPU or L2 clocks to be turned off at late init
-	 * if CPUFREQ or HOTPLUG configs are disabled. So, bump up the
-	 * refcount of these clocks. Any cpufreq/hotplug manager can assume
-	 * that the clocks have already been prepared and enabled by the time
-	 * they take over.
-	 */
-	for_each_online_cpu(cpu) {
-		clk_prepare_enable(clks[l2_mux]);
-		WARN(clk_prepare_enable(clks[cpu]),
-		     "Unable to turn on CPU%d clock", cpu);
-	}
+	clk = krait_add_clks(dev, -1, id->data);
+	if (IS_ERR(clk))
+		return PTR_ERR(clk);
+	clks->hws[KRAIT_L2] = clk;
 
 	/*
 	 * Force reinit of HFPLLs and muxes to overwrite any potential
@@ -410,31 +413,13 @@ static int krait_cc_probe(struct platform_device *pdev)
 	 * two different rates to force a HFPLL reinit under all
 	 * circumstances.
 	 */
-	cur_rate = clk_get_rate(clks[l2_mux]);
-	aux_rate = 384000000;
-	if (cur_rate < aux_rate) {
-		pr_info("L2 @ Undefined rate. Forcing new rate.\n");
-		cur_rate = aux_rate;
-	}
-	clk_set_rate(clks[l2_mux], aux_rate);
-	clk_set_rate(clks[l2_mux], 2);
-	clk_set_rate(clks[l2_mux], cur_rate);
-	pr_info("L2 @ %lu KHz\n", clk_get_rate(clks[l2_mux]) / 1000);
-	for_each_possible_cpu(cpu) {
-		clk = clks[cpu];
-		cur_rate = clk_get_rate(clk);
-		if (cur_rate < aux_rate) {
-			pr_info("CPU%d @ Undefined rate. Forcing new rate.\n", cpu);
-			cur_rate = aux_rate;
-		}
+	krait_clk_reinit(clks->hws[KRAIT_L2], -1);
+	for_each_possible_cpu(cpu)
+		krait_clk_reinit(clks->hws[cpu], cpu);
 
-		clk_set_rate(clk, aux_rate);
-		clk_set_rate(clk, 2);
-		clk_set_rate(clk, cur_rate);
-		pr_info("CPU%d @ %lu KHz\n", cpu, clk_get_rate(clk) / 1000);
-	}
-
-	of_clk_add_provider(dev->of_node, krait_of_get, clks);
+	ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, clks);
+	if (ret)
+		return ret;
 
 	return 0;
 }
-- 
2.39.2

[PATCH v2 08/26] soc: qcom: spm: add support for voltage regulator

[Dmitry Baryshkov]

The SPM / SAW2 device also provides a voltage regulator functionality
with optional AVS (Adaptive Voltage Scaling) support. The exact register
sequence and voltage ranges differs from device to device.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
 drivers/soc/qcom/spm.c | 205 ++++++++++++++++++++++++++++++++++++++++-
 include/soc/qcom/spm.h |   9 ++
 2 files changed, 212 insertions(+), 2 deletions(-)

diff --git a/drivers/soc/qcom/spm.c b/drivers/soc/qcom/spm.c
index a6cbeb40831b..3c16a7e1710c 100644
--- a/drivers/soc/qcom/spm.c
+++ b/drivers/soc/qcom/spm.c
@@ -9,19 +9,31 @@
 #include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/io.h>
+#include <linux/iopoll.h>
+#include <linux/linear_range.h>
 #include <linux/module.h>
 #include <linux/slab.h>
 #include <linux/of.h>
 #include <linux/of_address.h>
 #include <linux/of_device.h>
+#include <linux/bitfield.h>
 #include <linux/err.h>
 #include <linux/platform_device.h>
+#include <linux/regulator/driver.h>
+#include <linux/smp.h>
 #include <soc/qcom/spm.h>
 
+#define FIELD_SET(current, mask, val)	\
+	(((current) & ~(mask)) | FIELD_PREP((mask), (val)))
+
 #define SPM_CTL_INDEX		0x7f
 #define SPM_CTL_INDEX_SHIFT	4
 #define SPM_CTL_EN		BIT(0)
 
+#define SPM_1_1_AVS_CTL_AVS_ENABLED BIT(27)
+#define SPM_AVS_CTL_MIN_VLVL	(0x3f << 10)
+#define SPM_AVS_CTL_MAX_VLVL	(0x3f << 17)
+
 enum spm_reg {
 	SPM_REG_CFG,
 	SPM_REG_SPM_CTL,
@@ -31,10 +43,12 @@ enum spm_reg {
 	SPM_REG_PMIC_DATA_1,
 	SPM_REG_VCTL,
 	SPM_REG_SEQ_ENTRY,
-	SPM_REG_SPM_STS,
+	SPM_REG_STS0,
+	SPM_REG_STS1,
 	SPM_REG_PMIC_STS,
 	SPM_REG_AVS_CTL,
 	SPM_REG_AVS_LIMIT,
+	SPM_REG_RST,
 	SPM_REG_NR,
 };
 
@@ -171,6 +185,10 @@ static const struct spm_reg_data spm_reg_8226_cpu  = {
 
 static const u16 spm_reg_offset_v1_1[SPM_REG_NR] = {
 	[SPM_REG_CFG]		= 0x08,
+	[SPM_REG_STS0]		= 0x0c,
+	[SPM_REG_STS1]		= 0x10,
+	[SPM_REG_VCTL]		= 0x14,
+	[SPM_REG_AVS_CTL]	= 0x18,
 	[SPM_REG_SPM_CTL]	= 0x20,
 	[SPM_REG_PMIC_DLY]	= 0x24,
 	[SPM_REG_PMIC_DATA_0]	= 0x28,
@@ -178,7 +196,12 @@ static const u16 spm_reg_offset_v1_1[SPM_REG_NR] = {
 	[SPM_REG_SEQ_ENTRY]	= 0x80,
 };
 
+static void smp_set_vdd_v1_1(void *data);
+
 /* SPM register data for 8064 */
+static struct linear_range spm_v1_1_regulator_range =
+	REGULATOR_LINEAR_RANGE(700000, 0, 56, 12500);
+
 static const struct spm_reg_data spm_reg_8064_cpu = {
 	.reg_offset = spm_reg_offset_v1_1,
 	.spm_cfg = 0x1F,
@@ -189,6 +212,10 @@ static const struct spm_reg_data spm_reg_8064_cpu = {
 		0x10, 0x54, 0x30, 0x0C, 0x24, 0x30, 0x0F },
 	.start_index[PM_SLEEP_MODE_STBY] = 0,
 	.start_index[PM_SLEEP_MODE_SPC] = 2,
+	.set_vdd = smp_set_vdd_v1_1,
+	.range = &spm_v1_1_regulator_range,
+	.init_uV = 1300000,
+	.ramp_delay = 1250,
 };
 
 static inline void spm_register_write(struct spm_driver_data *drv,
@@ -240,6 +267,179 @@ void spm_set_low_power_mode(struct spm_driver_data *drv,
 	spm_register_write_sync(drv, SPM_REG_SPM_CTL, ctl_val);
 }
 
+static int spm_set_voltage_sel(struct regulator_dev *rdev, unsigned int selector)
+{
+	struct spm_driver_data *drv = rdev_get_drvdata(rdev);
+
+	drv->volt_sel = selector;
+
+	/* Always do the SAW register writes on the corresponding CPU */
+	return smp_call_function_single(drv->reg_cpu, drv->reg_data->set_vdd, drv, true);
+}
+
+static int spm_get_voltage_sel(struct regulator_dev *rdev)
+{
+	struct spm_driver_data *drv = rdev_get_drvdata(rdev);
+
+	return drv->volt_sel;
+}
+
+static const struct regulator_ops spm_reg_ops = {
+	.set_voltage_sel	= spm_set_voltage_sel,
+	.get_voltage_sel	= spm_get_voltage_sel,
+	.list_voltage		= regulator_list_voltage_linear_range,
+	.set_voltage_time_sel	= regulator_set_voltage_time_sel,
+};
+
+static void smp_set_vdd_v1_1(void *data)
+{
+	struct spm_driver_data *drv = data;
+	unsigned int vlevel = drv->volt_sel;
+	unsigned int vctl, data0, data1, avs_ctl, sts;
+	bool avs_enabled;
+
+	vlevel |= 0x80; /* band */
+
+	avs_ctl = spm_register_read(drv, SPM_REG_AVS_CTL);
+	vctl = spm_register_read(drv, SPM_REG_VCTL);
+	data0 = spm_register_read(drv, SPM_REG_PMIC_DATA_0);
+	data1 = spm_register_read(drv, SPM_REG_PMIC_DATA_1);
+
+	avs_enabled = avs_ctl & SPM_1_1_AVS_CTL_AVS_ENABLED;
+
+	/* If AVS is enabled, switch it off during the voltage change */
+	if (avs_enabled) {
+		avs_ctl &= ~SPM_1_1_AVS_CTL_AVS_ENABLED;
+		spm_register_write(drv, SPM_REG_AVS_CTL, avs_ctl);
+	}
+
+	/* Kick the state machine back to idle */
+	spm_register_write(drv, SPM_REG_RST, 1);
+
+	vctl = FIELD_SET(vctl, 0xff, vlevel);
+	data0 = FIELD_SET(data0, 0xff, vlevel);
+	data1 = FIELD_SET(data1, 0x3f, vlevel);
+	data1 = FIELD_SET(data1, 0x3f << 16, vlevel);
+
+	spm_register_write(drv, SPM_REG_VCTL, vctl);
+	spm_register_write(drv, SPM_REG_PMIC_DATA_0, data0);
+	spm_register_write(drv, SPM_REG_PMIC_DATA_1, data1);
+
+	if (read_poll_timeout_atomic(spm_register_read,
+				      sts, sts == vlevel,
+				      1, 200, false,
+				      drv, SPM_REG_STS1)) {
+		dev_err_ratelimited(drv->dev, "timeout setting the voltage (%x %x)!\n", sts, vlevel);
+		goto enable_avs;
+	}
+
+	if (avs_enabled) {
+		unsigned int max_avs = vlevel & 0x3f;
+		unsigned int min_avs = max(max_avs, 4U) - 4;
+		avs_ctl = FIELD_SET(avs_ctl, SPM_AVS_CTL_MIN_VLVL, min_avs);
+		avs_ctl = FIELD_SET(avs_ctl, SPM_AVS_CTL_MAX_VLVL, max_avs);
+		spm_register_write(drv, SPM_REG_AVS_CTL, avs_ctl);
+	}
+
+enable_avs:
+	if (avs_enabled) {
+		avs_ctl |= SPM_1_1_AVS_CTL_AVS_ENABLED;
+		spm_register_write(drv, SPM_REG_AVS_CTL, avs_ctl);
+	}
+}
+
+static int spm_get_cpu(struct device *dev)
+{
+	int cpu;
+	bool found;
+
+	for_each_possible_cpu(cpu) {
+		struct device_node *cpu_node, *saw_node;
+
+		cpu_node = of_cpu_device_node_get(cpu);
+		if (!cpu_node)
+			continue;
+
+		saw_node = of_parse_phandle(cpu_node, "qcom,saw", 0);
+		found = (saw_node == dev->of_node);
+		of_node_put(saw_node);
+		of_node_put(cpu_node);
+
+		if (found)
+			return cpu;
+	}
+
+	/* L2 SPM is not bound to any CPU, tie it to CPU0 */
+
+	return 0;
+}
+
+#ifdef CONFIG_REGULATOR
+static int spm_register_regulator(struct device *dev, struct spm_driver_data *drv)
+{
+	struct regulator_config config = {
+		.dev = dev,
+		.driver_data = drv,
+	};
+	struct regulator_desc *rdesc;
+	struct regulator_dev *rdev;
+	int ret;
+	bool found;
+
+	if (!drv->reg_data->set_vdd)
+		return 0;
+
+	rdesc = devm_kzalloc(dev, sizeof(*rdesc), GFP_KERNEL);
+	if (!rdesc)
+		return -ENOMEM;
+
+	rdesc->name = "spm";
+	rdesc->of_match = of_match_ptr("regulator");
+	rdesc->type = REGULATOR_VOLTAGE;
+	rdesc->owner = THIS_MODULE;
+	rdesc->ops = &spm_reg_ops;
+
+	rdesc->linear_ranges = drv->reg_data->range;
+	rdesc->n_linear_ranges = 1;
+	rdesc->n_voltages = rdesc->linear_ranges[rdesc->n_linear_ranges - 1].max_sel + 1;
+	rdesc->ramp_delay = drv->reg_data->ramp_delay;
+
+	drv->reg_cpu = spm_get_cpu(dev);
+	dev_dbg(dev, "SAW2 bound to CPU %d\n", drv->reg_cpu);
+
+	/*
+	 * Program initial voltage, otherwise registration will also try
+	 * setting the voltage, which might result in undervolting the CPU.
+	 */
+	drv->volt_sel = DIV_ROUND_UP(drv->reg_data->init_uV - rdesc->min_uV,
+				     rdesc->uV_step);
+	ret = linear_range_get_selector_high(drv->reg_data->range,
+					     drv->reg_data->init_uV,
+					     &drv->volt_sel,
+					     &found);
+	if (ret) {
+		dev_err(dev, "Initial uV value out of bounds\n");
+		return ret;
+	}
+
+	/* Always do the SAW register writes on the corresponding CPU */
+	smp_call_function_single(drv->reg_cpu, drv->reg_data->set_vdd, drv, true);
+
+	rdev = devm_regulator_register(dev, rdesc, &config);
+	if (IS_ERR(rdev)) {
+		dev_err(dev, "failed to register regulator\n");
+		return PTR_ERR(rdev);
+	}
+
+	return 0;
+}
+#else
+static int spm_register_regulator(struct device *dev, struct spm_driver_data *drv)
+{
+	return 0;
+}
+#endif
+
 static const struct of_device_id spm_match_table[] = {
 	{ .compatible = "qcom,sdm660-gold-saw2-v4.1-l2",
 	  .data = &spm_reg_660_gold_l2 },
@@ -292,6 +492,7 @@ static int spm_dev_probe(struct platform_device *pdev)
 		return -ENODEV;
 
 	drv->reg_data = match_id->data;
+	drv->dev = &pdev->dev;
 	platform_set_drvdata(pdev, drv);
 
 	/* Write the SPM sequences first.. */
@@ -319,7 +520,7 @@ static int spm_dev_probe(struct platform_device *pdev)
 	if (drv->reg_data->reg_offset[SPM_REG_SPM_CTL])
 		spm_set_low_power_mode(drv, PM_SLEEP_MODE_STBY);
 
-	return 0;
+	return spm_register_regulator(&pdev->dev, drv);
 }
 
 static struct platform_driver spm_driver = {
diff --git a/include/soc/qcom/spm.h b/include/soc/qcom/spm.h
index 4951f9d8b0bd..9859ebe42003 100644
--- a/include/soc/qcom/spm.h
+++ b/include/soc/qcom/spm.h
@@ -30,11 +30,20 @@ struct spm_reg_data {
 	u32 avs_limit;
 	u8 seq[MAX_SEQ_DATA];
 	u8 start_index[PM_SLEEP_MODE_NR];
+
+	smp_call_func_t set_vdd;
+	/* for now we support only a single range */
+	struct linear_range *range;
+	unsigned int ramp_delay;
+	unsigned int init_uV;
 };
 
 struct spm_driver_data {
 	void __iomem *reg_base;
 	const struct spm_reg_data *reg_data;
+	struct device *dev;
+	unsigned int volt_sel;
+	int reg_cpu;
 };
 
 void spm_set_low_power_mode(struct spm_driver_data *drv,
-- 
2.39.2

[PATCH v2 09/26] cpufreq: qcom-nvmem: create L2 cache device

[Dmitry Baryshkov]

Scaling the frequencies on some of Qualcomm Krait platforms (e.g.
APQ8064) also requires scaling of the L2 cache frequency. As the
l2-cache device node is places under /cpus/ path, it is not created by
default by the OF code. Create corresponding device here.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
 drivers/cpufreq/qcom-cpufreq-nvmem.c | 20 ++++++++++++++++++++
 1 file changed, 20 insertions(+)

diff --git a/drivers/cpufreq/qcom-cpufreq-nvmem.c b/drivers/cpufreq/qcom-cpufreq-nvmem.c
index a88b6fe5db50..ab78ef1531d0 100644
--- a/drivers/cpufreq/qcom-cpufreq-nvmem.c
+++ b/drivers/cpufreq/qcom-cpufreq-nvmem.c
@@ -380,6 +380,7 @@ static int __init qcom_cpufreq_init(void)
 {
 	struct device_node *np = of_find_node_by_path("/");
 	const struct of_device_id *match;
+	unsigned int cpu;
 	int ret;
 
 	if (!np)
@@ -390,6 +391,25 @@ static int __init qcom_cpufreq_init(void)
 	if (!match)
 		return -ENODEV;
 
+	for_each_possible_cpu(cpu) {
+		struct device *dev = get_cpu_device(cpu);
+		struct device_node *cache;
+		struct platform_device *pdev;
+
+		cache = of_find_next_cache_node(dev->of_node);
+		if (!cache)
+			continue;
+
+		if (of_device_is_compatible(cache, "qcom,krait-l2-cache")) {
+			pdev = of_platform_device_create(cache, NULL, NULL);
+			if (IS_ERR(pdev))
+				pr_err("%s: %pe, failed to create L2 cache node\n", __func__, pdev);
+			/* the error is not fatal */
+		}
+
+		of_node_put(cache);
+	}
+
 	ret = platform_driver_register(&qcom_cpufreq_driver);
 	if (unlikely(ret < 0))
 		return ret;
-- 
2.39.2

[PATCH v2 10/26] cpufreq: qcom-nvmem: also accept operating-points-v2-krait-cpu

[Dmitry Baryshkov]

the qcom-cpufreq-nvmem driver attempts to support both Qualcomm Kryo
(newer 64-bit ARMv8 cores) and Krait (older 32-bit ARMv7 cores). It
makes no sense to use 'operating-points-v2-kryo-cpu' compatibility node
for the Krait cores. Add support for 'operating-points-v2-krait-cpu'
compatibility string.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
 drivers/cpufreq/qcom-cpufreq-nvmem.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/cpufreq/qcom-cpufreq-nvmem.c b/drivers/cpufreq/qcom-cpufreq-nvmem.c
index ab78ef1531d0..3bb552f498da 100644
--- a/drivers/cpufreq/qcom-cpufreq-nvmem.c
+++ b/drivers/cpufreq/qcom-cpufreq-nvmem.c
@@ -238,7 +238,8 @@ static int qcom_cpufreq_probe(struct platform_device *pdev)
 	if (!np)
 		return -ENOENT;
 
-	ret = of_device_is_compatible(np, "operating-points-v2-kryo-cpu");
+	ret = of_device_is_compatible(np, "operating-points-v2-kryo-cpu") ||
+	      of_device_is_compatible(np, "operating-points-v2-krait-cpu");
 	if (!ret) {
 		of_node_put(np);
 		return -ENOENT;
-- 
2.39.2

[PATCH v2 11/26] cpufreq: qcom-nvmem: drop pvs_ver for format a fuses

[Dmitry Baryshkov]

The fuses used on msm8960 / apq8064 / ipq806x families of devices do not
have the pvs version. Drop this argument from parsing function.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
 drivers/cpufreq/qcom-cpufreq-nvmem.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/cpufreq/qcom-cpufreq-nvmem.c b/drivers/cpufreq/qcom-cpufreq-nvmem.c
index 3bb552f498da..2a591fafc090 100644
--- a/drivers/cpufreq/qcom-cpufreq-nvmem.c
+++ b/drivers/cpufreq/qcom-cpufreq-nvmem.c
@@ -50,7 +50,7 @@ struct qcom_cpufreq_drv {
 static struct platform_device *cpufreq_dt_pdev, *cpufreq_pdev;
 
 static void get_krait_bin_format_a(struct device *cpu_dev,
-					  int *speed, int *pvs, int *pvs_ver,
+					  int *speed, int *pvs,
 					  u8 *buf)
 {
 	u32 pte_efuse;
@@ -181,7 +181,7 @@ static int qcom_cpufreq_krait_name_version(struct device *cpu_dev,
 
 	switch (len) {
 	case 4:
-		get_krait_bin_format_a(cpu_dev, &speed, &pvs, &pvs_ver,
+		get_krait_bin_format_a(cpu_dev, &speed, &pvs,
 				       speedbin);
 		break;
 	case 8:
-- 
2.39.2

[PATCH v2 12/26] cpufreq: qcom-nvmem: provide separate configuration data for apq8064

[Dmitry Baryshkov]

APQ8064 can scale core voltage according to the frequency needs. Rather
than reusing the A/B format multiplexer, use a simple fuse parsing
function and configure required regulator.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
 drivers/cpufreq/qcom-cpufreq-nvmem.c | 49 ++++++++++++++++++++++++++--
 1 file changed, 47 insertions(+), 2 deletions(-)

diff --git a/drivers/cpufreq/qcom-cpufreq-nvmem.c b/drivers/cpufreq/qcom-cpufreq-nvmem.c
index 2a591fafc090..9cbc37ce91a8 100644
--- a/drivers/cpufreq/qcom-cpufreq-nvmem.c
+++ b/drivers/cpufreq/qcom-cpufreq-nvmem.c
@@ -26,6 +26,7 @@
 #include <linux/platform_device.h>
 #include <linux/pm_domain.h>
 #include <linux/pm_opp.h>
+#include <linux/regulator/consumer.h>
 #include <linux/slab.h>
 #include <linux/soc/qcom/smem.h>
 
@@ -39,6 +40,7 @@ struct qcom_cpufreq_match_data {
 			   char **pvs_name,
 			   struct qcom_cpufreq_drv *drv);
 	const char **genpd_names;
+	const char * const *regulator_names;
 };
 
 struct qcom_cpufreq_drv {
@@ -204,6 +206,34 @@ static int qcom_cpufreq_krait_name_version(struct device *cpu_dev,
 	return ret;
 }
 
+static int qcom_cpufreq_apq8064_name_version(struct device *cpu_dev,
+					     struct nvmem_cell *speedbin_nvmem,
+					     char **pvs_name,
+					     struct qcom_cpufreq_drv *drv)
+{
+	int speed = 0, pvs = 0;
+	u8 *speedbin;
+	size_t len;
+	int ret = 0;
+
+	speedbin = nvmem_cell_read(speedbin_nvmem, &len);
+	if (IS_ERR(speedbin))
+		return PTR_ERR(speedbin);
+
+	if (len != 4)
+		return -EINVAL;
+
+	get_krait_bin_format_a(cpu_dev, &speed, &pvs, speedbin);
+
+	snprintf(*pvs_name, sizeof("speedXX-pvsXX"), "speed%d-pvs%d",
+		 speed, pvs);
+
+	drv->versions = (1 << speed);
+
+	kfree(speedbin);
+	return ret;
+}
+
 static const struct qcom_cpufreq_match_data match_data_kryo = {
 	.get_version = qcom_cpufreq_kryo_name_version,
 };
@@ -218,6 +248,16 @@ static const struct qcom_cpufreq_match_data match_data_qcs404 = {
 	.genpd_names = qcs404_genpd_names,
 };
 
+static const char * apq8064_regulator_names[] = {
+	"vdd-core",
+	NULL
+};
+
+static const struct qcom_cpufreq_match_data match_data_apq8064 = {
+	.get_version = qcom_cpufreq_apq8064_name_version,
+	.regulator_names = apq8064_regulator_names,
+};
+
 static int qcom_cpufreq_probe(struct platform_device *pdev)
 {
 	struct qcom_cpufreq_drv *drv;
@@ -305,7 +345,12 @@ static int qcom_cpufreq_probe(struct platform_device *pdev)
 			config.virt_devs = NULL;
 		}
 
-		if (config.supported_hw || config.genpd_names) {
+		if (drv->data->regulator_names)
+			config.regulator_names = drv->data->regulator_names;
+
+		if (config.supported_hw ||
+		    config.genpd_names ||
+		    config.regulator_names) {
 			drv->opp_tokens[cpu] = dev_pm_opp_set_config(cpu_dev, &config);
 			if (drv->opp_tokens[cpu] < 0) {
 				ret = drv->opp_tokens[cpu];
@@ -364,7 +409,7 @@ static const struct of_device_id qcom_cpufreq_match_list[] __initconst = {
 	{ .compatible = "qcom,msm8996", .data = &match_data_kryo },
 	{ .compatible = "qcom,qcs404", .data = &match_data_qcs404 },
 	{ .compatible = "qcom,ipq8064", .data = &match_data_krait },
-	{ .compatible = "qcom,apq8064", .data = &match_data_krait },
+	{ .compatible = "qcom,apq8064", .data = &match_data_apq8064 },
 	{ .compatible = "qcom,msm8974", .data = &match_data_krait },
 	{ .compatible = "qcom,msm8960", .data = &match_data_krait },
 	{},
-- 
2.39.2

[PATCH v2 13/26] soc: qcom: Add driver for Qualcomm Krait L2 cache scaling

[Dmitry Baryshkov]

Add a simple driver that handles scaling of L2 frequency and voltages.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
 drivers/soc/qcom/Kconfig          |   9 ++
 drivers/soc/qcom/Makefile         |   1 +
 drivers/soc/qcom/krait-l2-cache.c | 190 ++++++++++++++++++++++++++++++
 3 files changed, 200 insertions(+)
 create mode 100644 drivers/soc/qcom/krait-l2-cache.c

diff --git a/drivers/soc/qcom/Kconfig b/drivers/soc/qcom/Kconfig
index e597799e8121..01090b7a3c06 100644
--- a/drivers/soc/qcom/Kconfig
+++ b/drivers/soc/qcom/Kconfig
@@ -70,6 +70,15 @@ config QCOM_LLCC
 	  SDM845. This provides interfaces to clients that use the LLCC.
 	  Say yes here to enable LLCC slice driver.
 
+config QCOM_KRAIT_L2_CACHE
+	tristate "Qualcomm Krait L2 cache scaling"
+	depends on ARCH_QCOM && ARM || COMPILE_TEST
+	select INTERCONNECT
+	select INTERCONNECT_CLK
+	default ARM_QCOM_CPUFREQ_NVMEM
+	help
+	  The driver for scaling the L2 cache frequency on Qualcomm Krait platforms.
+
 config QCOM_KRYO_L2_ACCESSORS
 	bool
 	depends on (ARCH_QCOM || COMPILE_TEST) && ARM64
diff --git a/drivers/soc/qcom/Makefile b/drivers/soc/qcom/Makefile
index 99114c71092b..cdd1cc96e9f9 100644
--- a/drivers/soc/qcom/Makefile
+++ b/drivers/soc/qcom/Makefile
@@ -31,6 +31,7 @@ obj-$(CONFIG_QCOM_APR) += apr.o
 obj-$(CONFIG_QCOM_LLCC) += llcc-qcom.o
 obj-$(CONFIG_QCOM_RPMHPD) += rpmhpd.o
 obj-$(CONFIG_QCOM_RPMPD) += rpmpd.o
+obj-$(CONFIG_QCOM_KRAIT_L2_CACHE) += krait-l2-cache.o
 obj-$(CONFIG_QCOM_KRYO_L2_ACCESSORS) +=	kryo-l2-accessors.o
 obj-$(CONFIG_QCOM_ICC_BWMON)	+= icc-bwmon.o
 qcom_ice-objs			+= ice.o
diff --git a/drivers/soc/qcom/krait-l2-cache.c b/drivers/soc/qcom/krait-l2-cache.c
new file mode 100644
index 000000000000..af9e7b955daf
--- /dev/null
+++ b/drivers/soc/qcom/krait-l2-cache.c
@@ -0,0 +1,190 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2023, Linaro Ltd.
+ */
+
+#include <linux/clk.h>
+#include <linux/interconnect-clk.h>
+#include <linux/interconnect-provider.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+#include <linux/pm_opp.h>
+#include <linux/regulator/consumer.h>
+
+#include <dt-bindings/soc/qcom,krait-l2-cache.h>
+
+/* Random ID that doesn't clash with main qnoc and OSM */
+#define L2_MASTER_NODE 2000
+
+/* vdd-mem and vdd-dig */
+#define NUM_SUPPLIES 2
+static int krait_l2_config_regulators(struct device *dev,
+				      struct dev_pm_opp *old_opp,
+				      struct dev_pm_opp *new_opp,
+				      struct regulator **regulators,
+				      unsigned int count)
+{
+	struct dev_pm_opp_supply supplies[NUM_SUPPLIES];
+	unsigned long old_freq, freq;
+	unsigned int i;
+	int ret;
+
+	if (WARN_ON_ONCE(count != NUM_SUPPLIES))
+		return -EINVAL;
+
+	ret = dev_pm_opp_get_supplies(new_opp, supplies);
+	if (WARN_ON(ret))
+		return ret;
+
+	old_freq = dev_pm_opp_get_freq(old_opp);
+	freq = dev_pm_opp_get_freq(new_opp);
+
+	WARN_ON(!old_freq || !freq);
+	if (freq > old_freq) {
+		for (i = 0; i < count; i++) {
+			struct regulator *reg = regulators[i];
+			struct dev_pm_opp_supply *supply = &supplies[i];
+
+			dev_dbg(dev, "%s: voltages (mV): %lu %lu %lu\n", __func__,
+				supply->u_volt_min, supply->u_volt, supply->u_volt_max);
+
+			ret = regulator_set_voltage_triplet(reg,
+							    supply->u_volt_min,
+							    supply->u_volt,
+							    supply->u_volt_max);
+			if (ret) {
+				dev_err(dev, "%s: failed to set voltage (%lu %lu %lu mV): %d\n",
+					__func__, supply->u_volt_min, supply->u_volt,
+					supply->u_volt_max, ret);
+				goto restore_backwards;
+			}
+		}
+	} else {
+		for (i = count; i > 0; i--) {
+			struct regulator *reg = regulators[i - 1];
+			struct dev_pm_opp_supply *supply = &supplies[i - 1];
+
+			dev_dbg(dev, "%s: voltages (mV): %lu %lu %lu\n", __func__,
+				supply->u_volt_min, supply->u_volt, supply->u_volt_max);
+
+			ret = regulator_set_voltage_triplet(reg,
+							    supply->u_volt_min,
+							    supply->u_volt,
+							    supply->u_volt_max);
+			if (ret) {
+				dev_err(dev, "%s: failed to set voltage (%lu %lu %lu mV): %d\n",
+					__func__, supply->u_volt_min, supply->u_volt,
+					supply->u_volt_max, ret);
+				goto restore_forward;
+			}
+		}
+	}
+
+	return 0;
+
+restore_backwards:
+
+	dev_pm_opp_get_supplies(old_opp, supplies);
+
+	for (; i > 0; i--) {
+		struct regulator *reg = regulators[i - 1];
+		struct dev_pm_opp_supply *supply = &supplies[i - 1];
+
+		dev_dbg(dev, "%s: voltages (mV): %lu %lu %lu\n", __func__,
+			supply->u_volt_min, supply->u_volt, supply->u_volt_max);
+
+		regulator_set_voltage_triplet(reg,
+					      supply->u_volt_min,
+					      supply->u_volt,
+					      supply->u_volt_max);
+	}
+
+	return ret;
+
+restore_forward:
+
+	dev_pm_opp_get_supplies(old_opp, supplies);
+
+	for ( ; i < count; i++) {
+		struct regulator *reg = regulators[i];
+		struct dev_pm_opp_supply *supply = &supplies[i];
+
+		dev_dbg(dev, "%s: voltages (mV): %lu %lu %lu\n", __func__,
+			supply->u_volt_min, supply->u_volt, supply->u_volt_max);
+
+		regulator_set_voltage_triplet(reg,
+					      supply->u_volt_min,
+					      supply->u_volt,
+					      supply->u_volt_max);
+	}
+
+	return ret;
+}
+
+static int krait_l2_probe(struct platform_device *pdev)
+{
+	struct dev_pm_opp_config krait_l2_cfg = {
+		.clk_names = (const char * const[]) { NULL, NULL },
+		.config_regulators = krait_l2_config_regulators,
+		.regulator_names = (const char * const[]) { "vdd-mem", "vdd-dig", NULL },
+	};
+	struct icc_clk_data data[] = {
+		{ .name = "l2", .opp = true},
+	};
+
+	struct device *dev = &pdev->dev;
+	struct icc_provider *provider;
+	struct clk *clk;
+	int ret;
+
+	clk = devm_clk_get(dev, NULL);
+	if (IS_ERR(clk))
+		return PTR_ERR(clk);
+
+	ret = devm_pm_opp_set_config(dev, &krait_l2_cfg);
+	if (ret)
+		return ret;
+
+	ret = devm_pm_opp_of_add_table(dev);
+	if (ret)
+		return ret;
+
+	data[0].clk = clk;
+	provider = icc_clk_register(dev, L2_MASTER_NODE, ARRAY_SIZE(data), data);
+	if (IS_ERR(provider))
+		return PTR_ERR(provider);
+
+	platform_set_drvdata(pdev, provider);
+
+	return 0;
+}
+
+static int krait_l2_remove(struct platform_device *pdev)
+{
+	struct icc_provider *provider = platform_get_drvdata(pdev);
+
+	icc_clk_unregister(provider);
+
+	return 0;
+}
+
+static const struct of_device_id krait_l2_match_table[] = {
+	{ .compatible = "qcom,krait-l2-cache" },
+	{}
+};
+MODULE_DEVICE_TABLE(of, krait_l2_match_table);
+
+static struct platform_driver krait_l2_driver = {
+	.probe = krait_l2_probe,
+	.remove = krait_l2_remove,
+	.driver = {
+		.name = "qcom-krait-l2",
+		.of_match_table = krait_l2_match_table,
+		.sync_state = icc_sync_state,
+	},
+};
+
+module_platform_driver(krait_l2_driver);
+
+MODULE_DESCRIPTION("Qualcomm Krait L2 scaling driver");
+MODULE_LICENSE("GPL v2");
-- 
2.39.2

[PATCH v2 14/26] ARM: dts: qcom: apq8064: rename SAW nodes to power-manager

[Dmitry Baryshkov]

Per the power-domain.yaml, the power-controller node name is reserved
for power-domain providers. Rename SAW2 nodes to 'power-manager', the
name which is suggested by qcom,spm.yaml

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
 arch/arm/boot/dts/qcom/qcom-apq8064.dtsi | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi
index d2289205ff81..471eeca6a589 100644
--- a/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi
+++ b/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi
@@ -422,25 +422,25 @@ acc3: clock-controller@20b8000 {
 			#clock-cells = <0>;
 		};
 
-		saw0: power-controller@2089000 {
+		saw0: power-manager@2089000 {
 			compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
 			reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
 			regulator;
 		};
 
-		saw1: power-controller@2099000 {
+		saw1: power-manager@2099000 {
 			compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
 			reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
 			regulator;
 		};
 
-		saw2: power-controller@20a9000 {
+		saw2: power-manager@20a9000 {
 			compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
 			reg = <0x020a9000 0x1000>, <0x02009000 0x1000>;
 			regulator;
 		};
 
-		saw3: power-controller@20b9000 {
+		saw3: power-manager@20b9000 {
 			compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
 			reg = <0x020b9000 0x1000>, <0x02009000 0x1000>;
 			regulator;
-- 
2.39.2

[PATCH v2 15/26] ARM: dts: qcom: apq8064: declare SAW2 regulators

[Dmitry Baryshkov]

The SAW2 (SPM and AVS Wrapper) among other things is yet another way to
handle CPU-related PMIC regulators. Provide a way to control voltage of
these regulators.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
 arch/arm/boot/dts/qcom/qcom-apq8064.dtsi | 24 ++++++++++++++++++++----
 1 file changed, 20 insertions(+), 4 deletions(-)

diff --git a/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi
index 471eeca6a589..1eb6d752ebae 100644
--- a/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi
+++ b/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi
@@ -425,25 +425,41 @@ acc3: clock-controller@20b8000 {
 		saw0: power-manager@2089000 {
 			compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
 			reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
-			regulator;
+
+			saw0_vreg: regulator {
+				regulator-min-microvolt = <850000>;
+				regulator-max-microvolt = <1300000>;
+			};
 		};
 
 		saw1: power-manager@2099000 {
 			compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
 			reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
-			regulator;
+
+			saw1_vreg: regulator {
+				regulator-min-microvolt = <850000>;
+				regulator-max-microvolt = <1300000>;
+			};
 		};
 
 		saw2: power-manager@20a9000 {
 			compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
 			reg = <0x020a9000 0x1000>, <0x02009000 0x1000>;
-			regulator;
+
+			saw2_vreg: regulator {
+				regulator-min-microvolt = <850000>;
+				regulator-max-microvolt = <1300000>;
+			};
 		};
 
 		saw3: power-manager@20b9000 {
 			compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
 			reg = <0x020b9000 0x1000>, <0x02009000 0x1000>;
-			regulator;
+
+			saw3_vreg: regulator {
+				regulator-min-microvolt = <850000>;
+				regulator-max-microvolt = <1300000>;
+			};
 		};
 
 		sps_sic_non_secure: sps-sic-non-secure@12100000 {
-- 
2.39.2

[PATCH v2 16/26] ARM: dts: qcom: apq8064: add L2 cache scaling

[Dmitry Baryshkov]

Populate L2 cache node with clock, supplies and OPP information to
facilitate scaling L2 frequency.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
 arch/arm/boot/dts/qcom/qcom-apq8064.dtsi | 101 ++++++++++++++++++++++-
 1 file changed, 100 insertions(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi
index 1eb6d752ebae..ac07170c702f 100644
--- a/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi
+++ b/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi
@@ -81,9 +81,108 @@ CPU3: cpu@3 {
 		};
 
 		L2: l2-cache {
-			compatible = "cache";
+			compatible = "qcom,krait-l2-cache", "cache";
 			cache-level = <2>;
 			cache-unified;
+			vdd-mem-supply = <&pm8921_l24>;
+			vdd-dig-supply = <&pm8921_s3>;
+			clocks = <&kraitcc KRAIT_L2>;
+			#interconnect-cells = <1>;
+			operating-points-v2 = <&l2_opp_table>;
+
+			l2_opp_table: opp-table-l2 {
+				compatible = "operating-points-v2";
+
+				opp-384000000 {
+					opp-hz = /bits/ 64 <384000000>;
+					opp-microvolt = <1050000 1050000 1150000>,
+							<950000 950000 1150000>;
+				};
+
+				opp-432000000 {
+					opp-hz = /bits/ 64 <432000000>;
+					opp-microvolt = <1050000 1050000 1150000>,
+							<1050000 1050000 1150000>;
+				};
+
+				opp-486000000 {
+					opp-hz = /bits/ 64 <486000000>;
+					opp-microvolt = <1050000 1050000 1150000>,
+							<1050000 1050000 1150000>;
+				};
+
+				opp-540000000 {
+					opp-hz = /bits/ 64 <540000000>;
+					opp-microvolt = <1050000 1050000 1150000>,
+							<1050000 1050000 1150000>;
+				};
+
+				opp-594000000 {
+					opp-hz = /bits/ 64 <594000000>;
+					opp-microvolt = <1050000 1050000 1150000>,
+							<1050000 1050000 1150000>;
+				};
+
+				opp-648000000 {
+					opp-hz = /bits/ 64 <648000000>;
+					opp-microvolt = <1050000 1050000 1150000>,
+							<1050000 1050000 1150000>;
+				};
+
+				opp-702000000 {
+					opp-hz = /bits/ 64 <702000000>;
+					opp-microvolt = <1150000 1150000 1150000>,
+							<1150000 1150000 1150000>;
+				};
+
+				opp-756000000 {
+					opp-hz = /bits/ 64 <756000000>;
+					opp-microvolt = <1150000 1150000 1150000>,
+							<1150000 1150000 1150000>;
+				};
+
+				opp-810000000 {
+					opp-hz = /bits/ 64 <810000000>;
+					opp-microvolt = <1150000 1150000 1150000>,
+							<1150000 1150000 1150000>;
+				};
+
+				opp-864000000 {
+					opp-hz = /bits/ 64 <864000000>;
+					opp-microvolt = <1150000 1150000 1150000>,
+							<1150000 1150000 1150000>;
+				};
+
+				opp-918000000 {
+					opp-hz = /bits/ 64 <918000000>;
+					opp-microvolt = <1150000 1150000 1150000>,
+							<1150000 1150000 1150000>;
+				};
+
+				opp-972000000 {
+					opp-hz = /bits/ 64 <972000000>;
+					opp-microvolt = <1150000 1150000 1150000>,
+							<1150000 1150000 1150000>;
+				};
+
+				opp-1026000000 {
+					opp-hz = /bits/ 64 <1026000000>;
+					opp-microvolt = <1150000 1150000 1150000>,
+							<1150000 1150000 1150000>;
+				};
+
+				opp-1080000000 {
+					opp-hz = /bits/ 64 <1080000000>;
+					opp-microvolt = <1150000 1150000 1150000>,
+							<1150000 1150000 1150000>;
+				};
+
+				opp-1134000000 {
+					opp-hz = /bits/ 64 <1134000000>;
+					opp-microvolt = <1150000 1150000 1150000>,
+							<1150000 1150000 1150000>;
+				};
+			};
 		};
 
 		idle-states {
-- 
2.39.2

[PATCH v2 17/26] ARM: dts: qcom: apq8064: add simple CPUFreq support

[Dmitry Baryshkov]

Declare CPU frequency-scaling properties. Each CPU has its own clock,
how all CPUs have the same OPP table. Voltage scaling is not (yet)
enabled with this patch. It will be enabled later.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
 arch/arm/boot/dts/qcom/qcom-apq8064.dtsi | 170 +++++++++++++++++++++++
 1 file changed, 170 insertions(+)

diff --git a/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi
index ac07170c702f..e4d2fd48d843 100644
--- a/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi
+++ b/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi
@@ -2,11 +2,13 @@
 /dts-v1/;
 
 #include <dt-bindings/clock/qcom,gcc-msm8960.h>
+#include <dt-bindings/clock/qcom,krait-cc.h>
 #include <dt-bindings/clock/qcom,lcc-msm8960.h>
 #include <dt-bindings/reset/qcom,gcc-msm8960.h>
 #include <dt-bindings/clock/qcom,mmcc-msm8960.h>
 #include <dt-bindings/clock/qcom,rpmcc.h>
 #include <dt-bindings/soc/qcom,gsbi.h>
+#include <dt-bindings/soc/qcom,krait-l2-cache.h>
 #include <dt-bindings/interrupt-controller/irq.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 / {
@@ -45,6 +47,12 @@ CPU0: cpu@0 {
 			qcom,acc = <&acc0>;
 			qcom,saw = <&saw0>;
 			cpu-idle-states = <&CPU_SPC>;
+			clocks = <&kraitcc KRAIT_CPU_0>;
+			clock-names = "cpu";
+			clock-latency = <100000>;
+			interconnects = <&L2 MASTER_KRAIT_L2 &L2 SLAVE_KRAIT_L2>;
+			operating-points-v2 = <&cpu_opp_table>;
+			#cooling-cells = <2>;
 		};
 
 		CPU1: cpu@1 {
@@ -56,6 +64,12 @@ CPU1: cpu@1 {
 			qcom,acc = <&acc1>;
 			qcom,saw = <&saw1>;
 			cpu-idle-states = <&CPU_SPC>;
+			clocks = <&kraitcc KRAIT_CPU_1>;
+			clock-names = "cpu";
+			clock-latency = <100000>;
+			interconnects = <&L2 MASTER_KRAIT_L2 &L2 SLAVE_KRAIT_L2>;
+			operating-points-v2 = <&cpu_opp_table>;
+			#cooling-cells = <2>;
 		};
 
 		CPU2: cpu@2 {
@@ -67,6 +81,12 @@ CPU2: cpu@2 {
 			qcom,acc = <&acc2>;
 			qcom,saw = <&saw2>;
 			cpu-idle-states = <&CPU_SPC>;
+			clocks = <&kraitcc KRAIT_CPU_2>;
+			clock-names = "cpu";
+			clock-latency = <100000>;
+			interconnects = <&L2 MASTER_KRAIT_L2 &L2 SLAVE_KRAIT_L2>;
+			operating-points-v2 = <&cpu_opp_table>;
+			#cooling-cells = <2>;
 		};
 
 		CPU3: cpu@3 {
@@ -78,6 +98,12 @@ CPU3: cpu@3 {
 			qcom,acc = <&acc3>;
 			qcom,saw = <&saw3>;
 			cpu-idle-states = <&CPU_SPC>;
+			clocks = <&kraitcc KRAIT_CPU_3>;
+			clock-names = "cpu";
+			clock-latency = <100000>;
+			interconnects = <&L2 MASTER_KRAIT_L2 &L2 SLAVE_KRAIT_L2>;
+			operating-points-v2 = <&cpu_opp_table>;
+			#cooling-cells = <2>;
 		};
 
 		L2: l2-cache {
@@ -196,6 +222,121 @@ CPU_SPC: spc {
 		};
 	};
 
+        cpu_opp_table: opp-table-cpu {
+		compatible = "operating-points-v2-krait-cpu";
+		nvmem-cells = <&speedbin_efuse>;
+
+		/*
+		 * Voltage thresholds are <target min max>
+		 */
+		opp-384000000 {
+			opp-hz = /bits/ 64 <384000000>;
+			opp-peak-kBps = <384000>;
+			opp-supported-hw = <0x4007>;
+			/*
+			 * higher latency as it requires switching between
+			 * clock sources
+			 */
+			clock-latency-ns = <244144>;
+		};
+
+		opp-486000000 {
+			opp-hz = /bits/ 64 <486000000>;
+			opp-peak-kBps = <648000>;
+			opp-supported-hw = <0x4007>;
+		};
+
+		opp-594000000 {
+			opp-hz = /bits/ 64 <594000000>;
+			opp-peak-kBps = <648000>;
+			opp-supported-hw = <0x4007>;
+		};
+
+		opp-702000000 {
+			opp-hz = /bits/ 64 <702000000>;
+			opp-peak-kBps = <648000>;
+			opp-supported-hw = <0x4007>;
+		};
+
+		opp-810000000 {
+			opp-hz = /bits/ 64 <810000000>;
+			opp-peak-kBps = <648000>;
+			opp-supported-hw = <0x4007>;
+		};
+
+		opp-918000000 {
+			opp-hz = /bits/ 64 <918000000>;
+			opp-peak-kBps = <648000>;
+			opp-supported-hw = <0x4007>;
+		};
+
+		opp-1026000000 {
+			opp-hz = /bits/ 64 <1026000000>;
+			opp-peak-kBps = <648000>;
+			opp-supported-hw = <0x4007>;
+		};
+
+		opp-1134000000 {
+			opp-hz = /bits/ 64 <1134000000>;
+			opp-peak-kBps = <1134000>;
+			opp-supported-hw = <0x4007>;
+		};
+
+		opp-1242000000 {
+			opp-hz = /bits/ 64 <1242000000>;
+			opp-peak-kBps = <1134000>;
+			opp-supported-hw = <0x4007>;
+		};
+
+		opp-1350000000 {
+			opp-hz = /bits/ 64 <1350000000>;
+			opp-peak-kBps = <1134000>;
+			opp-supported-hw = <0x4007>;
+		};
+
+		opp-1458000000 {
+			opp-hz = /bits/ 64 <1458000000>;
+			opp-peak-kBps = <1134000>;
+			opp-supported-hw = <0x4007>;
+		};
+
+		opp-1512000000 {
+			opp-hz = /bits/ 64 <1512000000>;
+			opp-peak-kBps = <1134000>;
+			opp-supported-hw = <0x4001>;
+		};
+
+		opp-1566000000 {
+			opp-hz = /bits/ 64 <1566000000>;
+			opp-peak-kBps = <1134000>;
+			opp-supported-hw = <0x06>;
+		};
+
+		opp-1674000000 {
+			opp-hz = /bits/ 64 <1674000000>;
+			opp-peak-kBps = <1134000>;
+			opp-supported-hw = <0x06>;
+		};
+
+		opp-1728000000 {
+			opp-hz = /bits/ 64 <1728000000>;
+			opp-peak-kBps = <1134000>;
+			opp-supported-hw = <0x02>;
+		};
+
+		opp-1782000000 {
+			opp-hz = /bits/ 64 <1782000000>;
+			opp-peak-kBps = <1134000>;
+			opp-supported-hw = <0x04>;
+		};
+
+		opp-1890000000 {
+			opp-hz = /bits/ 64 <1890000000>;
+			opp-peak-kBps = <1134000>;
+			opp-supported-hw = <0x04>;
+		};
+	};
+
 	memory@0 {
 		device_type = "memory";
 		reg = <0x0 0x0>;
@@ -312,6 +453,32 @@ sleep_clk: sleep_clk {
 		};
 	};
 
+	kraitcc: clock-controller {
+		compatible = "qcom,krait-cc-v1";
+		clocks = <&gcc PLL9>, /* hfpll0 */
+			 <&gcc PLL10>, /* hfpll1 */
+			 <&gcc PLL16>, /* hfpll2 */
+			 <&gcc PLL17>, /* hfpll3 */
+			 <&gcc PLL12>, /* hfpll_l2 */
+			 <&acc0>,
+			 <&acc1>,
+			 <&acc2>,
+			 <&acc3>,
+			 <&l2cc>;
+		clock-names = "hfpll0",
+			      "hfpll1",
+			      "hfpll2",
+			      "hfpll3",
+			      "hfpll_l2",
+			      "acpu0_aux",
+			      "acpu1_aux",
+			      "acpu2_aux",
+			      "acpu3_aux",
+			      "acpu_l2_aux";
+		#clock-cells = <1>;
+		#interconnect-cells = <1>;
+	};
+
 	sfpb_mutex: hwmutex {
 		compatible = "qcom,sfpb-mutex";
 		syscon = <&sfpb_wrapper_mutex 0x604 0x4>;
@@ -933,6 +1100,9 @@ qfprom: qfprom@700000 {
 			#address-cells = <1>;
 			#size-cells = <1>;
 			ranges;
+			speedbin_efuse: speedbin@c0 {
+				reg = <0x0c0 0x4>;
+			};
 			tsens_calib: calib@404 {
 				reg = <0x404 0x10>;
 			};
-- 
2.39.2

[PATCH v2 18/26] ARM: dts: qcom: apq8064: provide voltage scaling tables

[Dmitry Baryshkov]

APQ8064 has 4 speed bins, each of them having from 4 to 6 categorization
kinds. Provide tables necessary to handle voltage scaling on this SoC.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
 arch/arm/boot/dts/qcom/qcom-apq8064.dtsi | 339 +++++++++++++++++++++++
 1 file changed, 339 insertions(+)

diff --git a/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi
index e4d2fd48d843..b97d88517805 100644
--- a/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi
+++ b/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi
@@ -50,6 +50,7 @@ CPU0: cpu@0 {
 			clocks = <&kraitcc KRAIT_CPU_0>;
 			clock-names = "cpu";
 			clock-latency = <100000>;
+			vdd-core-supply = <&saw0_vreg>;
 			interconnects = <&L2 MASTER_KRAIT_L2 &L2 SLAVE_KRAIT_L2>;
 			operating-points-v2 = <&cpu_opp_table>;
 			#cooling-cells = <2>;
@@ -67,6 +68,7 @@ CPU1: cpu@1 {
 			clocks = <&kraitcc KRAIT_CPU_1>;
 			clock-names = "cpu";
 			clock-latency = <100000>;
+			vdd-core-supply = <&saw1_vreg>;
 			interconnects = <&L2 MASTER_KRAIT_L2 &L2 SLAVE_KRAIT_L2>;
 			operating-points-v2 = <&cpu_opp_table>;
 			#cooling-cells = <2>;
@@ -84,6 +86,7 @@ CPU2: cpu@2 {
 			clocks = <&kraitcc KRAIT_CPU_2>;
 			clock-names = "cpu";
 			clock-latency = <100000>;
+			vdd-core-supply = <&saw2_vreg>;
 			interconnects = <&L2 MASTER_KRAIT_L2 &L2 SLAVE_KRAIT_L2>;
 			operating-points-v2 = <&cpu_opp_table>;
 			#cooling-cells = <2>;
@@ -101,6 +104,7 @@ CPU3: cpu@3 {
 			clocks = <&kraitcc KRAIT_CPU_3>;
 			clock-names = "cpu";
 			clock-latency = <100000>;
+			vdd-core-supply = <&saw3_vreg>;
 			interconnects = <&L2 MASTER_KRAIT_L2 &L2 SLAVE_KRAIT_L2>;
 			operating-points-v2 = <&cpu_opp_table>;
 			#cooling-cells = <2>;
@@ -232,6 +236,31 @@ cpu_opp_table: opp-table-cpu {
 		opp-384000000 {
 			opp-hz = /bits/ 64 <384000000>;
 			opp-peak-kBps = <384000>;
+			opp-microvolt-speed0-pvs0 = <950000 950000 975000>;
+			opp-microvolt-speed0-pvs1 = <925000 900000 950000>;
+			opp-microvolt-speed0-pvs3 = <875000 850000 900000>;
+			opp-microvolt-speed0-pvs4 = <875000 850000 900000>;
+			opp-microvolt-speed1-pvs0 = <950000 950000 975000>;
+			opp-microvolt-speed1-pvs1 = <975000 950000 1000000>;
+			opp-microvolt-speed1-pvs2 = <950000 925000 975000>;
+			opp-microvolt-speed1-pvs3 = <925000 900000 950000>;
+			opp-microvolt-speed1-pvs4 = <900000 875000 925000>;
+			opp-microvolt-speed1-pvs5 = <900000 875000 925000>;
+			opp-microvolt-speed1-pvs6 = <900000 875000 925000>;
+			opp-microvolt-speed2-pvs0 = <950000 950000 975000>;
+			opp-microvolt-speed2-pvs1 = <925000 925000 925000>;
+			opp-microvolt-speed2-pvs2 = <925000 900000 950000>;
+			opp-microvolt-speed2-pvs3 = <925000 900000 950000>;
+			opp-microvolt-speed2-pvs4 = <900000 875000 925000>;
+			opp-microvolt-speed2-pvs5 = <900000 875000 925000>;
+			opp-microvolt-speed2-pvs6 = <900000 875000 925000>;
+			opp-microvolt-speed14-pvs0 = <950000 950000 975000>;
+			opp-microvolt-speed14-pvs1 = <975000 950000 1000000>;
+			opp-microvolt-speed14-pvs2 = <950000 925000 975000>;
+			opp-microvolt-speed14-pvs3 = <925000 900000 950000>;
+			opp-microvolt-speed14-pvs4 = <900000 875000 925000>;
+			opp-microvolt-speed14-pvs5 = <875000 875000 875000>;
+			opp-microvolt-speed14-pvs6 = <900000 875000 925000>;
 			opp-supported-hw = <0x4007>;
 			/*
 			 * higher latency as it requires switching between
@@ -243,96 +272,406 @@ opp-384000000 {
 		opp-486000000 {
 			opp-hz = /bits/ 64 <486000000>;
 			opp-peak-kBps = <648000>;
+			opp-microvolt-speed0-pvs0 = <975000 975000 1000000>;
+			opp-microvolt-speed0-pvs1 = <950000 925000 975000>;
+			opp-microvolt-speed0-pvs3 = <900000 875000 925000>;
+			opp-microvolt-speed0-pvs4 = <900000 875000 925000>;
+			opp-microvolt-speed1-pvs0 = <950000 950000 975000>;
+			opp-microvolt-speed1-pvs1 = <975000 950000 1000000>;
+			opp-microvolt-speed1-pvs2 = <950000 925000 975000>;
+			opp-microvolt-speed1-pvs3 = <925000 900000 950000>;
+			opp-microvolt-speed1-pvs4 = <900000 875000 925000>;
+			opp-microvolt-speed1-pvs5 = <900000 875000 925000>;
+			opp-microvolt-speed1-pvs6 = <900000 875000 925000>;
+			opp-microvolt-speed2-pvs0 = <950000 950000 975000>;
+			opp-microvolt-speed2-pvs1 = <925000 925000 925000>;
+			opp-microvolt-speed2-pvs2 = <925000 900000 950000>;
+			opp-microvolt-speed2-pvs3 = <925000 900000 950000>;
+			opp-microvolt-speed2-pvs4 = <900000 875000 925000>;
+			opp-microvolt-speed2-pvs5 = <900000 875000 925000>;
+			opp-microvolt-speed2-pvs6 = <900000 875000 925000>;
+			opp-microvolt-speed14-pvs0 = <950000 950000 975000>;
+			opp-microvolt-speed14-pvs1 = <975000 950000 1000000>;
+			opp-microvolt-speed14-pvs2 = <950000 925000 975000>;
+			opp-microvolt-speed14-pvs3 = <925000 900000 950000>;
+			opp-microvolt-speed14-pvs4 = <900000 875000 925000>;
+			opp-microvolt-speed14-pvs5 = <875000 875000 875000>;
+			opp-microvolt-speed14-pvs6 = <875000 875000 875000>;
 			opp-supported-hw = <0x4007>;
 		};
 
 		opp-594000000 {
 			opp-hz = /bits/ 64 <594000000>;
 			opp-peak-kBps = <648000>;
+			opp-microvolt-speed0-pvs0 = <1000000 1000000 1025000>;
+			opp-microvolt-speed0-pvs1 = <975000 950000 1000000>;
+			opp-microvolt-speed0-pvs3 = <925000 900000 950000>;
+			opp-microvolt-speed0-pvs4 = <925000 900000 950000>;
+			opp-microvolt-speed1-pvs0 = <950000 950000 975000>;
+			opp-microvolt-speed1-pvs1 = <975000 950000 1000000>;
+			opp-microvolt-speed1-pvs2 = <950000 925000 975000>;
+			opp-microvolt-speed1-pvs3 = <925000 900000 950000>;
+			opp-microvolt-speed1-pvs4 = <900000 875000 925000>;
+			opp-microvolt-speed1-pvs5 = <900000 875000 925000>;
+			opp-microvolt-speed1-pvs6 = <900000 875000 925000>;
+			opp-microvolt-speed2-pvs0 = <950000 950000 975000>;
+			opp-microvolt-speed2-pvs1 = <925000 925000 925000>;
+			opp-microvolt-speed2-pvs2 = <925000 900000 950000>;
+			opp-microvolt-speed2-pvs3 = <925000 900000 950000>;
+			opp-microvolt-speed2-pvs4 = <900000 875000 925000>;
+			opp-microvolt-speed2-pvs5 = <900000 875000 925000>;
+			opp-microvolt-speed2-pvs6 = <900000 875000 925000>;
+			opp-microvolt-speed14-pvs0 = <950000 950000 975000>;
+			opp-microvolt-speed14-pvs1 = <975000 950000 1000000>;
+			opp-microvolt-speed14-pvs2 = <950000 925000 975000>;
+			opp-microvolt-speed14-pvs3 = <925000 900000 950000>;
+			opp-microvolt-speed14-pvs4 = <900000 875000 925000>;
+			opp-microvolt-speed14-pvs5 = <875000 875000 875000>;
+			opp-microvolt-speed14-pvs6 = <900000 875000 925000>;
 			opp-supported-hw = <0x4007>;
 		};
 
 		opp-702000000 {
 			opp-hz = /bits/ 64 <702000000>;
 			opp-peak-kBps = <648000>;
+			opp-microvolt-speed0-pvs0 = <1025000 1025000 1050000>;
+			opp-microvolt-speed0-pvs1 = <1000000 975000 1025000>;
+			opp-microvolt-speed0-pvs3 = <950000 925000 975000>;
+			opp-microvolt-speed0-pvs4 = <950000 925000 975000>;
+			opp-microvolt-speed1-pvs0 = <962500 962500 987500>;
+			opp-microvolt-speed1-pvs1 = <987500 962500 1012500>;
+			opp-microvolt-speed1-pvs2 = <950000 925000 975000>;
+			opp-microvolt-speed1-pvs3 = <925000 900000 950000>;
+			opp-microvolt-speed1-pvs4 = <900000 875000 925000>;
+			opp-microvolt-speed1-pvs5 = <900000 875000 925000>;
+			opp-microvolt-speed1-pvs6 = <900000 875000 925000>;
+			opp-microvolt-speed2-pvs0 = <950000 950000 975000>;
+			opp-microvolt-speed2-pvs1 = <925000 925000 925000>;
+			opp-microvolt-speed2-pvs2 = <925000 900000 950000>;
+			opp-microvolt-speed2-pvs3 = <925000 900000 950000>;
+			opp-microvolt-speed2-pvs4 = <900000 875000 925000>;
+			opp-microvolt-speed2-pvs5 = <900000 875000 925000>;
+			opp-microvolt-speed2-pvs6 = <900000 875000 925000>;
+			opp-microvolt-speed14-pvs0 = <962500 962500 987500>;
+			opp-microvolt-speed14-pvs1 = <987500 962500 1012500>;
+			opp-microvolt-speed14-pvs2 = <950000 925000 975000>;
+			opp-microvolt-speed14-pvs3 = <925000 900000 950000>;
+			opp-microvolt-speed14-pvs4 = <900000 875000 925000>;
+			opp-microvolt-speed14-pvs5 = <875000 875000 875000>;
+			opp-microvolt-speed14-pvs6 = <900000 875000 925000>;
 			opp-supported-hw = <0x4007>;
 		};
 
 		opp-810000000 {
 			opp-hz = /bits/ 64 <810000000>;
 			opp-peak-kBps = <648000>;
+			opp-microvolt-speed0-pvs0 = <1075000 1075000 1100000>;
+			opp-microvolt-speed0-pvs1 = <1050000 1025000 1075000>;
+			opp-microvolt-speed0-pvs3 = <1000000 975000 1025000>;
+			opp-microvolt-speed0-pvs4 = <987500 962500 1012500>;
+			opp-microvolt-speed1-pvs0 = <1000000 1000000 1025000>;
+			opp-microvolt-speed1-pvs1 = <1000000 975000 1025000>;
+			opp-microvolt-speed1-pvs2 = <962500 937500 987500>;
+			opp-microvolt-speed1-pvs3 = <925000 900000 950000>;
+			opp-microvolt-speed1-pvs4 = <912500 887500 937500>;
+			opp-microvolt-speed1-pvs5 = <912500 887500 937500>;
+			opp-microvolt-speed1-pvs6 = <912500 887500 937500>;
+			opp-microvolt-speed2-pvs0 = <962500 962500 987500>;
+			opp-microvolt-speed2-pvs1 = <937500 937500 937500>;
+			opp-microvolt-speed2-pvs2 = <937500 912500 962500>;
+			opp-microvolt-speed2-pvs3 = <925000 900000 950000>;
+			opp-microvolt-speed2-pvs4 = <912500 887500 937500>;
+			opp-microvolt-speed2-pvs5 = <912500 887500 937500>;
+			opp-microvolt-speed2-pvs6 = <912500 887500 937500>;
+			opp-microvolt-speed14-pvs0 = <1000000 1000000 1025000>;
+			opp-microvolt-speed14-pvs1 = <1000000 975000 1025000>;
+			opp-microvolt-speed14-pvs2 = <962500 937500 987500>;
+			opp-microvolt-speed14-pvs3 = <925000 900000 950000>;
+			opp-microvolt-speed14-pvs4 = <912500 887500 937500>;
+			opp-microvolt-speed14-pvs5 = <887500 887500 887500>;
+			opp-microvolt-speed14-pvs6 = <912500 887500 937500>;
 			opp-supported-hw = <0x4007>;
 		};
 
 		opp-918000000 {
 			opp-hz = /bits/ 64 <918000000>;
 			opp-peak-kBps = <648000>;
+			opp-microvolt-speed0-pvs0 = <1100000 1100000 1125000>;
+			opp-microvolt-speed0-pvs1 = <1075000 1050000 1100000>;
+			opp-microvolt-speed0-pvs3 = <1025000 1000000 1050000>;
+			opp-microvolt-speed0-pvs4 = <1000000 975000 1025000>;
+			opp-microvolt-speed1-pvs0 = <1025000 1025000 1050000>;
+			opp-microvolt-speed1-pvs1 = <1025000 1000000 1050000>;
+			opp-microvolt-speed1-pvs2 = <975000 950000 1000000>;
+			opp-microvolt-speed1-pvs3 = <950000 925000 975000>;
+			opp-microvolt-speed1-pvs4 = <925000 900000 950000>;
+			opp-microvolt-speed1-pvs5 = <925000 900000 950000>;
+			opp-microvolt-speed1-pvs6 = <925000 900000 950000>;
+			opp-microvolt-speed2-pvs0 = <975000 975000 1000000>;
+			opp-microvolt-speed2-pvs1 = <950000 950000 950000>;
+			opp-microvolt-speed2-pvs2 = <950000 925000 975000>;
+			opp-microvolt-speed2-pvs3 = <937500 912500 962500>;
+			opp-microvolt-speed3-pvs4 = <925000 900000 950000>;
+			opp-microvolt-speed2-pvs5 = <925000 900000 950000>;
+			opp-microvolt-speed2-pvs6 = <925000 900000 950000>;
+			opp-microvolt-speed14-pvs0 = <1025000 1025000 1050000>;
+			opp-microvolt-speed14-pvs1 = <1025000 1000000 1050000>;
+			opp-microvolt-speed14-pvs2 = <975000 950000 1000000>;
+			opp-microvolt-speed14-pvs3 = <950000 925000 975000>;
+			opp-microvolt-speed14-pvs4 = <925000 900000 950000>;
+			opp-microvolt-speed14-pvs5 = <900000 900000 900000>;
+			opp-microvolt-speed14-pvs6 = <925000 900000 950000>;
 			opp-supported-hw = <0x4007>;
 		};
 
 		opp-1026000000 {
 			opp-hz = /bits/ 64 <1026000000>;
 			opp-peak-kBps = <648000>;
+			opp-microvolt-speed0-pvs0 = <1125000 1125000 1150000>;
+			opp-microvolt-speed0-pvs1 = <1100000 1075000 1125000>;
+			opp-microvolt-speed0-pvs3 = <1050000 1025000 1075000>;
+			opp-microvolt-speed0-pvs4 = <1025000 1000000 1050000>;
+			opp-microvolt-speed1-pvs0 = <1037500 1037500 1062500>;
+			opp-microvolt-speed1-pvs1 = <1037500 1012500 1062500>;
+			opp-microvolt-speed1-pvs2 = <1000000 975000 1025000>;
+			opp-microvolt-speed1-pvs3 = <975000 950000 1000000>;
+			opp-microvolt-speed1-pvs4 = <950000 925000 975000>;
+			opp-microvolt-speed1-pvs5 = <950000 925000 975000>;
+			opp-microvolt-speed1-pvs6 = <950000 925000 975000>;
+			opp-microvolt-speed2-pvs0 = <1000000 1000000 1025000>;
+			opp-microvolt-speed2-pvs1 = <975000 975000 975000>;
+			opp-microvolt-speed2-pvs2 = <975000 950000 1000000>;
+			opp-microvolt-speed2-pvs3 = <962500 937500 987500>;
+			opp-microvolt-speed2-pvs4 = <950000 925000 975000>;
+			opp-microvolt-speed2-pvs5 = <950000 925000 975000>;
+			opp-microvolt-speed2-pvs6 = <950000 925000 975000>;
+			opp-microvolt-speed14-pvs0 = <1037500 1037500 1062500>;
+			opp-microvolt-speed14-pvs1 = <1037500 1012500 1062500>;
+			opp-microvolt-speed14-pvs2 = <1000000 975000 1025000>;
+			opp-microvolt-speed14-pvs3 = <975000 950000 1000000>;
+			opp-microvolt-speed14-pvs4 = <950000 925000 975000>;
+			opp-microvolt-speed14-pvs5 = <925000 925000 925000>;
+			opp-microvolt-speed14-pvs6 = <950000 925000 975000>;
 			opp-supported-hw = <0x4007>;
 		};
 
 		opp-1134000000 {
 			opp-hz = /bits/ 64 <1134000000>;
 			opp-peak-kBps = <1134000>;
+			opp-microvolt-speed0-pvs0 = <1175000 1175000 1200000>;
+			opp-microvolt-speed0-pvs1 = <1150000 1125000 1175000>;
+			opp-microvolt-speed0-pvs3 = <1100000 1075000 1125000>;
+			opp-microvolt-speed0-pvs4 = <1075000 1050000 1100000>;
+			opp-microvolt-speed1-pvs0 = <1075000 1075000 1100000>;
+			opp-microvolt-speed1-pvs1 = <1062500 1037500 1087500>;
+			opp-microvolt-speed1-pvs2 = <1025000 1000000 1050000>;
+			opp-microvolt-speed1-pvs3 = <1000000 975000 1025000>;
+			opp-microvolt-speed1-pvs4 = <975000 950000 1000000>;
+			opp-microvolt-speed1-pvs5 = <962500 937500 987500>;
+			opp-microvolt-speed1-pvs6 = <962500 937500 987500>;
+			opp-microvolt-speed2-pvs0 = <1025000 1025000 1050000>;
+			opp-microvolt-speed2-pvs1 = <1000000 1000000 1000000>;
+			opp-microvolt-speed2-pvs2 = <1000000 975000 1025000>;
+			opp-microvolt-speed2-pvs3 = <987500 962500 1012500>;
+			opp-microvolt-speed2-pvs4 = <975000 950000 1000000>;
+			opp-microvolt-speed2-pvs5 = <962500 937500 987500>;
+			opp-microvolt-speed2-pvs6 = <962500 937500 987500>;
+			opp-microvolt-speed14-pvs0 = <1075000 1075000 1100000>;
+			opp-microvolt-speed14-pvs1 = <1062500 1037500 1087500>;
+			opp-microvolt-speed14-pvs2 = <1025000 1000000 1050000>;
+			opp-microvolt-speed14-pvs3 = <1000000 975000 1025000>;
+			opp-microvolt-speed14-pvs4 = <975000 950000 1000000>;
+			opp-microvolt-speed14-pvs5 = <937500 937500 937500>;
+			opp-microvolt-speed14-pvs6 = <962500 937500 987500>;
 			opp-supported-hw = <0x4007>;
 		};
 
 		opp-1242000000 {
 			opp-hz = /bits/ 64 <1242000000>;
 			opp-peak-kBps = <1134000>;
+			opp-microvolt-speed0-pvs0 = <1200000 1200000 1225000>;
+			opp-microvolt-speed0-pvs1 = <1175000 1150000 1200000>;
+			opp-microvolt-speed0-pvs3 = <1125000 1100000 1150000>;
+			opp-microvolt-speed0-pvs4 = <1100000 1075000 1125000>;
+			opp-microvolt-speed1-pvs0 = <1087500 1087500 1112500>;
+			opp-microvolt-speed1-pvs1 = <1075000 1050000 1100000>;
+			opp-microvolt-speed1-pvs2 = <1037500 1012500 1062500>;
+			opp-microvolt-speed1-pvs3 = <1012500 987500 1037500>;
+			opp-microvolt-speed1-pvs4 = <987500 962500 1012500>;
+			opp-microvolt-speed1-pvs5 = <975000 950000 1000000>;
+			opp-microvolt-speed1-pvs6 = <975000 950000 1000000>;
+			opp-microvolt-speed2-pvs0 = <1037500 1037500 1062500>;
+			opp-microvolt-speed2-pvs1 = <1012500 1012500 1012500>;
+			opp-microvolt-speed2-pvs2 = <1012500 987500 1037500>;
+			opp-microvolt-speed2-pvs3 = <1000000 975000 1025000>;
+			opp-microvolt-speed2-pvs4 = <987500 962500 1012500>;
+			opp-microvolt-speed2-pvs5 = <975000 950000 1000000>;
+			opp-microvolt-speed2-pvs6 = <975000 950000 1000000>;
+			opp-microvolt-speed14-pvs0 = <1087500 1087500 1112500>;
+			opp-microvolt-speed14-pvs1 = <1075000 1050000 1100000>;
+			opp-microvolt-speed14-pvs2 = <1037500 1012500 1062500>;
+			opp-microvolt-speed14-pvs3 = <1012500 987500 1037500>;
+			opp-microvolt-speed14-pvs4 = <987500 962500 1012500>;
+			opp-microvolt-speed14-pvs5 = <950000 950000 950000>;
+			opp-microvolt-speed14-pvs6 = <975000 950000 1000000>;
 			opp-supported-hw = <0x4007>;
 		};
 
 		opp-1350000000 {
 			opp-hz = /bits/ 64 <1350000000>;
 			opp-peak-kBps = <1134000>;
+			opp-microvolt-speed0-pvs0 = <1225000 1225000 1250000>;
+			opp-microvolt-speed0-pvs1 = <1200000 1175000 1225000>;
+			opp-microvolt-speed0-pvs3 = <1150000 1125000 1175000>;
+			opp-microvolt-speed0-pvs4 = <1125000 1100000 1150000>;
+			opp-microvolt-speed1-pvs0 = <1125000 1125000 1150000>;
+			opp-microvolt-speed1-pvs1 = <1112500 1087500 1137500>;
+			opp-microvolt-speed1-pvs2 = <1062500 1037500 1087500>;
+			opp-microvolt-speed1-pvs3 = <1025000 1000000 1050000>;
+			opp-microvolt-speed1-pvs4 = <1000000 975000 1025000>;
+			opp-microvolt-speed1-pvs5 = <987500 962500 1012500>;
+			opp-microvolt-speed1-pvs6 = <987500 962500 1012500>;
+			opp-microvolt-speed2-pvs0 = <1062500 1062500 1087500>;
+			opp-microvolt-speed2-pvs1 = <1037500 1037500 1037500>;
+			opp-microvolt-speed2-pvs2 = <1037500 1012500 1062500>;
+			opp-microvolt-speed2-pvs3 = <1025000 1000000 1050000>;
+			opp-microvolt-speed2-pvs4 = <1000000 975000 1025000>;
+			opp-microvolt-speed2-pvs5 = <987500 962500 1012500>;
+			opp-microvolt-speed2-pvs6 = <987500 962500 1012500>;
+			opp-microvolt-speed14-pvs0 = <1125000 1125000 1150000>;
+			opp-microvolt-speed14-pvs1 = <1112500 1087500 1137500>;
+			opp-microvolt-speed14-pvs2 = <1062500 1037500 1087500>;
+			opp-microvolt-speed14-pvs3 = <1025000 1000000 1050000>;
+			opp-microvolt-speed14-pvs4 = <1000000 975000 1025000>;
+			opp-microvolt-speed14-pvs5 = <962500 962500 962500>;
+			opp-microvolt-speed14-pvs6 = <987500 962500 1012500>;
 			opp-supported-hw = <0x4007>;
 		};
 
 		opp-1458000000 {
 			opp-hz = /bits/ 64 <1458000000>;
 			opp-peak-kBps = <1134000>;
+			opp-microvolt-speed0-pvs0 = <1237500 1237500 1262500>;
+			opp-microvolt-speed0-pvs1 = <1212500 1187500 1237500>;
+			opp-microvolt-speed0-pvs3 = <1162500 1137500 1187500>;
+			opp-microvolt-speed0-pvs4 = <1137500 1112500 1162500>;
+			opp-microvolt-speed1-pvs0 = <1150000 1150000 1175000>;
+			opp-microvolt-speed1-pvs1 = <1137500 1112500 1162500>;
+			opp-microvolt-speed1-pvs2 = <1100000 1075000 1125000>;
+			opp-microvolt-speed1-pvs3 = <1062500 1037500 1087500>;
+			opp-microvolt-speed1-pvs4 = <1025000 1000000 1050000>;
+			opp-microvolt-speed1-pvs5 = <1012500 987500 1037500>;
+			opp-microvolt-speed1-pvs6 = <1000000 975000 1025000>;
+			opp-microvolt-speed2-pvs0 = <1100000 1100000 1125000>;
+			opp-microvolt-speed2-pvs1 = <1075000 1075000 1075000>;
+			opp-microvolt-speed2-pvs2 = <1075000 1050000 1100000>;
+			opp-microvolt-speed2-pvs3 = <1050000 1025000 1075000>;
+			opp-microvolt-speed2-pvs4 = <1025000 1000000 1050000>;
+			opp-microvolt-speed2-pvs5 = <1012500 987500 1037500>;
+			opp-microvolt-speed2-pvs6 = <1000000 975000 1025000>;
+			opp-microvolt-speed14-pvs0 = <1150000 1150000 1175000>;
+			opp-microvolt-speed14-pvs1 = <1137500 1112500 1162500>;
+			opp-microvolt-speed14-pvs2 = <1100000 1075000 1125000>;
+			opp-microvolt-speed14-pvs3 = <1062500 1037500 1087500>;
+			opp-microvolt-speed14-pvs4 = <1025000 1000000 1050000>;
+			opp-microvolt-speed14-pvs5 = <987500 987500 987500>;
+			opp-microvolt-speed14-pvs6 = <1000000 975000 1025000>;
 			opp-supported-hw = <0x4007>;
 		};
 
 		opp-1512000000 {
 			opp-hz = /bits/ 64 <1512000000>;
 			opp-peak-kBps = <1134000>;
+			opp-microvolt-speed0-pvs0 = <1250000 1250000 1275000>;
+			opp-microvolt-speed0-pvs1 = <1225000 1200000 1250000>;
+			opp-microvolt-speed0-pvs3 = <1175000 1150000 1200000>;
+			opp-microvolt-speed0-pvs4 = <1150000 1125000 1175000>;
+			opp-microvolt-speed14-pvs0 = <1162500 1162500 1187500>;
+			opp-microvolt-speed14-pvs1 = <1150000 1125000 1175000>;
+			opp-microvolt-speed14-pvs2 = <1112500 1087500 1137500>;
+			opp-microvolt-speed14-pvs3 = <1075000 1050000 1100000>;
+			opp-microvolt-speed14-pvs4 = <1037500 1012500 1062500>;
+			opp-microvolt-speed14-pvs5 = <1000000 1000000 1000000>;
+			opp-microvolt-speed14-pvs6 = <1012500 987500 1037500>;
 			opp-supported-hw = <0x4001>;
 		};
 
 		opp-1566000000 {
 			opp-hz = /bits/ 64 <1566000000>;
 			opp-peak-kBps = <1134000>;
+			opp-microvolt-speed1-pvs0 = <1175000 1175000 1200000>;
+			opp-microvolt-speed1-pvs1 = <1175000 1150000 1200000>;
+			opp-microvolt-speed1-pvs2 = <1125000 1100000 1150000>;
+			opp-microvolt-speed1-pvs3 = <1087500 1062500 1112500>;
+			opp-microvolt-speed1-pvs4 = <1062500 1037500 1087500>;
+			opp-microvolt-speed1-pvs5 = <1037500 1012500 1062500>;
+			opp-microvolt-speed1-pvs6 = <1025000 1000000 1050000>;
+			opp-microvolt-speed2-pvs0 = <1125000 1125000 1150000>;
+			opp-microvolt-speed2-pvs1 = <1100000 1100000 1100000>;
+			opp-microvolt-speed2-pvs2 = <1100000 1075000 1125000>;
+			opp-microvolt-speed2-pvs3 = <1075000 1050000 1100000>;
+			opp-microvolt-speed2-pvs4 = <1062500 1037500 1087500>;
+			opp-microvolt-speed2-pvs5 = <1037500 1012500 1062500>;
+			opp-microvolt-speed2-pvs6 = <1025000 1000000 1050000>;
 			opp-supported-hw = <0x06>;
 		};
 
 		opp-1674000000 {
 			opp-hz = /bits/ 64 <1674000000>;
 			opp-peak-kBps = <1134000>;
+			opp-microvolt-speed1-pvs0 = <1225000 1225000 1250000>;
+			opp-microvolt-speed1-pvs1 = <1212500 1187500 1237500>;
+			opp-microvolt-speed1-pvs2 = <1162500 1137500 1187500>;
+			opp-microvolt-speed1-pvs3 = <1125000 1100000 1150000>;
+			opp-microvolt-speed1-pvs4 = <1100000 1075000 1125000>;
+			opp-microvolt-speed1-pvs5 = <1075000 1050000 1100000>;
+			opp-microvolt-speed1-pvs6 = <1050000 1025000 1075000>;
+			opp-microvolt-speed2-pvs0 = <1175000 1175000 1200000>;
+			opp-microvolt-speed2-pvs1 = <1137500 1137500 1137500>;
+			opp-microvolt-speed2-pvs2 = <1137500 1112500 1162500>;
+			opp-microvolt-speed2-pvs3 = <1112500 1087500 1137500>;
+			opp-microvolt-speed2-pvs4 = <1100000 1075000 1125000>;
+			opp-microvolt-speed2-pvs5 = <1075000 1050000 1100000>;
+			opp-microvolt-speed2-pvs6 = <1050000 1025000 1075000>;
 			opp-supported-hw = <0x06>;
 		};
 
 		opp-1728000000 {
 			opp-hz = /bits/ 64 <1728000000>;
 			opp-peak-kBps = <1134000>;
+			opp-microvolt-speed1-pvs0 = <1250000 1250000 1275000>;
+			opp-microvolt-speed1-pvs1 = <1225000 1200000 1250000>;
+			opp-microvolt-speed1-pvs2 = <1187500 1162500 1212500>;
+			opp-microvolt-speed1-pvs3 = <1150000 1125000 1175000>;
+			opp-microvolt-speed1-pvs4 = <1125000 1100000 1150000>;
+			opp-microvolt-speed1-pvs5 = <1100000 1075000 1125000>;
+			opp-microvolt-speed1-pvs6 = <1075000 1050000 1100000>;
 			opp-supported-hw = <0x02>;
 		};
 
 		opp-1782000000 {
 			opp-hz = /bits/ 64 <1782000000>;
 			opp-peak-kBps = <1134000>;
+			opp-microvolt-speed2-pvs0 = <1225000 1225000 1250000>;
+			opp-microvolt-speed2-pvs1 = <1187500 1187500 1187500>;
+			opp-microvolt-speed2-pvs2 = <1187500 1162500 1212500>;
+			opp-microvolt-speed2-pvs3 = <1162500 1137500 1187500>;
+			opp-microvolt-speed2-pvs4 = <1137500 1112500 1162500>;
+			opp-microvolt-speed2-pvs5 = <1112500 1087500 1137500>;
+			opp-microvolt-speed2-pvs6 = <1087500 1062500 1112500>;
 			opp-supported-hw = <0x04>;
 		};
 
 		opp-1890000000 {
 			opp-hz = /bits/ 64 <1890000000>;
 			opp-peak-kBps = <1134000>;
+			opp-microvolt-speed2-pvs0 = <1287500 1287500 1312500>;
+			opp-microvolt-speed2-pvs1 = <1250000 1250000 1250000>;
+			opp-microvolt-speed2-pvs2 = <1237500 1212500 1262500>;
+			opp-microvolt-speed2-pvs3 = <1200000 1175000 1225000>;
+			opp-microvolt-speed2-pvs4 = <1175000 1150000 1200000>;
+			opp-microvolt-speed2-pvs5 = <1150000 1125000 1175000>;
+			opp-microvolt-speed2-pvs6 = <1125000 1100000 1150000>;
 			opp-supported-hw = <0x04>;
 		};
 	};
-- 
2.39.2

[PATCH v2 19/26] ARM: dts: qcom: apq8064: enable passive CPU cooling

[Dmitry Baryshkov]

Wire up CPUs and thermal trip points to save the SoC from overheating by
lowering the CPU frequency.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
 arch/arm/boot/dts/qcom/qcom-apq8064.dtsi | 29 ++++++++++++++++++++++++
 1 file changed, 29 insertions(+)

diff --git a/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi
index b97d88517805..f38e3394b422 100644
--- a/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi
+++ b/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi
@@ -11,6 +11,7 @@
 #include <dt-bindings/soc/qcom,krait-l2-cache.h>
 #include <dt-bindings/interrupt-controller/irq.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/thermal/thermal.h>
 / {
 	#address-cells = <1>;
 	#size-cells = <1>;
@@ -701,6 +702,13 @@ cpu_crit0: trip1 {
 					type = "critical";
 				};
 			};
+
+			cooling-maps {
+				map0 {
+					trip = <&cpu_alert0>;
+					cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+				};
+			};
 		};
 
 		cpu1-thermal {
@@ -722,6 +730,13 @@ cpu_crit1: trip1 {
 					type = "critical";
 				};
 			};
+
+			cooling-maps {
+				map0 {
+					trip = <&cpu_alert1>;
+					cooling-device = <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+				};
+			};
 		};
 
 		cpu2-thermal {
@@ -743,6 +758,13 @@ cpu_crit2: trip1 {
 					type = "critical";
 				};
 			};
+
+			cooling-maps {
+				map0 {
+					trip = <&cpu_alert2>;
+					cooling-device = <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+				};
+			};
 		};
 
 		cpu3-thermal {
@@ -764,6 +786,13 @@ cpu_crit3: trip1 {
 					type = "critical";
 				};
 			};
+
+			cooling-maps {
+				map0 {
+					trip = <&cpu_alert3>;
+					cooling-device = <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+				};
+			};
 		};
 	};
 
-- 
2.39.2

[PATCH v2 20/26] ARM: dts: qcom: apq8064-asus-nexus7-flo: constraint cpufreq regulators

[Dmitry Baryshkov]

Add additional constraints to the CPUfreq-related regulators, it is
better be safe than sorry there.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
 .../boot/dts/qcom/qcom-apq8064-asus-nexus7-flo.dts | 14 ++++++++++++--
 1 file changed, 12 insertions(+), 2 deletions(-)

diff --git a/arch/arm/boot/dts/qcom/qcom-apq8064-asus-nexus7-flo.dts b/arch/arm/boot/dts/qcom/qcom-apq8064-asus-nexus7-flo.dts
index c57c27cd8a20..9f5d72727356 100644
--- a/arch/arm/boot/dts/qcom/qcom-apq8064-asus-nexus7-flo.dts
+++ b/arch/arm/boot/dts/qcom/qcom-apq8064-asus-nexus7-flo.dts
@@ -218,9 +218,9 @@ s1 {
 			bias-pull-down;
 		};
 
-		/* msm otg HSUSB_VDDCX */
+		/* msm otg HSUSB_VDDCX and VDD_DIG */
 		s3 {
-			regulator-min-microvolt = <500000>;
+			regulator-min-microvolt = <950000>;
 			regulator-max-microvolt = <1150000>;
 			qcom,switch-mode-frequency = <4800000>;
 		};
@@ -301,6 +301,12 @@ l23 {
 			bias-pull-down;
 		};
 
+		/* VDD_MEM */
+		l24 {
+			regulator-min-microvolt = <1050000>;
+			regulator-max-microvolt = <1150000>;
+		};
+
 		/*
 		 * tabla2x-slim-CDC_VDDA_A_1P2V
 		 * tabla2x-slim-VDDD_CDC_D
@@ -329,8 +335,12 @@ lvs6 {
 		/*
 		 * mipi_dsi.1-dsi1_vddio
 		 * pil_riva-pll_vdd
+		 * HFPLL regulator
 		 */
 		lvs7 {
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1800000>;
+			regulator-boot-on;
 			bias-pull-down;
 		};
 	};
-- 
2.39.2

[PATCH v2 21/26] ARM: dts: qcom: apq8064-ifc6410: constraint cpufreq regulators

[Dmitry Baryshkov]

Add additional constraints to the CPUfreq-related regulators, it is
better be safe than sorry there.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
 .../arm/boot/dts/qcom/qcom-apq8064-ifc6410.dts | 18 ++++++++++++++++--
 1 file changed, 16 insertions(+), 2 deletions(-)

diff --git a/arch/arm/boot/dts/qcom/qcom-apq8064-ifc6410.dts b/arch/arm/boot/dts/qcom/qcom-apq8064-ifc6410.dts
index 96307550523a..ad3cd45362df 100644
--- a/arch/arm/boot/dts/qcom/qcom-apq8064-ifc6410.dts
+++ b/arch/arm/boot/dts/qcom/qcom-apq8064-ifc6410.dts
@@ -215,8 +215,8 @@ s1 {
 		};
 
 		s3 {
-			regulator-min-microvolt = <1000000>;
-			regulator-max-microvolt = <1400000>;
+			regulator-min-microvolt = <950000>;
+			regulator-max-microvolt = <1150000>;
 			qcom,switch-mode-frequency = <4800000>;
 		};
 
@@ -262,6 +262,12 @@ l23 {
 			bias-pull-down;
 		};
 
+		l24 {
+			regulator-min-microvolt = <1050000>;
+			regulator-max-microvolt = <1150000>;
+			bias-pull-down;
+		};
+
 		lvs1 {
 			bias-pull-down;
 		};
@@ -269,6 +275,14 @@ lvs1 {
 		lvs6 {
 			bias-pull-down;
 		};
+
+		/* HFPLL regulator */
+		lvs7 {
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1800000>;
+			regulator-boot-on;
+			regulator-always-on;
+		};
 	};
 };
 
-- 
2.39.2

[PATCH v2 22/26] ARM: dts: qcom: msm8960: declare SAW2 regulators

[Dmitry Baryshkov]

The SAW2 (SPM and AVS Wrapper) among other things is yet another way to
handle CPU-related PMIC regulators. Provide a way to control voltage of
these regulators.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
 arch/arm/boot/dts/qcom/qcom-msm8960.dtsi | 12 ++++++++++--
 1 file changed, 10 insertions(+), 2 deletions(-)

diff --git a/arch/arm/boot/dts/qcom/qcom-msm8960.dtsi b/arch/arm/boot/dts/qcom/qcom-msm8960.dtsi
index fa2013388d99..50a5d87e9851 100644
--- a/arch/arm/boot/dts/qcom/qcom-msm8960.dtsi
+++ b/arch/arm/boot/dts/qcom/qcom-msm8960.dtsi
@@ -227,13 +227,21 @@ acc1: clock-controller@2098000 {
 		saw0: regulator@2089000 {
 			compatible = "qcom,saw2";
 			reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
-			regulator;
+
+			saw0_vreg: regulator {
+				regulator-min-microvolt = <850000>;
+				regulator-max-microvolt = <1300000>;
+			};
 		};
 
 		saw1: regulator@2099000 {
 			compatible = "qcom,saw2";
 			reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
-			regulator;
+
+			saw1_vreg: regulator {
+				regulator-min-microvolt = <850000>;
+				regulator-max-microvolt = <1300000>;
+			};
 		};
 
 		gsbi5: gsbi@16400000 {
-- 
2.39.2

[PATCH v2 23/26] ARM: dts: qcom: apq8084: drop 'regulator' property from SAW2 device

[Dmitry Baryshkov]

The SAW2 device should describe the regulator constraints rather than
just declaring that it has the regulator.

Drop the 'regulator' property. If/when CPU voltage scaling is
implemented for this platform, proper regulator node show be added
instead.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
 arch/arm/boot/dts/qcom/qcom-apq8084.dtsi | 1 -
 1 file changed, 1 deletion(-)

diff --git a/arch/arm/boot/dts/qcom/qcom-apq8084.dtsi b/arch/arm/boot/dts/qcom/qcom-apq8084.dtsi
index 8f178bc87e1d..6a2ff30a2f3c 100644
--- a/arch/arm/boot/dts/qcom/qcom-apq8084.dtsi
+++ b/arch/arm/boot/dts/qcom/qcom-apq8084.dtsi
@@ -652,7 +652,6 @@ saw3: power-controller@f90b9000 {
 		saw_l2: power-controller@f9012000 {
 			compatible = "qcom,saw2";
 			reg = <0xf9012000 0x1000>;
-			regulator;
 		};
 
 		acc0: power-manager@f9088000 {
-- 
2.39.2

[PATCH v2 24/26] ARM: dts: qcom: msm8974: drop 'regulator' property from SAW2 device

[Dmitry Baryshkov]

The SAW2 device should describe the regulator constraints rather than
just declaring that it has the regulator.

Drop the 'regulator' property. If/when CPU voltage scaling is
implemented for this platform, proper regulator node show be added
instead.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
 arch/arm/boot/dts/qcom/qcom-msm8974.dtsi | 1 -
 1 file changed, 1 deletion(-)

diff --git a/arch/arm/boot/dts/qcom/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom/qcom-msm8974.dtsi
index aeca504918a0..dffab32c757d 100644
--- a/arch/arm/boot/dts/qcom/qcom-msm8974.dtsi
+++ b/arch/arm/boot/dts/qcom/qcom-msm8974.dtsi
@@ -416,7 +416,6 @@ saw3: power-controller@f90b9000 {
 		saw_l2: power-controller@f9012000 {
 			compatible = "qcom,saw2";
 			reg = <0xf9012000 0x1000>;
-			regulator;
 		};
 
 		acc0: power-manager@f9088000 {
-- 
2.39.2

[PATCH v2 25/26] ARM: dts: qcom: ipq4019: drop 'regulator' property from SAW2 devices

[Dmitry Baryshkov]

The SAW2 device should describe the regulator constraints rather than
just declaring that it has the regulator.

Drop the 'regulator' property. If/when CPU voltage scaling is
implemented for this platform, proper regulator nodes show be added
instead.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
 arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi | 5 -----
 1 file changed, 5 deletions(-)

diff --git a/arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi b/arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi
index f0ef86fadc9d..ad3c922843c7 100644
--- a/arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi
+++ b/arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi
@@ -350,31 +350,26 @@ acc3: power-manager@b0b8000 {
 		saw0: regulator@b089000 {
 			compatible = "qcom,saw2";
 			reg = <0x0b089000 0x1000>, <0x0b009000 0x1000>;
-			regulator;
 		};
 
 		saw1: regulator@b099000 {
 			compatible = "qcom,saw2";
 			reg = <0x0b099000 0x1000>, <0x0b009000 0x1000>;
-			regulator;
 		};
 
 		saw2: regulator@b0a9000 {
 			compatible = "qcom,saw2";
 			reg = <0x0b0a9000 0x1000>, <0x0b009000 0x1000>;
-			regulator;
 		};
 
 		saw3: regulator@b0b9000 {
 			compatible = "qcom,saw2";
 			reg = <0x0b0b9000 0x1000>, <0x0b009000 0x1000>;
-			regulator;
 		};
 
 		saw_l2: regulator@b012000 {
 			compatible = "qcom,saw2";
 			reg = <0xb012000 0x1000>;
-			regulator;
 		};
 
 		blsp1_uart1: serial@78af000 {
-- 
2.39.2

[PATCH v2 26/26] ARM: dts: qcom: ipq8064: drop 'regulator' property from SAW2 devices

[Dmitry Baryshkov]

The SAW2 device should describe the regulator constraints rather than
just declaring that it has the regulator.

Drop the 'regulator' property. If/when CPU voltage scaling is
implemented for this platform, proper regulator nodes show be added
instead.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
 arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi | 2 --
 1 file changed, 2 deletions(-)

diff --git a/arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi b/arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi
index 6198f42f6a9c..ecb99e104de0 100644
--- a/arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi
+++ b/arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi
@@ -589,7 +589,6 @@ acc0: clock-controller@2088000 {
 		saw0: regulator@2089000 {
 			compatible = "qcom,saw2";
 			reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
-			regulator;
 		};
 
 		acc1: clock-controller@2098000 {
@@ -604,7 +603,6 @@ acc1: clock-controller@2098000 {
 		saw1: regulator@2099000 {
 			compatible = "qcom,saw2";
 			reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
-			regulator;
 		};
 
 		nss_common: syscon@3000000 {
-- 
2.39.2

Re: [PATCH v2 05/26] dt-bindings: cache: describe L2 cache on Qualcomm Krait platforms

[Rob Herring]

On Sun, 25 Jun 2023 23:25:26 +0300, Dmitry Baryshkov wrote:
> The L2 cache device on Qualcomm Krait platforms controls the supplying
> voltages and the cache frequency. Add corresponding bindings for this
> device.
> 
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
>  .../bindings/cache/qcom,krait-l2-cache.yaml   | 75 +++++++++++++++++++
>  include/dt-bindings/soc/qcom,krait-l2-cache.h | 12 +++
>  2 files changed, 87 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/cache/qcom,krait-l2-cache.yaml
>  create mode 100644 include/dt-bindings/soc/qcom,krait-l2-cache.h
> 

My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
on your patch (DT_CHECKER_FLAGS is new in v5.13):

yamllint warnings/errors:

dtschema/dtc warnings/errors:
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cache/sifive,ccache0.example.dtb: cache-controller@2010000: compatible:0: 'qcom,krait-l2-cache' was expected
	from schema $id: http://devicetree.org/schemas/cache/qcom,krait-l2-cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cache/sifive,ccache0.example.dtb: cache-controller@2010000: 'clocks' is a required property
	from schema $id: http://devicetree.org/schemas/cache/qcom,krait-l2-cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cache/sifive,ccache0.example.dtb: cache-controller@2010000: '#interconnect-cells' is a required property
	from schema $id: http://devicetree.org/schemas/cache/qcom,krait-l2-cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cache/sifive,ccache0.example.dtb: cache-controller@2010000: Unevaluated properties are not allowed ('compatible', 'interrupts', 'memory-region', 'reg' were unexpected)
	from schema $id: http://devicetree.org/schemas/cache/qcom,krait-l2-cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/opp/opp-v2-kryo-cpu.example.dtb: l2-cache: compatible:0: 'qcom,krait-l2-cache' was expected
	from schema $id: http://devicetree.org/schemas/cache/qcom,krait-l2-cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/opp/opp-v2-kryo-cpu.example.dtb: l2-cache: compatible: ['cache'] is too short
	from schema $id: http://devicetree.org/schemas/cache/qcom,krait-l2-cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/opp/opp-v2-kryo-cpu.example.dtb: l2-cache: 'clocks' is a required property
	from schema $id: http://devicetree.org/schemas/cache/qcom,krait-l2-cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/opp/opp-v2-kryo-cpu.example.dtb: l2-cache: '#interconnect-cells' is a required property
	from schema $id: http://devicetree.org/schemas/cache/qcom,krait-l2-cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/opp/opp-v2-kryo-cpu.example.dtb: l2-cache: Unevaluated properties are not allowed ('compatible' was unexpected)
	from schema $id: http://devicetree.org/schemas/cache/qcom,krait-l2-cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/opp/opp-v2-kryo-cpu.example.dtb: l2-cache: compatible:0: 'qcom,krait-l2-cache' was expected
	from schema $id: http://devicetree.org/schemas/cache/qcom,krait-l2-cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/opp/opp-v2-kryo-cpu.example.dtb: l2-cache: compatible: ['cache'] is too short
	from schema $id: http://devicetree.org/schemas/cache/qcom,krait-l2-cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/opp/opp-v2-kryo-cpu.example.dtb: l2-cache: 'clocks' is a required property
	from schema $id: http://devicetree.org/schemas/cache/qcom,krait-l2-cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/opp/opp-v2-kryo-cpu.example.dtb: l2-cache: '#interconnect-cells' is a required property
	from schema $id: http://devicetree.org/schemas/cache/qcom,krait-l2-cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/opp/opp-v2-kryo-cpu.example.dtb: l2-cache: Unevaluated properties are not allowed ('compatible' was unexpected)
	from schema $id: http://devicetree.org/schemas/cache/qcom,krait-l2-cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/thermal/thermal-cooling-devices.example.dtb: l2-cache: compatible:0: 'qcom,krait-l2-cache' was expected
	from schema $id: http://devicetree.org/schemas/cache/qcom,krait-l2-cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/thermal/thermal-cooling-devices.example.dtb: l2-cache: compatible: ['cache'] is too short
	from schema $id: http://devicetree.org/schemas/cache/qcom,krait-l2-cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/thermal/thermal-cooling-devices.example.dtb: l2-cache: 'clocks' is a required property
	from schema $id: http://devicetree.org/schemas/cache/qcom,krait-l2-cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/thermal/thermal-cooling-devices.example.dtb: l2-cache: '#interconnect-cells' is a required property
	from schema $id: http://devicetree.org/schemas/cache/qcom,krait-l2-cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/thermal/thermal-cooling-devices.example.dtb: l2-cache: Unevaluated properties are not allowed ('compatible', 'l3-cache' were unexpected)
	from schema $id: http://devicetree.org/schemas/cache/qcom,krait-l2-cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/thermal/thermal-cooling-devices.example.dtb: l3-cache: compatible:0: 'qcom,krait-l2-cache' was expected
	from schema $id: http://devicetree.org/schemas/cache/qcom,krait-l2-cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/thermal/thermal-cooling-devices.example.dtb: l3-cache: compatible: ['cache'] is too short
	from schema $id: http://devicetree.org/schemas/cache/qcom,krait-l2-cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/thermal/thermal-cooling-devices.example.dtb: l3-cache: 'clocks' is a required property
	from schema $id: http://devicetree.org/schemas/cache/qcom,krait-l2-cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/thermal/thermal-cooling-devices.example.dtb: l3-cache: '#interconnect-cells' is a required property
	from schema $id: http://devicetree.org/schemas/cache/qcom,krait-l2-cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/thermal/thermal-cooling-devices.example.dtb: l3-cache: Unevaluated properties are not allowed ('compatible' was unexpected)
	from schema $id: http://devicetree.org/schemas/cache/qcom,krait-l2-cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l2-cache: compatible:0: 'qcom,krait-l2-cache' was expected
	from schema $id: http://devicetree.org/schemas/cache/qcom,krait-l2-cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l2-cache: compatible: ['cache'] is too short
	from schema $id: http://devicetree.org/schemas/cache/qcom,krait-l2-cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l2-cache: 'clocks' is a required property
	from schema $id: http://devicetree.org/schemas/cache/qcom,krait-l2-cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l2-cache: '#interconnect-cells' is a required property
	from schema $id: http://devicetree.org/schemas/cache/qcom,krait-l2-cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l2-cache: Unevaluated properties are not allowed ('compatible', 'l3-cache' were unexpected)
	from schema $id: http://devicetree.org/schemas/cache/qcom,krait-l2-cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l3-cache: compatible:0: 'qcom,krait-l2-cache' was expected
	from schema $id: http://devicetree.org/schemas/cache/qcom,krait-l2-cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l3-cache: compatible: ['cache'] is too short
	from schema $id: http://devicetree.org/schemas/cache/qcom,krait-l2-cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l3-cache: 'clocks' is a required property
	from schema $id: http://devicetree.org/schemas/cache/qcom,krait-l2-cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l3-cache: '#interconnect-cells' is a required property
	from schema $id: http://devicetree.org/schemas/cache/qcom,krait-l2-cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l3-cache: Unevaluated properties are not allowed ('compatible' was unexpected)
	from schema $id: http://devicetree.org/schemas/cache/qcom,krait-l2-cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l2-cache: compatible:0: 'qcom,krait-l2-cache' was expected
	from schema $id: http://devicetree.org/schemas/cache/qcom,krait-l2-cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l2-cache: compatible: ['cache'] is too short
	from schema $id: http://devicetree.org/schemas/cache/qcom,krait-l2-cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l2-cache: 'clocks' is a required property
	from schema $id: http://devicetree.org/schemas/cache/qcom,krait-l2-cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l2-cache: '#interconnect-cells' is a required property
	from schema $id: http://devicetree.org/schemas/cache/qcom,krait-l2-cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l2-cache: Unevaluated properties are not allowed ('compatible' was unexpected)
	from schema $id: http://devicetree.org/schemas/cache/qcom,krait-l2-cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l2-cache: compatible:0: 'qcom,krait-l2-cache' was expected
	from schema $id: http://devicetree.org/schemas/cache/qcom,krait-l2-cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l2-cache: compatible: ['cache'] is too short
	from schema $id: http://devicetree.org/schemas/cache/qcom,krait-l2-cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l2-cache: 'clocks' is a required property
	from schema $id: http://devicetree.org/schemas/cache/qcom,krait-l2-cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l2-cache: '#interconnect-cells' is a required property
	from schema $id: http://devicetree.org/schemas/cache/qcom,krait-l2-cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l2-cache: Unevaluated properties are not allowed ('compatible' was unexpected)
	from schema $id: http://devicetree.org/schemas/cache/qcom,krait-l2-cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l2-cache: compatible:0: 'qcom,krait-l2-cache' was expected
	from schema $id: http://devicetree.org/schemas/cache/qcom,krait-l2-cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l2-cache: compatible: ['cache'] is too short
	from schema $id: http://devicetree.org/schemas/cache/qcom,krait-l2-cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l2-cache: 'clocks' is a required property
	from schema $id: http://devicetree.org/schemas/cache/qcom,krait-l2-cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l2-cache: '#interconnect-cells' is a required property
	from schema $id: http://devicetree.org/schemas/cache/qcom,krait-l2-cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l2-cache: Unevaluated properties are not allowed ('compatible' was unexpected)
	from schema $id: http://devicetree.org/schemas/cache/qcom,krait-l2-cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l2-cache: compatible:0: 'qcom,krait-l2-cache' was expected
	from schema $id: http://devicetree.org/schemas/cache/qcom,krait-l2-cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l2-cache: compatible: ['cache'] is too short
	from schema $id: http://devicetree.org/schemas/cache/qcom,krait-l2-cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l2-cache: 'clocks' is a required property
	from schema $id: http://devicetree.org/schemas/cache/qcom,krait-l2-cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l2-cache: '#interconnect-cells' is a required property
	from schema $id: http://devicetree.org/schemas/cache/qcom,krait-l2-cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l2-cache: Unevaluated properties are not allowed ('compatible' was unexpected)
	from schema $id: http://devicetree.org/schemas/cache/qcom,krait-l2-cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l2-cache: compatible:0: 'qcom,krait-l2-cache' was expected
	from schema $id: http://devicetree.org/schemas/cache/qcom,krait-l2-cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l2-cache: compatible: ['cache'] is too short
	from schema $id: http://devicetree.org/schemas/cache/qcom,krait-l2-cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l2-cache: 'clocks' is a required property
	from schema $id: http://devicetree.org/schemas/cache/qcom,krait-l2-cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l2-cache: '#interconnect-cells' is a required property
	from schema $id: http://devicetree.org/schemas/cache/qcom,krait-l2-cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l2-cache: Unevaluated properties are not allowed ('compatible' was unexpected)
	from schema $id: http://devicetree.org/schemas/cache/qcom,krait-l2-cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l2-cache: compatible:0: 'qcom,krait-l2-cache' was expected
	from schema $id: http://devicetree.org/schemas/cache/qcom,krait-l2-cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l2-cache: compatible: ['cache'] is too short
	from schema $id: http://devicetree.org/schemas/cache/qcom,krait-l2-cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l2-cache: 'clocks' is a required property
	from schema $id: http://devicetree.org/schemas/cache/qcom,krait-l2-cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l2-cache: '#interconnect-cells' is a required property
	from schema $id: http://devicetree.org/schemas/cache/qcom,krait-l2-cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l2-cache: Unevaluated properties are not allowed ('compatible' was unexpected)
	from schema $id: http://devicetree.org/schemas/cache/qcom,krait-l2-cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l2-cache: compatible:0: 'qcom,krait-l2-cache' was expected
	from schema $id: http://devicetree.org/schemas/cache/qcom,krait-l2-cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l2-cache: compatible: ['cache'] is too short
	from schema $id: http://devicetree.org/schemas/cache/qcom,krait-l2-cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l2-cache: 'clocks' is a required property
	from schema $id: http://devicetree.org/schemas/cache/qcom,krait-l2-cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l2-cache: '#interconnect-cells' is a required property
	from schema $id: http://devicetree.org/schemas/cache/qcom,krait-l2-cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l2-cache: Unevaluated properties are not allowed ('compatible' was unexpected)
	from schema $id: http://devicetree.org/schemas/cache/qcom,krait-l2-cache.yaml#

doc reference errors (make refcheckdocs):

See https://patchwork.ozlabs.org/project/devicetree-bindings/patch/20230625202547.174647-6-dmitry.baryshkov@linaro.org

The base for the series is generally the latest rc1. A different dependency
should be noted in *this* patch.

If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:

pip3 install dtschema --upgrade

Please check and re-submit after running the above command yourself. Note
that DT_SCHEMA_FILES can be set to your schema file to speed up checking
your schema. However, it must be unset to test all examples with your schema.

Re: [PATCH v2 04/26] dt-bindings: clock: qcom,krait-cc: Krait core clock controller

[Konrad Dybcio]

On 25.06.2023 22:25, Dmitry Baryshkov wrote:
> Define bindings for the Qualcomm Krait CPU and L2 clock controller. This
> device is used on old Qualcomm SoCs (APQ8064, MSM8960) and supports up
> to 4 core clocks and a separate L2 clock. Furthermore, L2 clock is
> represented as the interconnect to facilitate L2 frequency scaling
> together with scaling the CPU frequencies.
> 
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
Worth noting that there's no Krait cluster containing more than 4
cores and the last SoC using this uarch was released 10y ago, so
we can quite confidently say that the max cpu no won't change.

Konrad
>  include/dt-bindings/clock/qcom,krait-cc.h | 17 +++++++++++++++++
>  1 file changed, 17 insertions(+)
>  create mode 100644 include/dt-bindings/clock/qcom,krait-cc.h
> 
> diff --git a/include/dt-bindings/clock/qcom,krait-cc.h b/include/dt-bindings/clock/qcom,krait-cc.h
> new file mode 100644
> index 000000000000..ff69a0a968d8
> --- /dev/null
> +++ b/include/dt-bindings/clock/qcom,krait-cc.h
> @@ -0,0 +1,17 @@
> +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
> +/*
> + * Copyright (C) 2023 Linaro Ltd. All rights reserved.
> + */
> +
> +#ifndef __DT_BINDINGS_CLOCK_QCOM_KRAIT_CC_H
> +#define __DT_BINDINGS_CLOCK_QCOM_KRAIT_CC_H
> +
> +#define KRAIT_CPU_0		0
> +#define KRAIT_CPU_1		1
> +#define KRAIT_CPU_2		2
> +#define KRAIT_CPU_3		3
> +#define KRAIT_L2		4
> +
> +#define KRAIT_NUM_CLOCKS	5
> +
> +#endif

Re: [PATCH v2 06/26] interconnect: icc-clk: add support for scaling using OPP

[Konrad Dybcio]

On 25.06.2023 22:25, Dmitry Baryshkov wrote:
> Sometimes it might be required to scale the clock using the OPP
> framework (e.g. to scale regulators following the required clock rate).
> Extend the interconnec
't'

>-clk framework to handle OPP case in addition to
> scaling the clock.
> 
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
I think we should check for OPP at the icc-clk registration time,
instead of passing it as a parameter, e.g.:

qn.opp = IS_ERR(dev_pm_opp_get_opp_count)

Not sure if there's a more idiomatic way.

Konrad
>  drivers/interconnect/icc-clk.c   | 13 +++++++++++--
>  include/linux/interconnect-clk.h |  1 +
>  2 files changed, 12 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/interconnect/icc-clk.c b/drivers/interconnect/icc-clk.c
> index 4d43ebff4257..c7962acdcee7 100644
> --- a/drivers/interconnect/icc-clk.c
> +++ b/drivers/interconnect/icc-clk.c
> @@ -7,10 +7,13 @@
>  #include <linux/device.h>
>  #include <linux/interconnect-clk.h>
>  #include <linux/interconnect-provider.h>
> +#include <linux/pm_opp.h>
>  
>  struct icc_clk_node {
> +	struct device *dev;
>  	struct clk *clk;
>  	bool enabled;
> +	bool opp;
>  };
>  
>  struct icc_clk_provider {
> @@ -25,12 +28,16 @@ struct icc_clk_provider {
>  static int icc_clk_set(struct icc_node *src, struct icc_node *dst)
>  {
>  	struct icc_clk_node *qn = src->data;
> +	unsigned long rate = icc_units_to_bps(src->peak_bw);
>  	int ret;
>  
>  	if (!qn || !qn->clk)
>  		return 0;
>  
> -	if (!src->peak_bw) {
> +	if (qn->opp)
> +		return dev_pm_opp_set_rate(qn->dev, rate);
> +
> +	if (!rate) {
>  		if (qn->enabled)
>  			clk_disable_unprepare(qn->clk);
>  		qn->enabled = false;
> @@ -45,7 +52,7 @@ static int icc_clk_set(struct icc_node *src, struct icc_node *dst)
>  		qn->enabled = true;
>  	}
>  
> -	return clk_set_rate(qn->clk, icc_units_to_bps(src->peak_bw));
> +	return clk_set_rate(qn->clk, rate);
>  }
>  
>  static int icc_clk_get_bw(struct icc_node *node, u32 *avg, u32 *peak)
> @@ -106,7 +113,9 @@ struct icc_provider *icc_clk_register(struct device *dev,
>  	icc_provider_init(provider);
>  
>  	for (i = 0, j = 0; i < num_clocks; i++) {
> +		qp->clocks[i].dev = dev;
>  		qp->clocks[i].clk = data[i].clk;
> +		qp->clocks[i].opp = data[i].opp;
>  
>  		node = icc_node_create(first_id + j);
>  		if (IS_ERR(node)) {
> diff --git a/include/linux/interconnect-clk.h b/include/linux/interconnect-clk.h
> index 0cd80112bea5..c695e5099901 100644
> --- a/include/linux/interconnect-clk.h
> +++ b/include/linux/interconnect-clk.h
> @@ -11,6 +11,7 @@ struct device;
>  struct icc_clk_data {
>  	struct clk *clk;
>  	const char *name;
> +	bool opp;
>  };
>  
>  struct icc_provider *icc_clk_register(struct device *dev,

Re: [PATCH v2 08/26] soc: qcom: spm: add support for voltage regulator

[Konrad Dybcio]

On 25.06.2023 22:25, Dmitry Baryshkov wrote:
> The SPM / SAW2 device also provides a voltage regulator functionality
> with optional AVS (Adaptive Voltage Scaling) support. The exact register
> sequence and voltage ranges differs from device to device.
> 
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
>  drivers/soc/qcom/spm.c | 205 ++++++++++++++++++++++++++++++++++++++++-
>  include/soc/qcom/spm.h |   9 ++
>  2 files changed, 212 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/soc/qcom/spm.c b/drivers/soc/qcom/spm.c
> index a6cbeb40831b..3c16a7e1710c 100644
> --- a/drivers/soc/qcom/spm.c
> +++ b/drivers/soc/qcom/spm.c
> @@ -9,19 +9,31 @@
>  #include <linux/kernel.h>
>  #include <linux/init.h>
>  #include <linux/io.h>
> +#include <linux/iopoll.h>
> +#include <linux/linear_range.h>
>  #include <linux/module.h>
>  #include <linux/slab.h>
>  #include <linux/of.h>
>  #include <linux/of_address.h>
>  #include <linux/of_device.h>
> +#include <linux/bitfield.h>
This addition is very out-of-order

>  #include <linux/err.h>
>  #include <linux/platform_device.h>
> +#include <linux/regulator/driver.h>
> +#include <linux/smp.h>
>  #include <soc/qcom/spm.h>
>  
> +#define FIELD_SET(current, mask, val)	\
> +	(((current) & ~(mask)) | FIELD_PREP((mask), (val)))
> +
>  #define SPM_CTL_INDEX		0x7f
>  #define SPM_CTL_INDEX_SHIFT	4
>  #define SPM_CTL_EN		BIT(0)
>  
> +#define SPM_1_1_AVS_CTL_AVS_ENABLED BIT(27)
> +#define SPM_AVS_CTL_MIN_VLVL	(0x3f << 10)
> +#define SPM_AVS_CTL_MAX_VLVL	(0x3f << 17)
GENMASK

> +
>  enum spm_reg {
>  	SPM_REG_CFG,
>  	SPM_REG_SPM_CTL,
> @@ -31,10 +43,12 @@ enum spm_reg {
>  	SPM_REG_PMIC_DATA_1,
>  	SPM_REG_VCTL,
>  	SPM_REG_SEQ_ENTRY,
> -	SPM_REG_SPM_STS,
> +	SPM_REG_STS0,
> +	SPM_REG_STS1,
>  	SPM_REG_PMIC_STS,
>  	SPM_REG_AVS_CTL,
>  	SPM_REG_AVS_LIMIT,
> +	SPM_REG_RST,
>  	SPM_REG_NR,
>  };
>  
> @@ -171,6 +185,10 @@ static const struct spm_reg_data spm_reg_8226_cpu  = {
>  
>  static const u16 spm_reg_offset_v1_1[SPM_REG_NR] = {
>  	[SPM_REG_CFG]		= 0x08,
> +	[SPM_REG_STS0]		= 0x0c,
> +	[SPM_REG_STS1]		= 0x10,
> +	[SPM_REG_VCTL]		= 0x14,
> +	[SPM_REG_AVS_CTL]	= 0x18,
>  	[SPM_REG_SPM_CTL]	= 0x20,
>  	[SPM_REG_PMIC_DLY]	= 0x24,
>  	[SPM_REG_PMIC_DATA_0]	= 0x28,
> @@ -178,7 +196,12 @@ static const u16 spm_reg_offset_v1_1[SPM_REG_NR] = {
>  	[SPM_REG_SEQ_ENTRY]	= 0x80,
>  };
>  
> +static void smp_set_vdd_v1_1(void *data);
> +
>  /* SPM register data for 8064 */
> +static struct linear_range spm_v1_1_regulator_range =
> +	REGULATOR_LINEAR_RANGE(700000, 0, 56, 12500);
> +
>  static const struct spm_reg_data spm_reg_8064_cpu = {
>  	.reg_offset = spm_reg_offset_v1_1,
>  	.spm_cfg = 0x1F,
> @@ -189,6 +212,10 @@ static const struct spm_reg_data spm_reg_8064_cpu = {
>  		0x10, 0x54, 0x30, 0x0C, 0x24, 0x30, 0x0F },
>  	.start_index[PM_SLEEP_MODE_STBY] = 0,
>  	.start_index[PM_SLEEP_MODE_SPC] = 2,
> +	.set_vdd = smp_set_vdd_v1_1,
> +	.range = &spm_v1_1_regulator_range,
> +	.init_uV = 1300000,
> +	.ramp_delay = 1250,
>  };
>  
>  static inline void spm_register_write(struct spm_driver_data *drv,
> @@ -240,6 +267,179 @@ void spm_set_low_power_mode(struct spm_driver_data *drv,
>  	spm_register_write_sync(drv, SPM_REG_SPM_CTL, ctl_val);
>  }
>  
> +static int spm_set_voltage_sel(struct regulator_dev *rdev, unsigned int selector)
> +{
> +	struct spm_driver_data *drv = rdev_get_drvdata(rdev);
> +
> +	drv->volt_sel = selector;
> +
> +	/* Always do the SAW register writes on the corresponding CPU */
> +	return smp_call_function_single(drv->reg_cpu, drv->reg_data->set_vdd, drv, true);
> +}
> +
> +static int spm_get_voltage_sel(struct regulator_dev *rdev)
> +{
> +	struct spm_driver_data *drv = rdev_get_drvdata(rdev);
> +
> +	return drv->volt_sel;
> +}
> +
> +static const struct regulator_ops spm_reg_ops = {
> +	.set_voltage_sel	= spm_set_voltage_sel,
> +	.get_voltage_sel	= spm_get_voltage_sel,
> +	.list_voltage		= regulator_list_voltage_linear_range,
> +	.set_voltage_time_sel	= regulator_set_voltage_time_sel,
> +};
> +
> +static void smp_set_vdd_v1_1(void *data)
> +{
> +	struct spm_driver_data *drv = data;
> +	unsigned int vlevel = drv->volt_sel;
> +	unsigned int vctl, data0, data1, avs_ctl, sts;
> +	bool avs_enabled;
Reverse-Christmas-tree?

> +
> +	vlevel |= 0x80; /* band */
That's conveniently 1<<7.. do we know if it's a significant number
or just a bit that does something within that field?

> +
> +	avs_ctl = spm_register_read(drv, SPM_REG_AVS_CTL);
> +	vctl = spm_register_read(drv, SPM_REG_VCTL);
> +	data0 = spm_register_read(drv, SPM_REG_PMIC_DATA_0);
> +	data1 = spm_register_read(drv, SPM_REG_PMIC_DATA_1);
> +
> +	avs_enabled = avs_ctl & SPM_1_1_AVS_CTL_AVS_ENABLED;
> +
> +	/* If AVS is enabled, switch it off during the voltage change */
> +	if (avs_enabled) {
> +		avs_ctl &= ~SPM_1_1_AVS_CTL_AVS_ENABLED;
> +		spm_register_write(drv, SPM_REG_AVS_CTL, avs_ctl);
> +	}
> +
> +	/* Kick the state machine back to idle */
> +	spm_register_write(drv, SPM_REG_RST, 1);
> +
> +	vctl = FIELD_SET(vctl, 0xff, vlevel);
> +	data0 = FIELD_SET(data0, 0xff, vlevel);
> +	data1 = FIELD_SET(data1, 0x3f, vlevel);
> +	data1 = FIELD_SET(data1, 0x3f << 16, vlevel);
GENMASK

> +
> +	spm_register_write(drv, SPM_REG_VCTL, vctl);
> +	spm_register_write(drv, SPM_REG_PMIC_DATA_0, data0);
> +	spm_register_write(drv, SPM_REG_PMIC_DATA_1, data1);
> +
> +	if (read_poll_timeout_atomic(spm_register_read,
> +				      sts, sts == vlevel,
> +				      1, 200, false,
> +				      drv, SPM_REG_STS1)) {
Not sure if misaligned or thunderfox is acting up again

> +		dev_err_ratelimited(drv->dev, "timeout setting the voltage (%x %x)!\n", sts, vlevel);
> +		goto enable_avs;
> +	}
> +
> +	if (avs_enabled) {
> +		unsigned int max_avs = vlevel & 0x3f;
GENMASK

> +		unsigned int min_avs = max(max_avs, 4U) - 4;
So it's 0 or >= (1<<31 - 4)?

> +		avs_ctl = FIELD_SET(avs_ctl, SPM_AVS_CTL_MIN_VLVL, min_avs);
> +		avs_ctl = FIELD_SET(avs_ctl, SPM_AVS_CTL_MAX_VLVL, max_avs);
> +		spm_register_write(drv, SPM_REG_AVS_CTL, avs_ctl);
> +	}
> +
> +enable_avs:
> +	if (avs_enabled) {
> +		avs_ctl |= SPM_1_1_AVS_CTL_AVS_ENABLED;
> +		spm_register_write(drv, SPM_REG_AVS_CTL, avs_ctl);
> +	}
> +}
> +
> +static int spm_get_cpu(struct device *dev)
> +{
> +	int cpu;
> +	bool found;
Reverse-Christmas-tree?

> +
> +	for_each_possible_cpu(cpu) {
> +		struct device_node *cpu_node, *saw_node;
As long as Linux is running, there should be at least one CPU up,
so this always gets entered, perhaps the definitions could be moved
to the main function body

> +
> +		cpu_node = of_cpu_device_node_get(cpu);
> +		if (!cpu_node)
> +			continue;
> +
> +		saw_node = of_parse_phandle(cpu_node, "qcom,saw", 0);
> +		found = (saw_node == dev->of_node);
The error checking here works out, but it's a bit cryptic.. Though
I'm not opposed to saving 3 cycles on slow and old CPUs :D

> +		of_node_put(saw_node);
> +		of_node_put(cpu_node);
> +
> +		if (found)
> +			return cpu;
> +	}
> +
> +	/* L2 SPM is not bound to any CPU, tie it to CPU0 */
> +
> +	return 0;
> +}
> +
> +#ifdef CONFIG_REGULATOR
> +static int spm_register_regulator(struct device *dev, struct spm_driver_data *drv)
> +{
> +	struct regulator_config config = {
> +		.dev = dev,
> +		.driver_data = drv,
> +	};
> +	struct regulator_desc *rdesc;
> +	struct regulator_dev *rdev;
> +	int ret;
> +	bool found;
Reverse-Christmas-tree?

Konrad
> +
> +	if (!drv->reg_data->set_vdd)
> +		return 0;
> +
> +	rdesc = devm_kzalloc(dev, sizeof(*rdesc), GFP_KERNEL);
> +	if (!rdesc)
> +		return -ENOMEM;
> +
> +	rdesc->name = "spm";
> +	rdesc->of_match = of_match_ptr("regulator");
> +	rdesc->type = REGULATOR_VOLTAGE;
> +	rdesc->owner = THIS_MODULE;
> +	rdesc->ops = &spm_reg_ops;
> +
> +	rdesc->linear_ranges = drv->reg_data->range;
> +	rdesc->n_linear_ranges = 1;
> +	rdesc->n_voltages = rdesc->linear_ranges[rdesc->n_linear_ranges - 1].max_sel + 1;
> +	rdesc->ramp_delay = drv->reg_data->ramp_delay;
> +
> +	drv->reg_cpu = spm_get_cpu(dev);
> +	dev_dbg(dev, "SAW2 bound to CPU %d\n", drv->reg_cpu);
> +
> +	/*
> +	 * Program initial voltage, otherwise registration will also try
> +	 * setting the voltage, which might result in undervolting the CPU.
> +	 */
> +	drv->volt_sel = DIV_ROUND_UP(drv->reg_data->init_uV - rdesc->min_uV,
> +				     rdesc->uV_step);
> +	ret = linear_range_get_selector_high(drv->reg_data->range,
> +					     drv->reg_data->init_uV,
> +					     &drv->volt_sel,
> +					     &found);
> +	if (ret) {
> +		dev_err(dev, "Initial uV value out of bounds\n");
> +		return ret;
> +	}
> +
> +	/* Always do the SAW register writes on the corresponding CPU */
> +	smp_call_function_single(drv->reg_cpu, drv->reg_data->set_vdd, drv, true);
> +
> +	rdev = devm_regulator_register(dev, rdesc, &config);
> +	if (IS_ERR(rdev)) {
> +		dev_err(dev, "failed to register regulator\n");
> +		return PTR_ERR(rdev);
> +	}
> +
> +	return 0;
> +}
> +#else
> +static int spm_register_regulator(struct device *dev, struct spm_driver_data *drv)
> +{
> +	return 0;
> +}
> +#endif
> +
>  static const struct of_device_id spm_match_table[] = {
>  	{ .compatible = "qcom,sdm660-gold-saw2-v4.1-l2",
>  	  .data = &spm_reg_660_gold_l2 },
> @@ -292,6 +492,7 @@ static int spm_dev_probe(struct platform_device *pdev)
>  		return -ENODEV;
>  
>  	drv->reg_data = match_id->data;
> +	drv->dev = &pdev->dev;
>  	platform_set_drvdata(pdev, drv);
>  
>  	/* Write the SPM sequences first.. */
> @@ -319,7 +520,7 @@ static int spm_dev_probe(struct platform_device *pdev)
>  	if (drv->reg_data->reg_offset[SPM_REG_SPM_CTL])
>  		spm_set_low_power_mode(drv, PM_SLEEP_MODE_STBY);
>  
> -	return 0;
> +	return spm_register_regulator(&pdev->dev, drv);
>  }
>  
>  static struct platform_driver spm_driver = {
> diff --git a/include/soc/qcom/spm.h b/include/soc/qcom/spm.h
> index 4951f9d8b0bd..9859ebe42003 100644
> --- a/include/soc/qcom/spm.h
> +++ b/include/soc/qcom/spm.h
> @@ -30,11 +30,20 @@ struct spm_reg_data {
>  	u32 avs_limit;
>  	u8 seq[MAX_SEQ_DATA];
>  	u8 start_index[PM_SLEEP_MODE_NR];
> +
> +	smp_call_func_t set_vdd;
> +	/* for now we support only a single range */
> +	struct linear_range *range;
> +	unsigned int ramp_delay;
> +	unsigned int init_uV;
>  };
>  
>  struct spm_driver_data {
>  	void __iomem *reg_base;
>  	const struct spm_reg_data *reg_data;
> +	struct device *dev;
> +	unsigned int volt_sel;
> +	int reg_cpu;
>  };
>  
>  void spm_set_low_power_mode(struct spm_driver_data *drv,

Re: [PATCH v2 09/26] cpufreq: qcom-nvmem: create L2 cache device

[Konrad Dybcio]

On 25.06.2023 22:25, Dmitry Baryshkov wrote:
> Scaling the frequencies on some of Qualcomm Krait platforms (e.g.
> APQ8064) also requires scaling of the L2 cache frequency. As the
> l2-cache device node is places under /cpus/ path, it is not created by
> default by the OF code. Create corresponding device here.
> 
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
I think a generic solution (i.e. for each cpu node call
of_platform_populate in drivers/of/platform.c :
of_platform_default_populate_init) could be beneficial

Konrad
>  drivers/cpufreq/qcom-cpufreq-nvmem.c | 20 ++++++++++++++++++++
>  1 file changed, 20 insertions(+)
> 
> diff --git a/drivers/cpufreq/qcom-cpufreq-nvmem.c b/drivers/cpufreq/qcom-cpufreq-nvmem.c
> index a88b6fe5db50..ab78ef1531d0 100644
> --- a/drivers/cpufreq/qcom-cpufreq-nvmem.c
> +++ b/drivers/cpufreq/qcom-cpufreq-nvmem.c
> @@ -380,6 +380,7 @@ static int __init qcom_cpufreq_init(void)
>  {
>  	struct device_node *np = of_find_node_by_path("/");
>  	const struct of_device_id *match;
> +	unsigned int cpu;
>  	int ret;
>  
>  	if (!np)
> @@ -390,6 +391,25 @@ static int __init qcom_cpufreq_init(void)
>  	if (!match)
>  		return -ENODEV;
>  
> +	for_each_possible_cpu(cpu) {
> +		struct device *dev = get_cpu_device(cpu);
> +		struct device_node *cache;
> +		struct platform_device *pdev;
> +
> +		cache = of_find_next_cache_node(dev->of_node);
> +		if (!cache)
> +			continue;
> +
> +		if (of_device_is_compatible(cache, "qcom,krait-l2-cache")) {
> +			pdev = of_platform_device_create(cache, NULL, NULL);
> +			if (IS_ERR(pdev))
> +				pr_err("%s: %pe, failed to create L2 cache node\n", __func__, pdev);
> +			/* the error is not fatal */
> +		}
> +
> +		of_node_put(cache);
> +	}
> +
>  	ret = platform_driver_register(&qcom_cpufreq_driver);
>  	if (unlikely(ret < 0))
>  		return ret;

Re: [PATCH v2 10/26] cpufreq: qcom-nvmem: also accept operating-points-v2-krait-cpu

[Konrad Dybcio]

On 25.06.2023 22:25, Dmitry Baryshkov wrote:
> the qcom-cpufreq-nvmem driver attempts to support both Qualcomm Kryo
> (newer 64-bit ARMv8 cores) and Krait (older 32-bit ARMv7 cores). It
> makes no sense to use 'operating-points-v2-kryo-cpu' compatibility node
compatible string*

> for the Krait cores. Add support for 'operating-points-v2-krait-cpu'
> compatibility string.
> 
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>

Konrad
>  drivers/cpufreq/qcom-cpufreq-nvmem.c | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/cpufreq/qcom-cpufreq-nvmem.c b/drivers/cpufreq/qcom-cpufreq-nvmem.c
> index ab78ef1531d0..3bb552f498da 100644
> --- a/drivers/cpufreq/qcom-cpufreq-nvmem.c
> +++ b/drivers/cpufreq/qcom-cpufreq-nvmem.c
> @@ -238,7 +238,8 @@ static int qcom_cpufreq_probe(struct platform_device *pdev)
>  	if (!np)
>  		return -ENOENT;
>  
> -	ret = of_device_is_compatible(np, "operating-points-v2-kryo-cpu");
> +	ret = of_device_is_compatible(np, "operating-points-v2-kryo-cpu") ||
> +	      of_device_is_compatible(np, "operating-points-v2-krait-cpu");
>  	if (!ret) {
>  		of_node_put(np);
>  		return -ENOENT;

Re: [PATCH v2 11/26] cpufreq: qcom-nvmem: drop pvs_ver for format a fuses

[Konrad Dybcio]

On 25.06.2023 22:25, Dmitry Baryshkov wrote:
> The fuses used on msm8960 / apq8064 / ipq806x families of devices do not
> have the pvs version. Drop this argument from parsing function.
> 
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
>  drivers/cpufreq/qcom-cpufreq-nvmem.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/cpufreq/qcom-cpufreq-nvmem.c b/drivers/cpufreq/qcom-cpufreq-nvmem.c
> index 3bb552f498da..2a591fafc090 100644
> --- a/drivers/cpufreq/qcom-cpufreq-nvmem.c
> +++ b/drivers/cpufreq/qcom-cpufreq-nvmem.c
> @@ -50,7 +50,7 @@ struct qcom_cpufreq_drv {
>  static struct platform_device *cpufreq_dt_pdev, *cpufreq_pdev;
>  
>  static void get_krait_bin_format_a(struct device *cpu_dev,
> -					  int *speed, int *pvs, int *pvs_ver,
> +					  int *speed, int *pvs,
>  					  u8 *buf)
>  {
>  	u32 pte_efuse;
> @@ -181,7 +181,7 @@ static int qcom_cpufreq_krait_name_version(struct device *cpu_dev,
>  
>  	switch (len) {
>  	case 4:
> -		get_krait_bin_format_a(cpu_dev, &speed, &pvs, &pvs_ver,
> +		get_krait_bin_format_a(cpu_dev, &speed, &pvs,
>  				       speedbin);
Might have unwrapped this line while at it :P

Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>

Konrad
>  		break;
>  	case 8:

Re: [PATCH v2 14/26] ARM: dts: qcom: apq8064: rename SAW nodes to power-manager

[Konrad Dybcio]

On 25.06.2023 22:25, Dmitry Baryshkov wrote:
> Per the power-domain.yaml, the power-controller node name is reserved
> for power-domain providers. Rename SAW2 nodes to 'power-manager', the
> name which is suggested by qcom,spm.yaml
> 
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>

Konrad
>  arch/arm/boot/dts/qcom/qcom-apq8064.dtsi | 8 ++++----
>  1 file changed, 4 insertions(+), 4 deletions(-)
> 
> diff --git a/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi
> index d2289205ff81..471eeca6a589 100644
> --- a/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi
> +++ b/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi
> @@ -422,25 +422,25 @@ acc3: clock-controller@20b8000 {
>  			#clock-cells = <0>;
>  		};
>  
> -		saw0: power-controller@2089000 {
> +		saw0: power-manager@2089000 {
>  			compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
>  			reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
>  			regulator;
>  		};
>  
> -		saw1: power-controller@2099000 {
> +		saw1: power-manager@2099000 {
>  			compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
>  			reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
>  			regulator;
>  		};
>  
> -		saw2: power-controller@20a9000 {
> +		saw2: power-manager@20a9000 {
>  			compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
>  			reg = <0x020a9000 0x1000>, <0x02009000 0x1000>;
>  			regulator;
>  		};
>  
> -		saw3: power-controller@20b9000 {
> +		saw3: power-manager@20b9000 {
>  			compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
>  			reg = <0x020b9000 0x1000>, <0x02009000 0x1000>;
>  			regulator;

Re: [PATCH v2 15/26] ARM: dts: qcom: apq8064: declare SAW2 regulators

[Konrad Dybcio]

On 25.06.2023 22:25, Dmitry Baryshkov wrote:
> The SAW2 (SPM and AVS Wrapper) among other things is yet another way to
> handle CPU-related PMIC regulators. Provide a way to control voltage of
> these regulators.
> 
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>

Konrad
>  arch/arm/boot/dts/qcom/qcom-apq8064.dtsi | 24 ++++++++++++++++++++----
>  1 file changed, 20 insertions(+), 4 deletions(-)
> 
> diff --git a/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi
> index 471eeca6a589..1eb6d752ebae 100644
> --- a/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi
> +++ b/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi
> @@ -425,25 +425,41 @@ acc3: clock-controller@20b8000 {
>  		saw0: power-manager@2089000 {
>  			compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
>  			reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
> -			regulator;
> +
> +			saw0_vreg: regulator {
> +				regulator-min-microvolt = <850000>;
> +				regulator-max-microvolt = <1300000>;
> +			};
>  		};
>  
>  		saw1: power-manager@2099000 {
>  			compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
>  			reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
> -			regulator;
> +
> +			saw1_vreg: regulator {
> +				regulator-min-microvolt = <850000>;
> +				regulator-max-microvolt = <1300000>;
> +			};
>  		};
>  
>  		saw2: power-manager@20a9000 {
>  			compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
>  			reg = <0x020a9000 0x1000>, <0x02009000 0x1000>;
> -			regulator;
> +
> +			saw2_vreg: regulator {
> +				regulator-min-microvolt = <850000>;
> +				regulator-max-microvolt = <1300000>;
> +			};
>  		};
>  
>  		saw3: power-manager@20b9000 {
>  			compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
>  			reg = <0x020b9000 0x1000>, <0x02009000 0x1000>;
> -			regulator;
> +
> +			saw3_vreg: regulator {
> +				regulator-min-microvolt = <850000>;
> +				regulator-max-microvolt = <1300000>;
> +			};
>  		};
>  
>  		sps_sic_non_secure: sps-sic-non-secure@12100000 {

Re: [PATCH v2 09/26] cpufreq: qcom-nvmem: create L2 cache device

[Dmitry Baryshkov]

On 26/06/2023 14:50, Konrad Dybcio wrote:
> On 25.06.2023 22:25, Dmitry Baryshkov wrote:
>> Scaling the frequencies on some of Qualcomm Krait platforms (e.g.
>> APQ8064) also requires scaling of the L2 cache frequency. As the
>> l2-cache device node is places under /cpus/ path, it is not created by
>> default by the OF code. Create corresponding device here.
>>
>> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
>> ---
> I think a generic solution (i.e. for each cpu node call
> of_platform_populate in drivers/of/platform.c :
> of_platform_default_populate_init) could be beneficial

Yep. I thought about it, but I saw no direct benefit for it. Note, that 
we do not instantiate cpu devices directly. But, maybe something like 
/devices/system/cache/foo would make sense.

> 
> Konrad
>>   drivers/cpufreq/qcom-cpufreq-nvmem.c | 20 ++++++++++++++++++++
>>   1 file changed, 20 insertions(+)
>>
>> diff --git a/drivers/cpufreq/qcom-cpufreq-nvmem.c b/drivers/cpufreq/qcom-cpufreq-nvmem.c
>> index a88b6fe5db50..ab78ef1531d0 100644
>> --- a/drivers/cpufreq/qcom-cpufreq-nvmem.c
>> +++ b/drivers/cpufreq/qcom-cpufreq-nvmem.c
>> @@ -380,6 +380,7 @@ static int __init qcom_cpufreq_init(void)
>>   {
>>   	struct device_node *np = of_find_node_by_path("/");
>>   	const struct of_device_id *match;
>> +	unsigned int cpu;
>>   	int ret;
>>   
>>   	if (!np)
>> @@ -390,6 +391,25 @@ static int __init qcom_cpufreq_init(void)
>>   	if (!match)
>>   		return -ENODEV;
>>   
>> +	for_each_possible_cpu(cpu) {
>> +		struct device *dev = get_cpu_device(cpu);
>> +		struct device_node *cache;
>> +		struct platform_device *pdev;
>> +
>> +		cache = of_find_next_cache_node(dev->of_node);
>> +		if (!cache)
>> +			continue;
>> +
>> +		if (of_device_is_compatible(cache, "qcom,krait-l2-cache")) {
>> +			pdev = of_platform_device_create(cache, NULL, NULL);
>> +			if (IS_ERR(pdev))
>> +				pr_err("%s: %pe, failed to create L2 cache node\n", __func__, pdev);
>> +			/* the error is not fatal */
>> +		}
>> +
>> +		of_node_put(cache);
>> +	}
>> +
>>   	ret = platform_driver_register(&qcom_cpufreq_driver);
>>   	if (unlikely(ret < 0))
>>   		return ret;

-- 
With best wishes
Dmitry

Re: [PATCH v2 04/26] dt-bindings: clock: qcom,krait-cc: Krait core clock controller

[Dmitry Baryshkov]

On 26/06/2023 14:21, Konrad Dybcio wrote:
> On 25.06.2023 22:25, Dmitry Baryshkov wrote:
>> Define bindings for the Qualcomm Krait CPU and L2 clock controller. This
>> device is used on old Qualcomm SoCs (APQ8064, MSM8960) and supports up
>> to 4 core clocks and a separate L2 clock. Furthermore, L2 clock is
>> represented as the interconnect to facilitate L2 frequency scaling
>> together with scaling the CPU frequencies.
>>
>> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
>> ---
> Worth noting that there's no Krait cluster containing more than 4
> cores and the last SoC using this uarch was released 10y ago, so
> we can quite confidently say that the max cpu no won't change.

Yep. It it were new bindings, I'd probably use a different order: L2, 
then CPUs. But here I'm just documenting what is already done by the driver.

> 
> Konrad
>>   include/dt-bindings/clock/qcom,krait-cc.h | 17 +++++++++++++++++
>>   1 file changed, 17 insertions(+)
>>   create mode 100644 include/dt-bindings/clock/qcom,krait-cc.h
>>
>> diff --git a/include/dt-bindings/clock/qcom,krait-cc.h b/include/dt-bindings/clock/qcom,krait-cc.h
>> new file mode 100644
>> index 000000000000..ff69a0a968d8
>> --- /dev/null
>> +++ b/include/dt-bindings/clock/qcom,krait-cc.h
>> @@ -0,0 +1,17 @@
>> +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
>> +/*
>> + * Copyright (C) 2023 Linaro Ltd. All rights reserved.
>> + */
>> +
>> +#ifndef __DT_BINDINGS_CLOCK_QCOM_KRAIT_CC_H
>> +#define __DT_BINDINGS_CLOCK_QCOM_KRAIT_CC_H
>> +
>> +#define KRAIT_CPU_0		0
>> +#define KRAIT_CPU_1		1
>> +#define KRAIT_CPU_2		2
>> +#define KRAIT_CPU_3		3
>> +#define KRAIT_L2		4
>> +
>> +#define KRAIT_NUM_CLOCKS	5
>> +
>> +#endif

-- 
With best wishes
Dmitry

Re: [PATCH v2 06/26] interconnect: icc-clk: add support for scaling using OPP

[Dmitry Baryshkov]

On 26/06/2023 14:28, Konrad Dybcio wrote:
> On 25.06.2023 22:25, Dmitry Baryshkov wrote:
>> Sometimes it might be required to scale the clock using the OPP
>> framework (e.g. to scale regulators following the required clock rate).
>> Extend the interconnec
> 't'
> 
>> -clk framework to handle OPP case in addition to
>> scaling the clock.
>>
>> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
>> ---
> I think we should check for OPP at the icc-clk registration time,
> instead of passing it as a parameter, e.g.:
> 
> qn.opp = IS_ERR(dev_pm_opp_get_opp_count)
> 
> Not sure if there's a more idiomatic way.

No. icc-clk is not limited to a single clock->icc conversion. So it is 
possible to create several interconnect links, only one of which should 
be the OPP-based one.

> 
> Konrad
>>   drivers/interconnect/icc-clk.c   | 13 +++++++++++--
>>   include/linux/interconnect-clk.h |  1 +
>>   2 files changed, 12 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/interconnect/icc-clk.c b/drivers/interconnect/icc-clk.c
>> index 4d43ebff4257..c7962acdcee7 100644
>> --- a/drivers/interconnect/icc-clk.c
>> +++ b/drivers/interconnect/icc-clk.c
>> @@ -7,10 +7,13 @@
>>   #include <linux/device.h>
>>   #include <linux/interconnect-clk.h>
>>   #include <linux/interconnect-provider.h>
>> +#include <linux/pm_opp.h>
>>   
>>   struct icc_clk_node {
>> +	struct device *dev;
>>   	struct clk *clk;
>>   	bool enabled;
>> +	bool opp;
>>   };
>>   
>>   struct icc_clk_provider {
>> @@ -25,12 +28,16 @@ struct icc_clk_provider {
>>   static int icc_clk_set(struct icc_node *src, struct icc_node *dst)
>>   {
>>   	struct icc_clk_node *qn = src->data;
>> +	unsigned long rate = icc_units_to_bps(src->peak_bw);
>>   	int ret;
>>   
>>   	if (!qn || !qn->clk)
>>   		return 0;
>>   
>> -	if (!src->peak_bw) {
>> +	if (qn->opp)
>> +		return dev_pm_opp_set_rate(qn->dev, rate);
>> +
>> +	if (!rate) {
>>   		if (qn->enabled)
>>   			clk_disable_unprepare(qn->clk);
>>   		qn->enabled = false;
>> @@ -45,7 +52,7 @@ static int icc_clk_set(struct icc_node *src, struct icc_node *dst)
>>   		qn->enabled = true;
>>   	}
>>   
>> -	return clk_set_rate(qn->clk, icc_units_to_bps(src->peak_bw));
>> +	return clk_set_rate(qn->clk, rate);
>>   }
>>   
>>   static int icc_clk_get_bw(struct icc_node *node, u32 *avg, u32 *peak)
>> @@ -106,7 +113,9 @@ struct icc_provider *icc_clk_register(struct device *dev,
>>   	icc_provider_init(provider);
>>   
>>   	for (i = 0, j = 0; i < num_clocks; i++) {
>> +		qp->clocks[i].dev = dev;
>>   		qp->clocks[i].clk = data[i].clk;
>> +		qp->clocks[i].opp = data[i].opp;
>>   
>>   		node = icc_node_create(first_id + j);
>>   		if (IS_ERR(node)) {
>> diff --git a/include/linux/interconnect-clk.h b/include/linux/interconnect-clk.h
>> index 0cd80112bea5..c695e5099901 100644
>> --- a/include/linux/interconnect-clk.h
>> +++ b/include/linux/interconnect-clk.h
>> @@ -11,6 +11,7 @@ struct device;
>>   struct icc_clk_data {
>>   	struct clk *clk;
>>   	const char *name;
>> +	bool opp;
>>   };
>>   
>>   struct icc_provider *icc_clk_register(struct device *dev,

-- 
With best wishes
Dmitry

Re: [PATCH v2 08/26] soc: qcom: spm: add support for voltage regulator

[Dmitry Baryshkov]

On 26/06/2023 14:47, Konrad Dybcio wrote:
> On 25.06.2023 22:25, Dmitry Baryshkov wrote:
>> The SPM / SAW2 device also provides a voltage regulator functionality
>> with optional AVS (Adaptive Voltage Scaling) support. The exact register
>> sequence and voltage ranges differs from device to device.
>>
>> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
>> ---
>>   drivers/soc/qcom/spm.c | 205 ++++++++++++++++++++++++++++++++++++++++-
>>   include/soc/qcom/spm.h |   9 ++
>>   2 files changed, 212 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/soc/qcom/spm.c b/drivers/soc/qcom/spm.c
>> index a6cbeb40831b..3c16a7e1710c 100644
>> --- a/drivers/soc/qcom/spm.c
>> +++ b/drivers/soc/qcom/spm.c
>> @@ -9,19 +9,31 @@
>>   #include <linux/kernel.h>
>>   #include <linux/init.h>
>>   #include <linux/io.h>
>> +#include <linux/iopoll.h>
>> +#include <linux/linear_range.h>
>>   #include <linux/module.h>
>>   #include <linux/slab.h>
>>   #include <linux/of.h>
>>   #include <linux/of_address.h>
>>   #include <linux/of_device.h>
>> +#include <linux/bitfield.h>
> This addition is very out-of-order

The whole list is out of order. Proably I should sort it first

> 
>>   #include <linux/err.h>
>>   #include <linux/platform_device.h>
>> +#include <linux/regulator/driver.h>
>> +#include <linux/smp.h>
>>   #include <soc/qcom/spm.h>
>>   
>> +#define FIELD_SET(current, mask, val)	\
>> +	(((current) & ~(mask)) | FIELD_PREP((mask), (val)))
>> +
>>   #define SPM_CTL_INDEX		0x7f
>>   #define SPM_CTL_INDEX_SHIFT	4
>>   #define SPM_CTL_EN		BIT(0)
>>   
>> +#define SPM_1_1_AVS_CTL_AVS_ENABLED BIT(27)
>> +#define SPM_AVS_CTL_MIN_VLVL	(0x3f << 10)
>> +#define SPM_AVS_CTL_MAX_VLVL	(0x3f << 17)
> GENMASK

ack

> 
>> +
>>   enum spm_reg {
>>   	SPM_REG_CFG,
>>   	SPM_REG_SPM_CTL,
>> @@ -31,10 +43,12 @@ enum spm_reg {
>>   	SPM_REG_PMIC_DATA_1,
>>   	SPM_REG_VCTL,
>>   	SPM_REG_SEQ_ENTRY,
>> -	SPM_REG_SPM_STS,
>> +	SPM_REG_STS0,
>> +	SPM_REG_STS1,
>>   	SPM_REG_PMIC_STS,
>>   	SPM_REG_AVS_CTL,
>>   	SPM_REG_AVS_LIMIT,
>> +	SPM_REG_RST,
>>   	SPM_REG_NR,
>>   };
>>   
>> @@ -171,6 +185,10 @@ static const struct spm_reg_data spm_reg_8226_cpu  = {
>>   
>>   static const u16 spm_reg_offset_v1_1[SPM_REG_NR] = {
>>   	[SPM_REG_CFG]		= 0x08,
>> +	[SPM_REG_STS0]		= 0x0c,
>> +	[SPM_REG_STS1]		= 0x10,
>> +	[SPM_REG_VCTL]		= 0x14,
>> +	[SPM_REG_AVS_CTL]	= 0x18,
>>   	[SPM_REG_SPM_CTL]	= 0x20,
>>   	[SPM_REG_PMIC_DLY]	= 0x24,
>>   	[SPM_REG_PMIC_DATA_0]	= 0x28,
>> @@ -178,7 +196,12 @@ static const u16 spm_reg_offset_v1_1[SPM_REG_NR] = {
>>   	[SPM_REG_SEQ_ENTRY]	= 0x80,
>>   };
>>   
>> +static void smp_set_vdd_v1_1(void *data);
>> +
>>   /* SPM register data for 8064 */
>> +static struct linear_range spm_v1_1_regulator_range =
>> +	REGULATOR_LINEAR_RANGE(700000, 0, 56, 12500);
>> +
>>   static const struct spm_reg_data spm_reg_8064_cpu = {
>>   	.reg_offset = spm_reg_offset_v1_1,
>>   	.spm_cfg = 0x1F,
>> @@ -189,6 +212,10 @@ static const struct spm_reg_data spm_reg_8064_cpu = {
>>   		0x10, 0x54, 0x30, 0x0C, 0x24, 0x30, 0x0F },
>>   	.start_index[PM_SLEEP_MODE_STBY] = 0,
>>   	.start_index[PM_SLEEP_MODE_SPC] = 2,
>> +	.set_vdd = smp_set_vdd_v1_1,
>> +	.range = &spm_v1_1_regulator_range,
>> +	.init_uV = 1300000,
>> +	.ramp_delay = 1250,
>>   };
>>   
>>   static inline void spm_register_write(struct spm_driver_data *drv,
>> @@ -240,6 +267,179 @@ void spm_set_low_power_mode(struct spm_driver_data *drv,
>>   	spm_register_write_sync(drv, SPM_REG_SPM_CTL, ctl_val);
>>   }
>>   
>> +static int spm_set_voltage_sel(struct regulator_dev *rdev, unsigned int selector)
>> +{
>> +	struct spm_driver_data *drv = rdev_get_drvdata(rdev);
>> +
>> +	drv->volt_sel = selector;
>> +
>> +	/* Always do the SAW register writes on the corresponding CPU */
>> +	return smp_call_function_single(drv->reg_cpu, drv->reg_data->set_vdd, drv, true);
>> +}
>> +
>> +static int spm_get_voltage_sel(struct regulator_dev *rdev)
>> +{
>> +	struct spm_driver_data *drv = rdev_get_drvdata(rdev);
>> +
>> +	return drv->volt_sel;
>> +}
>> +
>> +static const struct regulator_ops spm_reg_ops = {
>> +	.set_voltage_sel	= spm_set_voltage_sel,
>> +	.get_voltage_sel	= spm_get_voltage_sel,
>> +	.list_voltage		= regulator_list_voltage_linear_range,
>> +	.set_voltage_time_sel	= regulator_set_voltage_time_sel,
>> +};
>> +
>> +static void smp_set_vdd_v1_1(void *data)
>> +{
>> +	struct spm_driver_data *drv = data;
>> +	unsigned int vlevel = drv->volt_sel;
>> +	unsigned int vctl, data0, data1, avs_ctl, sts;
>> +	bool avs_enabled;
> Reverse-Christmas-tree?
> 
>> +
>> +	vlevel |= 0x80; /* band */
> That's conveniently 1<<7.. do we know if it's a significant number
> or just a bit that does something within that field?

More like 2 << 6. A bit of the issue is that PMIC_DATA_n format is 
PMIC-specific. I'll see what I can do here.

> 
>> +
>> +	avs_ctl = spm_register_read(drv, SPM_REG_AVS_CTL);
>> +	vctl = spm_register_read(drv, SPM_REG_VCTL);
>> +	data0 = spm_register_read(drv, SPM_REG_PMIC_DATA_0);
>> +	data1 = spm_register_read(drv, SPM_REG_PMIC_DATA_1);
>> +
>> +	avs_enabled = avs_ctl & SPM_1_1_AVS_CTL_AVS_ENABLED;
>> +
>> +	/* If AVS is enabled, switch it off during the voltage change */
>> +	if (avs_enabled) {
>> +		avs_ctl &= ~SPM_1_1_AVS_CTL_AVS_ENABLED;
>> +		spm_register_write(drv, SPM_REG_AVS_CTL, avs_ctl);
>> +	}
>> +
>> +	/* Kick the state machine back to idle */
>> +	spm_register_write(drv, SPM_REG_RST, 1);
>> +
>> +	vctl = FIELD_SET(vctl, 0xff, vlevel);
>> +	data0 = FIELD_SET(data0, 0xff, vlevel);
>> +	data1 = FIELD_SET(data1, 0x3f, vlevel);
>> +	data1 = FIELD_SET(data1, 0x3f << 16, vlevel);
> GENMASK
> 
>> +
>> +	spm_register_write(drv, SPM_REG_VCTL, vctl);
>> +	spm_register_write(drv, SPM_REG_PMIC_DATA_0, data0);
>> +	spm_register_write(drv, SPM_REG_PMIC_DATA_1, data1);
>> +
>> +	if (read_poll_timeout_atomic(spm_register_read,
>> +				      sts, sts == vlevel,
>> +				      1, 200, false,
>> +				      drv, SPM_REG_STS1)) {
> Not sure if misaligned or thunderfox is acting up again

off-by-one, I'll fix it.

> 
>> +		dev_err_ratelimited(drv->dev, "timeout setting the voltage (%x %x)!\n", sts, vlevel);
>> +		goto enable_avs;
>> +	}
>> +
>> +	if (avs_enabled) {
>> +		unsigned int max_avs = vlevel & 0x3f;
> GENMASK
> 
>> +		unsigned int min_avs = max(max_avs, 4U) - 4;
> So it's 0 or >= (1<<31 - 4)?
> 
>> +		avs_ctl = FIELD_SET(avs_ctl, SPM_AVS_CTL_MIN_VLVL, min_avs);
>> +		avs_ctl = FIELD_SET(avs_ctl, SPM_AVS_CTL_MAX_VLVL, max_avs);
>> +		spm_register_write(drv, SPM_REG_AVS_CTL, avs_ctl);
>> +	}
>> +
>> +enable_avs:
>> +	if (avs_enabled) {
>> +		avs_ctl |= SPM_1_1_AVS_CTL_AVS_ENABLED;
>> +		spm_register_write(drv, SPM_REG_AVS_CTL, avs_ctl);
>> +	}
>> +}
>> +
>> +static int spm_get_cpu(struct device *dev)
>> +{
>> +	int cpu;
>> +	bool found;
> Reverse-Christmas-tree?
> 
>> +
>> +	for_each_possible_cpu(cpu) {
>> +		struct device_node *cpu_node, *saw_node;
> As long as Linux is running, there should be at least one CPU up,
> so this always gets entered, perhaps the definitions could be moved
> to the main function body

Huh, I'm not sure that I got you correct here. Do you mean movign 
cpu_node and saw_node to the top of spm_get_cpu()?

> 
>> +
>> +		cpu_node = of_cpu_device_node_get(cpu);
>> +		if (!cpu_node)
>> +			continue;
>> +
>> +		saw_node = of_parse_phandle(cpu_node, "qcom,saw", 0);
>> +		found = (saw_node == dev->of_node);
> The error checking here works out, but it's a bit cryptic.. Though
> I'm not opposed to saving 3 cycles on slow and old CPUs :D

It's not the error checking per se. We have to put both nodes before 
returning.

So an alternative might me:

saw_node = ...
if (saw_node == cpu_node) {
     of_node_put(saw_node);
     of_node_put(cpu_node);
     return cpu;
}

of_node_put(saw_node);
of_node_put(cpu_node);

But it looks worse to me. Did you mean this kind of code or was 
something else on your mind?

> 
>> +		of_node_put(saw_node);
>> +		of_node_put(cpu_node);
>> +
>> +		if (found)
>> +			return cpu;
>> +	}
>> +
>> +	/* L2 SPM is not bound to any CPU, tie it to CPU0 */
>> +
>> +	return 0;
>> +}
>> +
>> +#ifdef CONFIG_REGULATOR
>> +static int spm_register_regulator(struct device *dev, struct spm_driver_data *drv)
>> +{
>> +	struct regulator_config config = {
>> +		.dev = dev,
>> +		.driver_data = drv,
>> +	};
>> +	struct regulator_desc *rdesc;
>> +	struct regulator_dev *rdev;
>> +	int ret;
>> +	bool found;
> Reverse-Christmas-tree?
> 
> Konrad
>> +
>> +	if (!drv->reg_data->set_vdd)
>> +		return 0;
>> +
>> +	rdesc = devm_kzalloc(dev, sizeof(*rdesc), GFP_KERNEL);
>> +	if (!rdesc)
>> +		return -ENOMEM;
>> +
>> +	rdesc->name = "spm";
>> +	rdesc->of_match = of_match_ptr("regulator");
>> +	rdesc->type = REGULATOR_VOLTAGE;
>> +	rdesc->owner = THIS_MODULE;
>> +	rdesc->ops = &spm_reg_ops;
>> +
>> +	rdesc->linear_ranges = drv->reg_data->range;
>> +	rdesc->n_linear_ranges = 1;
>> +	rdesc->n_voltages = rdesc->linear_ranges[rdesc->n_linear_ranges - 1].max_sel + 1;
>> +	rdesc->ramp_delay = drv->reg_data->ramp_delay;
>> +
>> +	drv->reg_cpu = spm_get_cpu(dev);
>> +	dev_dbg(dev, "SAW2 bound to CPU %d\n", drv->reg_cpu);
>> +
>> +	/*
>> +	 * Program initial voltage, otherwise registration will also try
>> +	 * setting the voltage, which might result in undervolting the CPU.
>> +	 */
>> +	drv->volt_sel = DIV_ROUND_UP(drv->reg_data->init_uV - rdesc->min_uV,
>> +				     rdesc->uV_step);
>> +	ret = linear_range_get_selector_high(drv->reg_data->range,
>> +					     drv->reg_data->init_uV,
>> +					     &drv->volt_sel,
>> +					     &found);
>> +	if (ret) {
>> +		dev_err(dev, "Initial uV value out of bounds\n");
>> +		return ret;
>> +	}
>> +
>> +	/* Always do the SAW register writes on the corresponding CPU */
>> +	smp_call_function_single(drv->reg_cpu, drv->reg_data->set_vdd, drv, true);
>> +
>> +	rdev = devm_regulator_register(dev, rdesc, &config);
>> +	if (IS_ERR(rdev)) {
>> +		dev_err(dev, "failed to register regulator\n");
>> +		return PTR_ERR(rdev);
>> +	}
>> +
>> +	return 0;
>> +}
>> +#else
>> +static int spm_register_regulator(struct device *dev, struct spm_driver_data *drv)
>> +{
>> +	return 0;
>> +}
>> +#endif
>> +
>>   static const struct of_device_id spm_match_table[] = {
>>   	{ .compatible = "qcom,sdm660-gold-saw2-v4.1-l2",
>>   	  .data = &spm_reg_660_gold_l2 },
>> @@ -292,6 +492,7 @@ static int spm_dev_probe(struct platform_device *pdev)
>>   		return -ENODEV;
>>   
>>   	drv->reg_data = match_id->data;
>> +	drv->dev = &pdev->dev;
>>   	platform_set_drvdata(pdev, drv);
>>   
>>   	/* Write the SPM sequences first.. */
>> @@ -319,7 +520,7 @@ static int spm_dev_probe(struct platform_device *pdev)
>>   	if (drv->reg_data->reg_offset[SPM_REG_SPM_CTL])
>>   		spm_set_low_power_mode(drv, PM_SLEEP_MODE_STBY);
>>   
>> -	return 0;
>> +	return spm_register_regulator(&pdev->dev, drv);
>>   }
>>   
>>   static struct platform_driver spm_driver = {
>> diff --git a/include/soc/qcom/spm.h b/include/soc/qcom/spm.h
>> index 4951f9d8b0bd..9859ebe42003 100644
>> --- a/include/soc/qcom/spm.h
>> +++ b/include/soc/qcom/spm.h
>> @@ -30,11 +30,20 @@ struct spm_reg_data {
>>   	u32 avs_limit;
>>   	u8 seq[MAX_SEQ_DATA];
>>   	u8 start_index[PM_SLEEP_MODE_NR];
>> +
>> +	smp_call_func_t set_vdd;
>> +	/* for now we support only a single range */
>> +	struct linear_range *range;
>> +	unsigned int ramp_delay;
>> +	unsigned int init_uV;
>>   };
>>   
>>   struct spm_driver_data {
>>   	void __iomem *reg_base;
>>   	const struct spm_reg_data *reg_data;
>> +	struct device *dev;
>> +	unsigned int volt_sel;
>> +	int reg_cpu;
>>   };
>>   
>>   void spm_set_low_power_mode(struct spm_driver_data *drv,

-- 
With best wishes
Dmitry

Re: [PATCH v2 08/26] soc: qcom: spm: add support for voltage regulator

[Konrad Dybcio]

On 26.06.2023 15:53, Dmitry Baryshkov wrote:
> On 26/06/2023 14:47, Konrad Dybcio wrote:
>> On 25.06.2023 22:25, Dmitry Baryshkov wrote:
>>> The SPM / SAW2 device also provides a voltage regulator functionality
>>> with optional AVS (Adaptive Voltage Scaling) support. The exact register
>>> sequence and voltage ranges differs from device to device.
>>>
>>> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
>>> ---
>>>   drivers/soc/qcom/spm.c | 205 ++++++++++++++++++++++++++++++++++++++++-
>>>   include/soc/qcom/spm.h |   9 ++
>>>   2 files changed, 212 insertions(+), 2 deletions(-)
>>>
>>> diff --git a/drivers/soc/qcom/spm.c b/drivers/soc/qcom/spm.c
>>> index a6cbeb40831b..3c16a7e1710c 100644
>>> --- a/drivers/soc/qcom/spm.c
>>> +++ b/drivers/soc/qcom/spm.c
>>> @@ -9,19 +9,31 @@
>>>   #include <linux/kernel.h>
>>>   #include <linux/init.h>
>>>   #include <linux/io.h>
>>> +#include <linux/iopoll.h>
>>> +#include <linux/linear_range.h>
>>>   #include <linux/module.h>
>>>   #include <linux/slab.h>
>>>   #include <linux/of.h>
>>>   #include <linux/of_address.h>
>>>   #include <linux/of_device.h>
>>> +#include <linux/bitfield.h>
>> This addition is very out-of-order
> 
> The whole list is out of order. Proably I should sort it first
> 
>>
>>>   #include <linux/err.h>
>>>   #include <linux/platform_device.h>
>>> +#include <linux/regulator/driver.h>
>>> +#include <linux/smp.h>
>>>   #include <soc/qcom/spm.h>
>>>   +#define FIELD_SET(current, mask, val)    \
>>> +    (((current) & ~(mask)) | FIELD_PREP((mask), (val)))
>>> +
>>>   #define SPM_CTL_INDEX        0x7f
>>>   #define SPM_CTL_INDEX_SHIFT    4
>>>   #define SPM_CTL_EN        BIT(0)
>>>   +#define SPM_1_1_AVS_CTL_AVS_ENABLED BIT(27)
>>> +#define SPM_AVS_CTL_MIN_VLVL    (0x3f << 10)
>>> +#define SPM_AVS_CTL_MAX_VLVL    (0x3f << 17)
>> GENMASK
> 
> ack
> 
>>
>>> +
>>>   enum spm_reg {
>>>       SPM_REG_CFG,
>>>       SPM_REG_SPM_CTL,
>>> @@ -31,10 +43,12 @@ enum spm_reg {
>>>       SPM_REG_PMIC_DATA_1,
>>>       SPM_REG_VCTL,
>>>       SPM_REG_SEQ_ENTRY,
>>> -    SPM_REG_SPM_STS,
>>> +    SPM_REG_STS0,
>>> +    SPM_REG_STS1,
>>>       SPM_REG_PMIC_STS,
>>>       SPM_REG_AVS_CTL,
>>>       SPM_REG_AVS_LIMIT,
>>> +    SPM_REG_RST,
>>>       SPM_REG_NR,
>>>   };
>>>   @@ -171,6 +185,10 @@ static const struct spm_reg_data spm_reg_8226_cpu  = {
>>>     static const u16 spm_reg_offset_v1_1[SPM_REG_NR] = {
>>>       [SPM_REG_CFG]        = 0x08,
>>> +    [SPM_REG_STS0]        = 0x0c,
>>> +    [SPM_REG_STS1]        = 0x10,
>>> +    [SPM_REG_VCTL]        = 0x14,
>>> +    [SPM_REG_AVS_CTL]    = 0x18,
>>>       [SPM_REG_SPM_CTL]    = 0x20,
>>>       [SPM_REG_PMIC_DLY]    = 0x24,
>>>       [SPM_REG_PMIC_DATA_0]    = 0x28,
>>> @@ -178,7 +196,12 @@ static const u16 spm_reg_offset_v1_1[SPM_REG_NR] = {
>>>       [SPM_REG_SEQ_ENTRY]    = 0x80,
>>>   };
>>>   +static void smp_set_vdd_v1_1(void *data);
>>> +
>>>   /* SPM register data for 8064 */
>>> +static struct linear_range spm_v1_1_regulator_range =
>>> +    REGULATOR_LINEAR_RANGE(700000, 0, 56, 12500);
>>> +
>>>   static const struct spm_reg_data spm_reg_8064_cpu = {
>>>       .reg_offset = spm_reg_offset_v1_1,
>>>       .spm_cfg = 0x1F,
>>> @@ -189,6 +212,10 @@ static const struct spm_reg_data spm_reg_8064_cpu = {
>>>           0x10, 0x54, 0x30, 0x0C, 0x24, 0x30, 0x0F },
>>>       .start_index[PM_SLEEP_MODE_STBY] = 0,
>>>       .start_index[PM_SLEEP_MODE_SPC] = 2,
>>> +    .set_vdd = smp_set_vdd_v1_1,
>>> +    .range = &spm_v1_1_regulator_range,
>>> +    .init_uV = 1300000,
>>> +    .ramp_delay = 1250,
>>>   };
>>>     static inline void spm_register_write(struct spm_driver_data *drv,
>>> @@ -240,6 +267,179 @@ void spm_set_low_power_mode(struct spm_driver_data *drv,
>>>       spm_register_write_sync(drv, SPM_REG_SPM_CTL, ctl_val);
>>>   }
>>>   +static int spm_set_voltage_sel(struct regulator_dev *rdev, unsigned int selector)
>>> +{
>>> +    struct spm_driver_data *drv = rdev_get_drvdata(rdev);
>>> +
>>> +    drv->volt_sel = selector;
>>> +
>>> +    /* Always do the SAW register writes on the corresponding CPU */
>>> +    return smp_call_function_single(drv->reg_cpu, drv->reg_data->set_vdd, drv, true);
>>> +}
>>> +
>>> +static int spm_get_voltage_sel(struct regulator_dev *rdev)
>>> +{
>>> +    struct spm_driver_data *drv = rdev_get_drvdata(rdev);
>>> +
>>> +    return drv->volt_sel;
>>> +}
>>> +
>>> +static const struct regulator_ops spm_reg_ops = {
>>> +    .set_voltage_sel    = spm_set_voltage_sel,
>>> +    .get_voltage_sel    = spm_get_voltage_sel,
>>> +    .list_voltage        = regulator_list_voltage_linear_range,
>>> +    .set_voltage_time_sel    = regulator_set_voltage_time_sel,
>>> +};
>>> +
>>> +static void smp_set_vdd_v1_1(void *data)
>>> +{
>>> +    struct spm_driver_data *drv = data;
>>> +    unsigned int vlevel = drv->volt_sel;
>>> +    unsigned int vctl, data0, data1, avs_ctl, sts;
>>> +    bool avs_enabled;
>> Reverse-Christmas-tree?
>>
>>> +
>>> +    vlevel |= 0x80; /* band */
>> That's conveniently 1<<7.. do we know if it's a significant number
>> or just a bit that does something within that field?
> 
> More like 2 << 6. A bit of the issue is that PMIC_DATA_n format is PMIC-specific. I'll see what I can do here.
> 
>>
>>> +
>>> +    avs_ctl = spm_register_read(drv, SPM_REG_AVS_CTL);
>>> +    vctl = spm_register_read(drv, SPM_REG_VCTL);
>>> +    data0 = spm_register_read(drv, SPM_REG_PMIC_DATA_0);
>>> +    data1 = spm_register_read(drv, SPM_REG_PMIC_DATA_1);
>>> +
>>> +    avs_enabled = avs_ctl & SPM_1_1_AVS_CTL_AVS_ENABLED;
>>> +
>>> +    /* If AVS is enabled, switch it off during the voltage change */
>>> +    if (avs_enabled) {
>>> +        avs_ctl &= ~SPM_1_1_AVS_CTL_AVS_ENABLED;
>>> +        spm_register_write(drv, SPM_REG_AVS_CTL, avs_ctl);
>>> +    }
>>> +
>>> +    /* Kick the state machine back to idle */
>>> +    spm_register_write(drv, SPM_REG_RST, 1);
>>> +
>>> +    vctl = FIELD_SET(vctl, 0xff, vlevel);
>>> +    data0 = FIELD_SET(data0, 0xff, vlevel);
>>> +    data1 = FIELD_SET(data1, 0x3f, vlevel);
>>> +    data1 = FIELD_SET(data1, 0x3f << 16, vlevel);
>> GENMASK
>>
>>> +
>>> +    spm_register_write(drv, SPM_REG_VCTL, vctl);
>>> +    spm_register_write(drv, SPM_REG_PMIC_DATA_0, data0);
>>> +    spm_register_write(drv, SPM_REG_PMIC_DATA_1, data1);
>>> +
>>> +    if (read_poll_timeout_atomic(spm_register_read,
>>> +                      sts, sts == vlevel,
>>> +                      1, 200, false,
>>> +                      drv, SPM_REG_STS1)) {
>> Not sure if misaligned or thunderfox is acting up again
> 
> off-by-one, I'll fix it.
> 
>>
>>> +        dev_err_ratelimited(drv->dev, "timeout setting the voltage (%x %x)!\n", sts, vlevel);
>>> +        goto enable_avs;
>>> +    }
>>> +
>>> +    if (avs_enabled) {
>>> +        unsigned int max_avs = vlevel & 0x3f;
>> GENMASK
>>
>>> +        unsigned int min_avs = max(max_avs, 4U) - 4;
>> So it's 0 or >= (1<<31 - 4)?
>>
>>> +        avs_ctl = FIELD_SET(avs_ctl, SPM_AVS_CTL_MIN_VLVL, min_avs);
>>> +        avs_ctl = FIELD_SET(avs_ctl, SPM_AVS_CTL_MAX_VLVL, max_avs);
>>> +        spm_register_write(drv, SPM_REG_AVS_CTL, avs_ctl);
>>> +    }
>>> +
>>> +enable_avs:
>>> +    if (avs_enabled) {
>>> +        avs_ctl |= SPM_1_1_AVS_CTL_AVS_ENABLED;
>>> +        spm_register_write(drv, SPM_REG_AVS_CTL, avs_ctl);
>>> +    }
>>> +}
>>> +
>>> +static int spm_get_cpu(struct device *dev)
>>> +{
>>> +    int cpu;
>>> +    bool found;
>> Reverse-Christmas-tree?
>>
>>> +
>>> +    for_each_possible_cpu(cpu) {
>>> +        struct device_node *cpu_node, *saw_node;
>> As long as Linux is running, there should be at least one CPU up,
>> so this always gets entered, perhaps the definitions could be moved
>> to the main function body
> 
> Huh, I'm not sure that I got you correct here. Do you mean movign cpu_node and saw_node to the top of spm_get_cpu()?
Yes

> 
>>
>>> +
>>> +        cpu_node = of_cpu_device_node_get(cpu);
>>> +        if (!cpu_node)
>>> +            continue;
>>> +
>>> +        saw_node = of_parse_phandle(cpu_node, "qcom,saw", 0);
>>> +        found = (saw_node == dev->of_node);
>> The error checking here works out, but it's a bit cryptic.. Though
>> I'm not opposed to saving 3 cycles on slow and old CPUs :D
> 
> It's not the error checking per se. We have to put both nodes before returning.
> 
> So an alternative might me:
> 
> saw_node = ...
> if (saw_node == cpu_node) {
>     of_node_put(saw_node);
>     of_node_put(cpu_node);
>     return cpu;
> }
> 
> of_node_put(saw_node);
> of_node_put(cpu_node);
> 
> But it looks worse to me. Did you mean this kind of code or was something else on your mind?
I was basically thinking that there's no explicit if (ret < 0) or whatever
but the code from this patch also works, so let's keep it as-is

Konrad
> 
>>
>>> +        of_node_put(saw_node);
>>> +        of_node_put(cpu_node);
>>> +
>>> +        if (found)
>>> +            return cpu;
>>> +    }
>>> +
>>> +    /* L2 SPM is not bound to any CPU, tie it to CPU0 */
>>> +
>>> +    return 0;
>>> +}
>>> +
>>> +#ifdef CONFIG_REGULATOR
>>> +static int spm_register_regulator(struct device *dev, struct spm_driver_data *drv)
>>> +{
>>> +    struct regulator_config config = {
>>> +        .dev = dev,
>>> +        .driver_data = drv,
>>> +    };
>>> +    struct regulator_desc *rdesc;
>>> +    struct regulator_dev *rdev;
>>> +    int ret;
>>> +    bool found;
>> Reverse-Christmas-tree?
>>
>> Konrad
>>> +
>>> +    if (!drv->reg_data->set_vdd)
>>> +        return 0;
>>> +
>>> +    rdesc = devm_kzalloc(dev, sizeof(*rdesc), GFP_KERNEL);
>>> +    if (!rdesc)
>>> +        return -ENOMEM;
>>> +
>>> +    rdesc->name = "spm";
>>> +    rdesc->of_match = of_match_ptr("regulator");
>>> +    rdesc->type = REGULATOR_VOLTAGE;
>>> +    rdesc->owner = THIS_MODULE;
>>> +    rdesc->ops = &spm_reg_ops;
>>> +
>>> +    rdesc->linear_ranges = drv->reg_data->range;
>>> +    rdesc->n_linear_ranges = 1;
>>> +    rdesc->n_voltages = rdesc->linear_ranges[rdesc->n_linear_ranges - 1].max_sel + 1;
>>> +    rdesc->ramp_delay = drv->reg_data->ramp_delay;
>>> +
>>> +    drv->reg_cpu = spm_get_cpu(dev);
>>> +    dev_dbg(dev, "SAW2 bound to CPU %d\n", drv->reg_cpu);
>>> +
>>> +    /*
>>> +     * Program initial voltage, otherwise registration will also try
>>> +     * setting the voltage, which might result in undervolting the CPU.
>>> +     */
>>> +    drv->volt_sel = DIV_ROUND_UP(drv->reg_data->init_uV - rdesc->min_uV,
>>> +                     rdesc->uV_step);
>>> +    ret = linear_range_get_selector_high(drv->reg_data->range,
>>> +                         drv->reg_data->init_uV,
>>> +                         &drv->volt_sel,
>>> +                         &found);
>>> +    if (ret) {
>>> +        dev_err(dev, "Initial uV value out of bounds\n");
>>> +        return ret;
>>> +    }
>>> +
>>> +    /* Always do the SAW register writes on the corresponding CPU */
>>> +    smp_call_function_single(drv->reg_cpu, drv->reg_data->set_vdd, drv, true);
>>> +
>>> +    rdev = devm_regulator_register(dev, rdesc, &config);
>>> +    if (IS_ERR(rdev)) {
>>> +        dev_err(dev, "failed to register regulator\n");
>>> +        return PTR_ERR(rdev);
>>> +    }
>>> +
>>> +    return 0;
>>> +}
>>> +#else
>>> +static int spm_register_regulator(struct device *dev, struct spm_driver_data *drv)
>>> +{
>>> +    return 0;
>>> +}
>>> +#endif
>>> +
>>>   static const struct of_device_id spm_match_table[] = {
>>>       { .compatible = "qcom,sdm660-gold-saw2-v4.1-l2",
>>>         .data = &spm_reg_660_gold_l2 },
>>> @@ -292,6 +492,7 @@ static int spm_dev_probe(struct platform_device *pdev)
>>>           return -ENODEV;
>>>         drv->reg_data = match_id->data;
>>> +    drv->dev = &pdev->dev;
>>>       platform_set_drvdata(pdev, drv);
>>>         /* Write the SPM sequences first.. */
>>> @@ -319,7 +520,7 @@ static int spm_dev_probe(struct platform_device *pdev)
>>>       if (drv->reg_data->reg_offset[SPM_REG_SPM_CTL])
>>>           spm_set_low_power_mode(drv, PM_SLEEP_MODE_STBY);
>>>   -    return 0;
>>> +    return spm_register_regulator(&pdev->dev, drv);
>>>   }
>>>     static struct platform_driver spm_driver = {
>>> diff --git a/include/soc/qcom/spm.h b/include/soc/qcom/spm.h
>>> index 4951f9d8b0bd..9859ebe42003 100644
>>> --- a/include/soc/qcom/spm.h
>>> +++ b/include/soc/qcom/spm.h
>>> @@ -30,11 +30,20 @@ struct spm_reg_data {
>>>       u32 avs_limit;
>>>       u8 seq[MAX_SEQ_DATA];
>>>       u8 start_index[PM_SLEEP_MODE_NR];
>>> +
>>> +    smp_call_func_t set_vdd;
>>> +    /* for now we support only a single range */
>>> +    struct linear_range *range;
>>> +    unsigned int ramp_delay;
>>> +    unsigned int init_uV;
>>>   };
>>>     struct spm_driver_data {
>>>       void __iomem *reg_base;
>>>       const struct spm_reg_data *reg_data;
>>> +    struct device *dev;
>>> +    unsigned int volt_sel;
>>> +    int reg_cpu;
>>>   };
>>>     void spm_set_low_power_mode(struct spm_driver_data *drv,
> 

Re: [PATCH v2 25/26] ARM: dts: qcom: ipq4019: drop 'regulator' property from SAW2 devices

[Konrad Dybcio]

On 25.06.2023 22:25, Dmitry Baryshkov wrote:
> The SAW2 device should describe the regulator constraints rather than
> just declaring that it has the regulator.
> 
> Drop the 'regulator' property. If/when CPU voltage scaling is
> implemented for this platform, proper regulator nodes show be added
> instead.
> 
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>

Konrad
>  arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi | 5 -----
>  1 file changed, 5 deletions(-)
> 
> diff --git a/arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi b/arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi
> index f0ef86fadc9d..ad3c922843c7 100644
> --- a/arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi
> +++ b/arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi
> @@ -350,31 +350,26 @@ acc3: power-manager@b0b8000 {
>  		saw0: regulator@b089000 {
>  			compatible = "qcom,saw2";
>  			reg = <0x0b089000 0x1000>, <0x0b009000 0x1000>;
> -			regulator;
>  		};
>  
>  		saw1: regulator@b099000 {
>  			compatible = "qcom,saw2";
>  			reg = <0x0b099000 0x1000>, <0x0b009000 0x1000>;
> -			regulator;
>  		};
>  
>  		saw2: regulator@b0a9000 {
>  			compatible = "qcom,saw2";
>  			reg = <0x0b0a9000 0x1000>, <0x0b009000 0x1000>;
> -			regulator;
>  		};
>  
>  		saw3: regulator@b0b9000 {
>  			compatible = "qcom,saw2";
>  			reg = <0x0b0b9000 0x1000>, <0x0b009000 0x1000>;
> -			regulator;
>  		};
>  
>  		saw_l2: regulator@b012000 {
>  			compatible = "qcom,saw2";
>  			reg = <0xb012000 0x1000>;
> -			regulator;
>  		};
>  
>  		blsp1_uart1: serial@78af000 {

Re: [PATCH v2 26/26] ARM: dts: qcom: ipq8064: drop 'regulator' property from SAW2 devices

[Konrad Dybcio]

On 25.06.2023 22:25, Dmitry Baryshkov wrote:
> The SAW2 device should describe the regulator constraints rather than
> just declaring that it has the regulator.
> 
> Drop the 'regulator' property. If/when CPU voltage scaling is
> implemented for this platform, proper regulator nodes show be added
> instead.
> 
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>

Konrad
>  arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi | 2 --
>  1 file changed, 2 deletions(-)
> 
> diff --git a/arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi b/arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi
> index 6198f42f6a9c..ecb99e104de0 100644
> --- a/arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi
> +++ b/arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi
> @@ -589,7 +589,6 @@ acc0: clock-controller@2088000 {
>  		saw0: regulator@2089000 {
>  			compatible = "qcom,saw2";
>  			reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
> -			regulator;
>  		};
>  
>  		acc1: clock-controller@2098000 {
> @@ -604,7 +603,6 @@ acc1: clock-controller@2098000 {
>  		saw1: regulator@2099000 {
>  			compatible = "qcom,saw2";
>  			reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
> -			regulator;
>  		};
>  
>  		nss_common: syscon@3000000 {

Re: [PATCH v2 24/26] ARM: dts: qcom: msm8974: drop 'regulator' property from SAW2 device

[Konrad Dybcio]

On 25.06.2023 22:25, Dmitry Baryshkov wrote:
> The SAW2 device should describe the regulator constraints rather than
> just declaring that it has the regulator.
> 
> Drop the 'regulator' property. If/when CPU voltage scaling is
> implemented for this platform, proper regulator node show be added
> instead.
> 
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>

Konrad
>  arch/arm/boot/dts/qcom/qcom-msm8974.dtsi | 1 -
>  1 file changed, 1 deletion(-)
> 
> diff --git a/arch/arm/boot/dts/qcom/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom/qcom-msm8974.dtsi
> index aeca504918a0..dffab32c757d 100644
> --- a/arch/arm/boot/dts/qcom/qcom-msm8974.dtsi
> +++ b/arch/arm/boot/dts/qcom/qcom-msm8974.dtsi
> @@ -416,7 +416,6 @@ saw3: power-controller@f90b9000 {
>  		saw_l2: power-controller@f9012000 {
>  			compatible = "qcom,saw2";
>  			reg = <0xf9012000 0x1000>;
> -			regulator;
>  		};
>  
>  		acc0: power-manager@f9088000 {

Re: [PATCH v2 23/26] ARM: dts: qcom: apq8084: drop 'regulator' property from SAW2 device

[Konrad Dybcio]

On 25.06.2023 22:25, Dmitry Baryshkov wrote:
> The SAW2 device should describe the regulator constraints rather than
> just declaring that it has the regulator.
> 
> Drop the 'regulator' property. If/when CPU voltage scaling is
> implemented for this platform, proper regulator node show be added
> instead.
> 
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>

Konrad
>  arch/arm/boot/dts/qcom/qcom-apq8084.dtsi | 1 -
>  1 file changed, 1 deletion(-)
> 
> diff --git a/arch/arm/boot/dts/qcom/qcom-apq8084.dtsi b/arch/arm/boot/dts/qcom/qcom-apq8084.dtsi
> index 8f178bc87e1d..6a2ff30a2f3c 100644
> --- a/arch/arm/boot/dts/qcom/qcom-apq8084.dtsi
> +++ b/arch/arm/boot/dts/qcom/qcom-apq8084.dtsi
> @@ -652,7 +652,6 @@ saw3: power-controller@f90b9000 {
>  		saw_l2: power-controller@f9012000 {
>  			compatible = "qcom,saw2";
>  			reg = <0xf9012000 0x1000>;
> -			regulator;
>  		};
>  
>  		acc0: power-manager@f9088000 {

Re: [PATCH v2 22/26] ARM: dts: qcom: msm8960: declare SAW2 regulators

[Konrad Dybcio]

On 25.06.2023 22:25, Dmitry Baryshkov wrote:
> The SAW2 (SPM and AVS Wrapper) among other things is yet another way to
> handle CPU-related PMIC regulators. Provide a way to control voltage of
> these regulators.
> 
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>

Konrad
>  arch/arm/boot/dts/qcom/qcom-msm8960.dtsi | 12 ++++++++++--
>  1 file changed, 10 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/arm/boot/dts/qcom/qcom-msm8960.dtsi b/arch/arm/boot/dts/qcom/qcom-msm8960.dtsi
> index fa2013388d99..50a5d87e9851 100644
> --- a/arch/arm/boot/dts/qcom/qcom-msm8960.dtsi
> +++ b/arch/arm/boot/dts/qcom/qcom-msm8960.dtsi
> @@ -227,13 +227,21 @@ acc1: clock-controller@2098000 {
>  		saw0: regulator@2089000 {
>  			compatible = "qcom,saw2";
>  			reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
> -			regulator;
> +
> +			saw0_vreg: regulator {
> +				regulator-min-microvolt = <850000>;
> +				regulator-max-microvolt = <1300000>;
> +			};
>  		};
>  
>  		saw1: regulator@2099000 {
>  			compatible = "qcom,saw2";
>  			reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
> -			regulator;
> +
> +			saw1_vreg: regulator {
> +				regulator-min-microvolt = <850000>;
> +				regulator-max-microvolt = <1300000>;
> +			};
>  		};
>  
>  		gsbi5: gsbi@16400000 {

Re: [PATCH v2 16/26] ARM: dts: qcom: apq8064: add L2 cache scaling

[Konrad Dybcio]

On 25.06.2023 22:25, Dmitry Baryshkov wrote:
> Populate L2 cache node with clock, supplies and OPP information to
> facilitate scaling L2 frequency.
> 
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
Are the L2 voltage ranges independent of speedbin?

Konrad
>  arch/arm/boot/dts/qcom/qcom-apq8064.dtsi | 101 ++++++++++++++++++++++-
>  1 file changed, 100 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi
> index 1eb6d752ebae..ac07170c702f 100644
> --- a/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi
> +++ b/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi
> @@ -81,9 +81,108 @@ CPU3: cpu@3 {
>  		};
>  
>  		L2: l2-cache {
> -			compatible = "cache";
> +			compatible = "qcom,krait-l2-cache", "cache";
>  			cache-level = <2>;
>  			cache-unified;
> +			vdd-mem-supply = <&pm8921_l24>;
> +			vdd-dig-supply = <&pm8921_s3>;
> +			clocks = <&kraitcc KRAIT_L2>;
> +			#interconnect-cells = <1>;
> +			operating-points-v2 = <&l2_opp_table>;
> +
> +			l2_opp_table: opp-table-l2 {
> +				compatible = "operating-points-v2";
> +
> +				opp-384000000 {
> +					opp-hz = /bits/ 64 <384000000>;
> +					opp-microvolt = <1050000 1050000 1150000>,
> +							<950000 950000 1150000>;
> +				};
> +
> +				opp-432000000 {
> +					opp-hz = /bits/ 64 <432000000>;
> +					opp-microvolt = <1050000 1050000 1150000>,
> +							<1050000 1050000 1150000>;
> +				};
> +
> +				opp-486000000 {
> +					opp-hz = /bits/ 64 <486000000>;
> +					opp-microvolt = <1050000 1050000 1150000>,
> +							<1050000 1050000 1150000>;
> +				};
> +
> +				opp-540000000 {
> +					opp-hz = /bits/ 64 <540000000>;
> +					opp-microvolt = <1050000 1050000 1150000>,
> +							<1050000 1050000 1150000>;
> +				};
> +
> +				opp-594000000 {
> +					opp-hz = /bits/ 64 <594000000>;
> +					opp-microvolt = <1050000 1050000 1150000>,
> +							<1050000 1050000 1150000>;
> +				};
> +
> +				opp-648000000 {
> +					opp-hz = /bits/ 64 <648000000>;
> +					opp-microvolt = <1050000 1050000 1150000>,
> +							<1050000 1050000 1150000>;
> +				};
> +
> +				opp-702000000 {
> +					opp-hz = /bits/ 64 <702000000>;
> +					opp-microvolt = <1150000 1150000 1150000>,
> +							<1150000 1150000 1150000>;
> +				};
> +
> +				opp-756000000 {
> +					opp-hz = /bits/ 64 <756000000>;
> +					opp-microvolt = <1150000 1150000 1150000>,
> +							<1150000 1150000 1150000>;
> +				};
> +
> +				opp-810000000 {
> +					opp-hz = /bits/ 64 <810000000>;
> +					opp-microvolt = <1150000 1150000 1150000>,
> +							<1150000 1150000 1150000>;
> +				};
> +
> +				opp-864000000 {
> +					opp-hz = /bits/ 64 <864000000>;
> +					opp-microvolt = <1150000 1150000 1150000>,
> +							<1150000 1150000 1150000>;
> +				};
> +
> +				opp-918000000 {
> +					opp-hz = /bits/ 64 <918000000>;
> +					opp-microvolt = <1150000 1150000 1150000>,
> +							<1150000 1150000 1150000>;
> +				};
> +
> +				opp-972000000 {
> +					opp-hz = /bits/ 64 <972000000>;
> +					opp-microvolt = <1150000 1150000 1150000>,
> +							<1150000 1150000 1150000>;
> +				};
> +
> +				opp-1026000000 {
> +					opp-hz = /bits/ 64 <1026000000>;
> +					opp-microvolt = <1150000 1150000 1150000>,
> +							<1150000 1150000 1150000>;
> +				};
> +
> +				opp-1080000000 {
> +					opp-hz = /bits/ 64 <1080000000>;
> +					opp-microvolt = <1150000 1150000 1150000>,
> +							<1150000 1150000 1150000>;
> +				};
> +
> +				opp-1134000000 {
> +					opp-hz = /bits/ 64 <1134000000>;
> +					opp-microvolt = <1150000 1150000 1150000>,
> +							<1150000 1150000 1150000>;
> +				};
> +			};
>  		};
>  
>  		idle-states {

Re: [PATCH v2 17/26] ARM: dts: qcom: apq8064: add simple CPUFreq support

[Konrad Dybcio]

On 25.06.2023 22:25, Dmitry Baryshkov wrote:
> Declare CPU frequency-scaling properties. Each CPU has its own clock,
> how
however?

> all CPUs have the same OPP table. Voltage scaling is not (yet)
> enabled with this patch. It will be enabled later.
Risky business.

> 
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
>  arch/arm/boot/dts/qcom/qcom-apq8064.dtsi | 170 +++++++++++++++++++++++
>  1 file changed, 170 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi
> index ac07170c702f..e4d2fd48d843 100644
> --- a/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi
> +++ b/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi
> @@ -2,11 +2,13 @@
>  /dts-v1/;
>  
>  #include <dt-bindings/clock/qcom,gcc-msm8960.h>
> +#include <dt-bindings/clock/qcom,krait-cc.h>
>  #include <dt-bindings/clock/qcom,lcc-msm8960.h>
>  #include <dt-bindings/reset/qcom,gcc-msm8960.h>
>  #include <dt-bindings/clock/qcom,mmcc-msm8960.h>
>  #include <dt-bindings/clock/qcom,rpmcc.h>
>  #include <dt-bindings/soc/qcom,gsbi.h>
> +#include <dt-bindings/soc/qcom,krait-l2-cache.h>
>  #include <dt-bindings/interrupt-controller/irq.h>
>  #include <dt-bindings/interrupt-controller/arm-gic.h>
>  / {
> @@ -45,6 +47,12 @@ CPU0: cpu@0 {
>  			qcom,acc = <&acc0>;
>  			qcom,saw = <&saw0>;
>  			cpu-idle-states = <&CPU_SPC>;
> +			clocks = <&kraitcc KRAIT_CPU_0>;
> +			clock-names = "cpu";
> +			clock-latency = <100000>;
> +			interconnects = <&L2 MASTER_KRAIT_L2 &L2 SLAVE_KRAIT_L2>;
> +			operating-points-v2 = <&cpu_opp_table>;
> +			#cooling-cells = <2>;
>  		};
>  
>  		CPU1: cpu@1 {
> @@ -56,6 +64,12 @@ CPU1: cpu@1 {
>  			qcom,acc = <&acc1>;
>  			qcom,saw = <&saw1>;
>  			cpu-idle-states = <&CPU_SPC>;
> +			clocks = <&kraitcc KRAIT_CPU_1>;
> +			clock-names = "cpu";
> +			clock-latency = <100000>;
> +			interconnects = <&L2 MASTER_KRAIT_L2 &L2 SLAVE_KRAIT_L2>;
> +			operating-points-v2 = <&cpu_opp_table>;
> +			#cooling-cells = <2>;
>  		};
>  
>  		CPU2: cpu@2 {
> @@ -67,6 +81,12 @@ CPU2: cpu@2 {
>  			qcom,acc = <&acc2>;
>  			qcom,saw = <&saw2>;
>  			cpu-idle-states = <&CPU_SPC>;
> +			clocks = <&kraitcc KRAIT_CPU_2>;
> +			clock-names = "cpu";
> +			clock-latency = <100000>;
> +			interconnects = <&L2 MASTER_KRAIT_L2 &L2 SLAVE_KRAIT_L2>;
> +			operating-points-v2 = <&cpu_opp_table>;
> +			#cooling-cells = <2>;
>  		};
>  
>  		CPU3: cpu@3 {
> @@ -78,6 +98,12 @@ CPU3: cpu@3 {
>  			qcom,acc = <&acc3>;
>  			qcom,saw = <&saw3>;
>  			cpu-idle-states = <&CPU_SPC>;
> +			clocks = <&kraitcc KRAIT_CPU_3>;
> +			clock-names = "cpu";
> +			clock-latency = <100000>;
> +			interconnects = <&L2 MASTER_KRAIT_L2 &L2 SLAVE_KRAIT_L2>;
> +			operating-points-v2 = <&cpu_opp_table>;
> +			#cooling-cells = <2>;
>  		};
>  
>  		L2: l2-cache {
> @@ -196,6 +222,121 @@ CPU_SPC: spc {
>  		};
>  	};
>  
> +        cpu_opp_table: opp-table-cpu {
> +		compatible = "operating-points-v2-krait-cpu";
> +		nvmem-cells = <&speedbin_efuse>;
> +
> +		/*
> +		 * Voltage thresholds are <target min max>
> +		 */
What voltage thresholds?

> +		opp-384000000 {
> +			opp-hz = /bits/ 64 <384000000>;
> +			opp-peak-kBps = <384000>;
> +			opp-supported-hw = <0x4007>;
> +			/*
> +			 * higher latency as it requires switching between
> +			 * clock sources
> +			 */
> +			clock-latency-ns = <244144>;
> +		};
> +
> +		opp-486000000 {
> +			opp-hz = /bits/ 64 <486000000>;
> +			opp-peak-kBps = <648000>;
> +			opp-supported-hw = <0x4007>;
> +		};
> +
> +		opp-594000000 {
> +			opp-hz = /bits/ 64 <594000000>;
> +			opp-peak-kBps = <648000>;
> +			opp-supported-hw = <0x4007>;
> +		};
> +
> +		opp-702000000 {
> +			opp-hz = /bits/ 64 <702000000>;
> +			opp-peak-kBps = <648000>;
> +			opp-supported-hw = <0x4007>;
> +		};
> +
> +		opp-810000000 {
> +			opp-hz = /bits/ 64 <810000000>;
> +			opp-peak-kBps = <648000>;
> +			opp-supported-hw = <0x4007>;
> +		};
> +
> +		opp-918000000 {
> +			opp-hz = /bits/ 64 <918000000>;
> +			opp-peak-kBps = <648000>;
> +			opp-supported-hw = <0x4007>;
> +		};
> +
> +		opp-1026000000 {
> +			opp-hz = /bits/ 64 <1026000000>;
> +			opp-peak-kBps = <648000>;
> +			opp-supported-hw = <0x4007>;
> +		};
> +
> +		opp-1134000000 {
> +			opp-hz = /bits/ 64 <1134000000>;
> +			opp-peak-kBps = <1134000>;
> +			opp-supported-hw = <0x4007>;
> +		};
> +
> +		opp-1242000000 {
> +			opp-hz = /bits/ 64 <1242000000>;
> +			opp-peak-kBps = <1134000>;
> +			opp-supported-hw = <0x4007>;
> +		};
> +
> +		opp-1350000000 {
> +			opp-hz = /bits/ 64 <1350000000>;
> +			opp-peak-kBps = <1134000>;
> +			opp-supported-hw = <0x4007>;
> +		};
> +
> +		opp-1458000000 {
> +			opp-hz = /bits/ 64 <1458000000>;
> +			opp-peak-kBps = <1134000>;
> +			opp-supported-hw = <0x4007>;
> +		};
> +
> +		opp-1512000000 {
> +			opp-hz = /bits/ 64 <1512000000>;
> +			opp-peak-kBps = <1134000>;
> +			opp-supported-hw = <0x4001>;
> +		};
> +
> +		opp-1566000000 {
> +			opp-hz = /bits/ 64 <1566000000>;
> +			opp-peak-kBps = <1134000>;
> +			opp-supported-hw = <0x06>;
> +		};
> +
> +		opp-1674000000 {
> +			opp-hz = /bits/ 64 <1674000000>;
> +			opp-peak-kBps = <1134000>;
> +			opp-supported-hw = <0x06>;
> +		};
> +
> +		opp-1728000000 {
> +			opp-hz = /bits/ 64 <1728000000>;
> +			opp-peak-kBps = <1134000>;
> +			opp-supported-hw = <0x02>;
> +		};
> +
> +		opp-1782000000 {
> +			opp-hz = /bits/ 64 <1782000000>;
> +			opp-peak-kBps = <1134000>;
> +			opp-supported-hw = <0x04>;
> +		};
> +
> +		opp-1890000000 {
> +			opp-hz = /bits/ 64 <1890000000>;
> +			opp-peak-kBps = <1134000>;
> +			opp-supported-hw = <0x04>;
> +		};
> +	};
> +
>  	memory@0 {
>  		device_type = "memory";
>  		reg = <0x0 0x0>;
> @@ -312,6 +453,32 @@ sleep_clk: sleep_clk {
>  		};
>  	};
>  
> +	kraitcc: clock-controller {
> +		compatible = "qcom,krait-cc-v1";
Are we sure we don't wanna rework this compatible? Check the comment in
drivers/clk/qcom/krait-cc.c : krait_add_sec_mux()


> +		clocks = <&gcc PLL9>, /* hfpll0 */
> +			 <&gcc PLL10>, /* hfpll1 */
> +			 <&gcc PLL16>, /* hfpll2 */
> +			 <&gcc PLL17>, /* hfpll3 */
> +			 <&gcc PLL12>, /* hfpll_l2 */
> +			 <&acc0>,
> +			 <&acc1>,
> +			 <&acc2>,
> +			 <&acc3>,
> +			 <&l2cc>;
> +		clock-names = "hfpll0",
> +			      "hfpll1",
> +			      "hfpll2",
> +			      "hfpll3",
> +			      "hfpll_l2",
> +			      "acpu0_aux",
> +			      "acpu1_aux",
> +			      "acpu2_aux",
> +			      "acpu3_aux",
> +			      "acpu_l2_aux";
> +		#clock-cells = <1>;
> +		#interconnect-cells = <1>;
> +	};
> +
>  	sfpb_mutex: hwmutex {
>  		compatible = "qcom,sfpb-mutex";
>  		syscon = <&sfpb_wrapper_mutex 0x604 0x4>;
> @@ -933,6 +1100,9 @@ qfprom: qfprom@700000 {
>  			#address-cells = <1>;
>  			#size-cells = <1>;
>  			ranges;
> +			speedbin_efuse: speedbin@c0 {
> +				reg = <0x0c0 0x4>;
> +			};
Newline between properties and subnodes & between individual subnodes,
please

Konrad
>  			tsens_calib: calib@404 {
>  				reg = <0x404 0x10>;
>  			};

Re: [PATCH v2 18/26] ARM: dts: qcom: apq8064: provide voltage scaling tables

[Konrad Dybcio]

On 25.06.2023 22:25, Dmitry Baryshkov wrote:
> APQ8064 has 4 speed bins, each of them having from 4 to 6 categorization
> kinds. Provide tables necessary to handle voltage scaling on this SoC.
> 
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
I am trusting you all of this is correct :D

Acked-by: Konrad Dybcio <konrad.dybcio@linaro.org>

Konrad
>  arch/arm/boot/dts/qcom/qcom-apq8064.dtsi | 339 +++++++++++++++++++++++
>  1 file changed, 339 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi
> index e4d2fd48d843..b97d88517805 100644
> --- a/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi
> +++ b/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi
> @@ -50,6 +50,7 @@ CPU0: cpu@0 {
>  			clocks = <&kraitcc KRAIT_CPU_0>;
>  			clock-names = "cpu";
>  			clock-latency = <100000>;
> +			vdd-core-supply = <&saw0_vreg>;
>  			interconnects = <&L2 MASTER_KRAIT_L2 &L2 SLAVE_KRAIT_L2>;
>  			operating-points-v2 = <&cpu_opp_table>;
>  			#cooling-cells = <2>;
> @@ -67,6 +68,7 @@ CPU1: cpu@1 {
>  			clocks = <&kraitcc KRAIT_CPU_1>;
>  			clock-names = "cpu";
>  			clock-latency = <100000>;
> +			vdd-core-supply = <&saw1_vreg>;
>  			interconnects = <&L2 MASTER_KRAIT_L2 &L2 SLAVE_KRAIT_L2>;
>  			operating-points-v2 = <&cpu_opp_table>;
>  			#cooling-cells = <2>;
> @@ -84,6 +86,7 @@ CPU2: cpu@2 {
>  			clocks = <&kraitcc KRAIT_CPU_2>;
>  			clock-names = "cpu";
>  			clock-latency = <100000>;
> +			vdd-core-supply = <&saw2_vreg>;
>  			interconnects = <&L2 MASTER_KRAIT_L2 &L2 SLAVE_KRAIT_L2>;
>  			operating-points-v2 = <&cpu_opp_table>;
>  			#cooling-cells = <2>;
> @@ -101,6 +104,7 @@ CPU3: cpu@3 {
>  			clocks = <&kraitcc KRAIT_CPU_3>;
>  			clock-names = "cpu";
>  			clock-latency = <100000>;
> +			vdd-core-supply = <&saw3_vreg>;
>  			interconnects = <&L2 MASTER_KRAIT_L2 &L2 SLAVE_KRAIT_L2>;
>  			operating-points-v2 = <&cpu_opp_table>;
>  			#cooling-cells = <2>;
> @@ -232,6 +236,31 @@ cpu_opp_table: opp-table-cpu {
>  		opp-384000000 {
>  			opp-hz = /bits/ 64 <384000000>;
>  			opp-peak-kBps = <384000>;
> +			opp-microvolt-speed0-pvs0 = <950000 950000 975000>;
> +			opp-microvolt-speed0-pvs1 = <925000 900000 950000>;
> +			opp-microvolt-speed0-pvs3 = <875000 850000 900000>;
> +			opp-microvolt-speed0-pvs4 = <875000 850000 900000>;
> +			opp-microvolt-speed1-pvs0 = <950000 950000 975000>;
> +			opp-microvolt-speed1-pvs1 = <975000 950000 1000000>;
> +			opp-microvolt-speed1-pvs2 = <950000 925000 975000>;
> +			opp-microvolt-speed1-pvs3 = <925000 900000 950000>;
> +			opp-microvolt-speed1-pvs4 = <900000 875000 925000>;
> +			opp-microvolt-speed1-pvs5 = <900000 875000 925000>;
> +			opp-microvolt-speed1-pvs6 = <900000 875000 925000>;
> +			opp-microvolt-speed2-pvs0 = <950000 950000 975000>;
> +			opp-microvolt-speed2-pvs1 = <925000 925000 925000>;
> +			opp-microvolt-speed2-pvs2 = <925000 900000 950000>;
> +			opp-microvolt-speed2-pvs3 = <925000 900000 950000>;
> +			opp-microvolt-speed2-pvs4 = <900000 875000 925000>;
> +			opp-microvolt-speed2-pvs5 = <900000 875000 925000>;
> +			opp-microvolt-speed2-pvs6 = <900000 875000 925000>;
> +			opp-microvolt-speed14-pvs0 = <950000 950000 975000>;
> +			opp-microvolt-speed14-pvs1 = <975000 950000 1000000>;
> +			opp-microvolt-speed14-pvs2 = <950000 925000 975000>;
> +			opp-microvolt-speed14-pvs3 = <925000 900000 950000>;
> +			opp-microvolt-speed14-pvs4 = <900000 875000 925000>;
> +			opp-microvolt-speed14-pvs5 = <875000 875000 875000>;
> +			opp-microvolt-speed14-pvs6 = <900000 875000 925000>;
>  			opp-supported-hw = <0x4007>;
>  			/*
>  			 * higher latency as it requires switching between
> @@ -243,96 +272,406 @@ opp-384000000 {
>  		opp-486000000 {
>  			opp-hz = /bits/ 64 <486000000>;
>  			opp-peak-kBps = <648000>;
> +			opp-microvolt-speed0-pvs0 = <975000 975000 1000000>;
> +			opp-microvolt-speed0-pvs1 = <950000 925000 975000>;
> +			opp-microvolt-speed0-pvs3 = <900000 875000 925000>;
> +			opp-microvolt-speed0-pvs4 = <900000 875000 925000>;
> +			opp-microvolt-speed1-pvs0 = <950000 950000 975000>;
> +			opp-microvolt-speed1-pvs1 = <975000 950000 1000000>;
> +			opp-microvolt-speed1-pvs2 = <950000 925000 975000>;
> +			opp-microvolt-speed1-pvs3 = <925000 900000 950000>;
> +			opp-microvolt-speed1-pvs4 = <900000 875000 925000>;
> +			opp-microvolt-speed1-pvs5 = <900000 875000 925000>;
> +			opp-microvolt-speed1-pvs6 = <900000 875000 925000>;
> +			opp-microvolt-speed2-pvs0 = <950000 950000 975000>;
> +			opp-microvolt-speed2-pvs1 = <925000 925000 925000>;
> +			opp-microvolt-speed2-pvs2 = <925000 900000 950000>;
> +			opp-microvolt-speed2-pvs3 = <925000 900000 950000>;
> +			opp-microvolt-speed2-pvs4 = <900000 875000 925000>;
> +			opp-microvolt-speed2-pvs5 = <900000 875000 925000>;
> +			opp-microvolt-speed2-pvs6 = <900000 875000 925000>;
> +			opp-microvolt-speed14-pvs0 = <950000 950000 975000>;
> +			opp-microvolt-speed14-pvs1 = <975000 950000 1000000>;
> +			opp-microvolt-speed14-pvs2 = <950000 925000 975000>;
> +			opp-microvolt-speed14-pvs3 = <925000 900000 950000>;
> +			opp-microvolt-speed14-pvs4 = <900000 875000 925000>;
> +			opp-microvolt-speed14-pvs5 = <875000 875000 875000>;
> +			opp-microvolt-speed14-pvs6 = <875000 875000 875000>;
>  			opp-supported-hw = <0x4007>;
>  		};
>  
>  		opp-594000000 {
>  			opp-hz = /bits/ 64 <594000000>;
>  			opp-peak-kBps = <648000>;
> +			opp-microvolt-speed0-pvs0 = <1000000 1000000 1025000>;
> +			opp-microvolt-speed0-pvs1 = <975000 950000 1000000>;
> +			opp-microvolt-speed0-pvs3 = <925000 900000 950000>;
> +			opp-microvolt-speed0-pvs4 = <925000 900000 950000>;
> +			opp-microvolt-speed1-pvs0 = <950000 950000 975000>;
> +			opp-microvolt-speed1-pvs1 = <975000 950000 1000000>;
> +			opp-microvolt-speed1-pvs2 = <950000 925000 975000>;
> +			opp-microvolt-speed1-pvs3 = <925000 900000 950000>;
> +			opp-microvolt-speed1-pvs4 = <900000 875000 925000>;
> +			opp-microvolt-speed1-pvs5 = <900000 875000 925000>;
> +			opp-microvolt-speed1-pvs6 = <900000 875000 925000>;
> +			opp-microvolt-speed2-pvs0 = <950000 950000 975000>;
> +			opp-microvolt-speed2-pvs1 = <925000 925000 925000>;
> +			opp-microvolt-speed2-pvs2 = <925000 900000 950000>;
> +			opp-microvolt-speed2-pvs3 = <925000 900000 950000>;
> +			opp-microvolt-speed2-pvs4 = <900000 875000 925000>;
> +			opp-microvolt-speed2-pvs5 = <900000 875000 925000>;
> +			opp-microvolt-speed2-pvs6 = <900000 875000 925000>;
> +			opp-microvolt-speed14-pvs0 = <950000 950000 975000>;
> +			opp-microvolt-speed14-pvs1 = <975000 950000 1000000>;
> +			opp-microvolt-speed14-pvs2 = <950000 925000 975000>;
> +			opp-microvolt-speed14-pvs3 = <925000 900000 950000>;
> +			opp-microvolt-speed14-pvs4 = <900000 875000 925000>;
> +			opp-microvolt-speed14-pvs5 = <875000 875000 875000>;
> +			opp-microvolt-speed14-pvs6 = <900000 875000 925000>;
>  			opp-supported-hw = <0x4007>;
>  		};
>  
>  		opp-702000000 {
>  			opp-hz = /bits/ 64 <702000000>;
>  			opp-peak-kBps = <648000>;
> +			opp-microvolt-speed0-pvs0 = <1025000 1025000 1050000>;
> +			opp-microvolt-speed0-pvs1 = <1000000 975000 1025000>;
> +			opp-microvolt-speed0-pvs3 = <950000 925000 975000>;
> +			opp-microvolt-speed0-pvs4 = <950000 925000 975000>;
> +			opp-microvolt-speed1-pvs0 = <962500 962500 987500>;
> +			opp-microvolt-speed1-pvs1 = <987500 962500 1012500>;
> +			opp-microvolt-speed1-pvs2 = <950000 925000 975000>;
> +			opp-microvolt-speed1-pvs3 = <925000 900000 950000>;
> +			opp-microvolt-speed1-pvs4 = <900000 875000 925000>;
> +			opp-microvolt-speed1-pvs5 = <900000 875000 925000>;
> +			opp-microvolt-speed1-pvs6 = <900000 875000 925000>;
> +			opp-microvolt-speed2-pvs0 = <950000 950000 975000>;
> +			opp-microvolt-speed2-pvs1 = <925000 925000 925000>;
> +			opp-microvolt-speed2-pvs2 = <925000 900000 950000>;
> +			opp-microvolt-speed2-pvs3 = <925000 900000 950000>;
> +			opp-microvolt-speed2-pvs4 = <900000 875000 925000>;
> +			opp-microvolt-speed2-pvs5 = <900000 875000 925000>;
> +			opp-microvolt-speed2-pvs6 = <900000 875000 925000>;
> +			opp-microvolt-speed14-pvs0 = <962500 962500 987500>;
> +			opp-microvolt-speed14-pvs1 = <987500 962500 1012500>;
> +			opp-microvolt-speed14-pvs2 = <950000 925000 975000>;
> +			opp-microvolt-speed14-pvs3 = <925000 900000 950000>;
> +			opp-microvolt-speed14-pvs4 = <900000 875000 925000>;
> +			opp-microvolt-speed14-pvs5 = <875000 875000 875000>;
> +			opp-microvolt-speed14-pvs6 = <900000 875000 925000>;
>  			opp-supported-hw = <0x4007>;
>  		};
>  
>  		opp-810000000 {
>  			opp-hz = /bits/ 64 <810000000>;
>  			opp-peak-kBps = <648000>;
> +			opp-microvolt-speed0-pvs0 = <1075000 1075000 1100000>;
> +			opp-microvolt-speed0-pvs1 = <1050000 1025000 1075000>;
> +			opp-microvolt-speed0-pvs3 = <1000000 975000 1025000>;
> +			opp-microvolt-speed0-pvs4 = <987500 962500 1012500>;
> +			opp-microvolt-speed1-pvs0 = <1000000 1000000 1025000>;
> +			opp-microvolt-speed1-pvs1 = <1000000 975000 1025000>;
> +			opp-microvolt-speed1-pvs2 = <962500 937500 987500>;
> +			opp-microvolt-speed1-pvs3 = <925000 900000 950000>;
> +			opp-microvolt-speed1-pvs4 = <912500 887500 937500>;
> +			opp-microvolt-speed1-pvs5 = <912500 887500 937500>;
> +			opp-microvolt-speed1-pvs6 = <912500 887500 937500>;
> +			opp-microvolt-speed2-pvs0 = <962500 962500 987500>;
> +			opp-microvolt-speed2-pvs1 = <937500 937500 937500>;
> +			opp-microvolt-speed2-pvs2 = <937500 912500 962500>;
> +			opp-microvolt-speed2-pvs3 = <925000 900000 950000>;
> +			opp-microvolt-speed2-pvs4 = <912500 887500 937500>;
> +			opp-microvolt-speed2-pvs5 = <912500 887500 937500>;
> +			opp-microvolt-speed2-pvs6 = <912500 887500 937500>;
> +			opp-microvolt-speed14-pvs0 = <1000000 1000000 1025000>;
> +			opp-microvolt-speed14-pvs1 = <1000000 975000 1025000>;
> +			opp-microvolt-speed14-pvs2 = <962500 937500 987500>;
> +			opp-microvolt-speed14-pvs3 = <925000 900000 950000>;
> +			opp-microvolt-speed14-pvs4 = <912500 887500 937500>;
> +			opp-microvolt-speed14-pvs5 = <887500 887500 887500>;
> +			opp-microvolt-speed14-pvs6 = <912500 887500 937500>;
>  			opp-supported-hw = <0x4007>;
>  		};
>  
>  		opp-918000000 {
>  			opp-hz = /bits/ 64 <918000000>;
>  			opp-peak-kBps = <648000>;
> +			opp-microvolt-speed0-pvs0 = <1100000 1100000 1125000>;
> +			opp-microvolt-speed0-pvs1 = <1075000 1050000 1100000>;
> +			opp-microvolt-speed0-pvs3 = <1025000 1000000 1050000>;
> +			opp-microvolt-speed0-pvs4 = <1000000 975000 1025000>;
> +			opp-microvolt-speed1-pvs0 = <1025000 1025000 1050000>;
> +			opp-microvolt-speed1-pvs1 = <1025000 1000000 1050000>;
> +			opp-microvolt-speed1-pvs2 = <975000 950000 1000000>;
> +			opp-microvolt-speed1-pvs3 = <950000 925000 975000>;
> +			opp-microvolt-speed1-pvs4 = <925000 900000 950000>;
> +			opp-microvolt-speed1-pvs5 = <925000 900000 950000>;
> +			opp-microvolt-speed1-pvs6 = <925000 900000 950000>;
> +			opp-microvolt-speed2-pvs0 = <975000 975000 1000000>;
> +			opp-microvolt-speed2-pvs1 = <950000 950000 950000>;
> +			opp-microvolt-speed2-pvs2 = <950000 925000 975000>;
> +			opp-microvolt-speed2-pvs3 = <937500 912500 962500>;
> +			opp-microvolt-speed3-pvs4 = <925000 900000 950000>;
> +			opp-microvolt-speed2-pvs5 = <925000 900000 950000>;
> +			opp-microvolt-speed2-pvs6 = <925000 900000 950000>;
> +			opp-microvolt-speed14-pvs0 = <1025000 1025000 1050000>;
> +			opp-microvolt-speed14-pvs1 = <1025000 1000000 1050000>;
> +			opp-microvolt-speed14-pvs2 = <975000 950000 1000000>;
> +			opp-microvolt-speed14-pvs3 = <950000 925000 975000>;
> +			opp-microvolt-speed14-pvs4 = <925000 900000 950000>;
> +			opp-microvolt-speed14-pvs5 = <900000 900000 900000>;
> +			opp-microvolt-speed14-pvs6 = <925000 900000 950000>;
>  			opp-supported-hw = <0x4007>;
>  		};
>  
>  		opp-1026000000 {
>  			opp-hz = /bits/ 64 <1026000000>;
>  			opp-peak-kBps = <648000>;
> +			opp-microvolt-speed0-pvs0 = <1125000 1125000 1150000>;
> +			opp-microvolt-speed0-pvs1 = <1100000 1075000 1125000>;
> +			opp-microvolt-speed0-pvs3 = <1050000 1025000 1075000>;
> +			opp-microvolt-speed0-pvs4 = <1025000 1000000 1050000>;
> +			opp-microvolt-speed1-pvs0 = <1037500 1037500 1062500>;
> +			opp-microvolt-speed1-pvs1 = <1037500 1012500 1062500>;
> +			opp-microvolt-speed1-pvs2 = <1000000 975000 1025000>;
> +			opp-microvolt-speed1-pvs3 = <975000 950000 1000000>;
> +			opp-microvolt-speed1-pvs4 = <950000 925000 975000>;
> +			opp-microvolt-speed1-pvs5 = <950000 925000 975000>;
> +			opp-microvolt-speed1-pvs6 = <950000 925000 975000>;
> +			opp-microvolt-speed2-pvs0 = <1000000 1000000 1025000>;
> +			opp-microvolt-speed2-pvs1 = <975000 975000 975000>;
> +			opp-microvolt-speed2-pvs2 = <975000 950000 1000000>;
> +			opp-microvolt-speed2-pvs3 = <962500 937500 987500>;
> +			opp-microvolt-speed2-pvs4 = <950000 925000 975000>;
> +			opp-microvolt-speed2-pvs5 = <950000 925000 975000>;
> +			opp-microvolt-speed2-pvs6 = <950000 925000 975000>;
> +			opp-microvolt-speed14-pvs0 = <1037500 1037500 1062500>;
> +			opp-microvolt-speed14-pvs1 = <1037500 1012500 1062500>;
> +			opp-microvolt-speed14-pvs2 = <1000000 975000 1025000>;
> +			opp-microvolt-speed14-pvs3 = <975000 950000 1000000>;
> +			opp-microvolt-speed14-pvs4 = <950000 925000 975000>;
> +			opp-microvolt-speed14-pvs5 = <925000 925000 925000>;
> +			opp-microvolt-speed14-pvs6 = <950000 925000 975000>;
>  			opp-supported-hw = <0x4007>;
>  		};
>  
>  		opp-1134000000 {
>  			opp-hz = /bits/ 64 <1134000000>;
>  			opp-peak-kBps = <1134000>;
> +			opp-microvolt-speed0-pvs0 = <1175000 1175000 1200000>;
> +			opp-microvolt-speed0-pvs1 = <1150000 1125000 1175000>;
> +			opp-microvolt-speed0-pvs3 = <1100000 1075000 1125000>;
> +			opp-microvolt-speed0-pvs4 = <1075000 1050000 1100000>;
> +			opp-microvolt-speed1-pvs0 = <1075000 1075000 1100000>;
> +			opp-microvolt-speed1-pvs1 = <1062500 1037500 1087500>;
> +			opp-microvolt-speed1-pvs2 = <1025000 1000000 1050000>;
> +			opp-microvolt-speed1-pvs3 = <1000000 975000 1025000>;
> +			opp-microvolt-speed1-pvs4 = <975000 950000 1000000>;
> +			opp-microvolt-speed1-pvs5 = <962500 937500 987500>;
> +			opp-microvolt-speed1-pvs6 = <962500 937500 987500>;
> +			opp-microvolt-speed2-pvs0 = <1025000 1025000 1050000>;
> +			opp-microvolt-speed2-pvs1 = <1000000 1000000 1000000>;
> +			opp-microvolt-speed2-pvs2 = <1000000 975000 1025000>;
> +			opp-microvolt-speed2-pvs3 = <987500 962500 1012500>;
> +			opp-microvolt-speed2-pvs4 = <975000 950000 1000000>;
> +			opp-microvolt-speed2-pvs5 = <962500 937500 987500>;
> +			opp-microvolt-speed2-pvs6 = <962500 937500 987500>;
> +			opp-microvolt-speed14-pvs0 = <1075000 1075000 1100000>;
> +			opp-microvolt-speed14-pvs1 = <1062500 1037500 1087500>;
> +			opp-microvolt-speed14-pvs2 = <1025000 1000000 1050000>;
> +			opp-microvolt-speed14-pvs3 = <1000000 975000 1025000>;
> +			opp-microvolt-speed14-pvs4 = <975000 950000 1000000>;
> +			opp-microvolt-speed14-pvs5 = <937500 937500 937500>;
> +			opp-microvolt-speed14-pvs6 = <962500 937500 987500>;
>  			opp-supported-hw = <0x4007>;
>  		};
>  
>  		opp-1242000000 {
>  			opp-hz = /bits/ 64 <1242000000>;
>  			opp-peak-kBps = <1134000>;
> +			opp-microvolt-speed0-pvs0 = <1200000 1200000 1225000>;
> +			opp-microvolt-speed0-pvs1 = <1175000 1150000 1200000>;
> +			opp-microvolt-speed0-pvs3 = <1125000 1100000 1150000>;
> +			opp-microvolt-speed0-pvs4 = <1100000 1075000 1125000>;
> +			opp-microvolt-speed1-pvs0 = <1087500 1087500 1112500>;
> +			opp-microvolt-speed1-pvs1 = <1075000 1050000 1100000>;
> +			opp-microvolt-speed1-pvs2 = <1037500 1012500 1062500>;
> +			opp-microvolt-speed1-pvs3 = <1012500 987500 1037500>;
> +			opp-microvolt-speed1-pvs4 = <987500 962500 1012500>;
> +			opp-microvolt-speed1-pvs5 = <975000 950000 1000000>;
> +			opp-microvolt-speed1-pvs6 = <975000 950000 1000000>;
> +			opp-microvolt-speed2-pvs0 = <1037500 1037500 1062500>;
> +			opp-microvolt-speed2-pvs1 = <1012500 1012500 1012500>;
> +			opp-microvolt-speed2-pvs2 = <1012500 987500 1037500>;
> +			opp-microvolt-speed2-pvs3 = <1000000 975000 1025000>;
> +			opp-microvolt-speed2-pvs4 = <987500 962500 1012500>;
> +			opp-microvolt-speed2-pvs5 = <975000 950000 1000000>;
> +			opp-microvolt-speed2-pvs6 = <975000 950000 1000000>;
> +			opp-microvolt-speed14-pvs0 = <1087500 1087500 1112500>;
> +			opp-microvolt-speed14-pvs1 = <1075000 1050000 1100000>;
> +			opp-microvolt-speed14-pvs2 = <1037500 1012500 1062500>;
> +			opp-microvolt-speed14-pvs3 = <1012500 987500 1037500>;
> +			opp-microvolt-speed14-pvs4 = <987500 962500 1012500>;
> +			opp-microvolt-speed14-pvs5 = <950000 950000 950000>;
> +			opp-microvolt-speed14-pvs6 = <975000 950000 1000000>;
>  			opp-supported-hw = <0x4007>;
>  		};
>  
>  		opp-1350000000 {
>  			opp-hz = /bits/ 64 <1350000000>;
>  			opp-peak-kBps = <1134000>;
> +			opp-microvolt-speed0-pvs0 = <1225000 1225000 1250000>;
> +			opp-microvolt-speed0-pvs1 = <1200000 1175000 1225000>;
> +			opp-microvolt-speed0-pvs3 = <1150000 1125000 1175000>;
> +			opp-microvolt-speed0-pvs4 = <1125000 1100000 1150000>;
> +			opp-microvolt-speed1-pvs0 = <1125000 1125000 1150000>;
> +			opp-microvolt-speed1-pvs1 = <1112500 1087500 1137500>;
> +			opp-microvolt-speed1-pvs2 = <1062500 1037500 1087500>;
> +			opp-microvolt-speed1-pvs3 = <1025000 1000000 1050000>;
> +			opp-microvolt-speed1-pvs4 = <1000000 975000 1025000>;
> +			opp-microvolt-speed1-pvs5 = <987500 962500 1012500>;
> +			opp-microvolt-speed1-pvs6 = <987500 962500 1012500>;
> +			opp-microvolt-speed2-pvs0 = <1062500 1062500 1087500>;
> +			opp-microvolt-speed2-pvs1 = <1037500 1037500 1037500>;
> +			opp-microvolt-speed2-pvs2 = <1037500 1012500 1062500>;
> +			opp-microvolt-speed2-pvs3 = <1025000 1000000 1050000>;
> +			opp-microvolt-speed2-pvs4 = <1000000 975000 1025000>;
> +			opp-microvolt-speed2-pvs5 = <987500 962500 1012500>;
> +			opp-microvolt-speed2-pvs6 = <987500 962500 1012500>;
> +			opp-microvolt-speed14-pvs0 = <1125000 1125000 1150000>;
> +			opp-microvolt-speed14-pvs1 = <1112500 1087500 1137500>;
> +			opp-microvolt-speed14-pvs2 = <1062500 1037500 1087500>;
> +			opp-microvolt-speed14-pvs3 = <1025000 1000000 1050000>;
> +			opp-microvolt-speed14-pvs4 = <1000000 975000 1025000>;
> +			opp-microvolt-speed14-pvs5 = <962500 962500 962500>;
> +			opp-microvolt-speed14-pvs6 = <987500 962500 1012500>;
>  			opp-supported-hw = <0x4007>;
>  		};
>  
>  		opp-1458000000 {
>  			opp-hz = /bits/ 64 <1458000000>;
>  			opp-peak-kBps = <1134000>;
> +			opp-microvolt-speed0-pvs0 = <1237500 1237500 1262500>;
> +			opp-microvolt-speed0-pvs1 = <1212500 1187500 1237500>;
> +			opp-microvolt-speed0-pvs3 = <1162500 1137500 1187500>;
> +			opp-microvolt-speed0-pvs4 = <1137500 1112500 1162500>;
> +			opp-microvolt-speed1-pvs0 = <1150000 1150000 1175000>;
> +			opp-microvolt-speed1-pvs1 = <1137500 1112500 1162500>;
> +			opp-microvolt-speed1-pvs2 = <1100000 1075000 1125000>;
> +			opp-microvolt-speed1-pvs3 = <1062500 1037500 1087500>;
> +			opp-microvolt-speed1-pvs4 = <1025000 1000000 1050000>;
> +			opp-microvolt-speed1-pvs5 = <1012500 987500 1037500>;
> +			opp-microvolt-speed1-pvs6 = <1000000 975000 1025000>;
> +			opp-microvolt-speed2-pvs0 = <1100000 1100000 1125000>;
> +			opp-microvolt-speed2-pvs1 = <1075000 1075000 1075000>;
> +			opp-microvolt-speed2-pvs2 = <1075000 1050000 1100000>;
> +			opp-microvolt-speed2-pvs3 = <1050000 1025000 1075000>;
> +			opp-microvolt-speed2-pvs4 = <1025000 1000000 1050000>;
> +			opp-microvolt-speed2-pvs5 = <1012500 987500 1037500>;
> +			opp-microvolt-speed2-pvs6 = <1000000 975000 1025000>;
> +			opp-microvolt-speed14-pvs0 = <1150000 1150000 1175000>;
> +			opp-microvolt-speed14-pvs1 = <1137500 1112500 1162500>;
> +			opp-microvolt-speed14-pvs2 = <1100000 1075000 1125000>;
> +			opp-microvolt-speed14-pvs3 = <1062500 1037500 1087500>;
> +			opp-microvolt-speed14-pvs4 = <1025000 1000000 1050000>;
> +			opp-microvolt-speed14-pvs5 = <987500 987500 987500>;
> +			opp-microvolt-speed14-pvs6 = <1000000 975000 1025000>;
>  			opp-supported-hw = <0x4007>;
>  		};
>  
>  		opp-1512000000 {
>  			opp-hz = /bits/ 64 <1512000000>;
>  			opp-peak-kBps = <1134000>;
> +			opp-microvolt-speed0-pvs0 = <1250000 1250000 1275000>;
> +			opp-microvolt-speed0-pvs1 = <1225000 1200000 1250000>;
> +			opp-microvolt-speed0-pvs3 = <1175000 1150000 1200000>;
> +			opp-microvolt-speed0-pvs4 = <1150000 1125000 1175000>;
> +			opp-microvolt-speed14-pvs0 = <1162500 1162500 1187500>;
> +			opp-microvolt-speed14-pvs1 = <1150000 1125000 1175000>;
> +			opp-microvolt-speed14-pvs2 = <1112500 1087500 1137500>;
> +			opp-microvolt-speed14-pvs3 = <1075000 1050000 1100000>;
> +			opp-microvolt-speed14-pvs4 = <1037500 1012500 1062500>;
> +			opp-microvolt-speed14-pvs5 = <1000000 1000000 1000000>;
> +			opp-microvolt-speed14-pvs6 = <1012500 987500 1037500>;
>  			opp-supported-hw = <0x4001>;
>  		};
>  
>  		opp-1566000000 {
>  			opp-hz = /bits/ 64 <1566000000>;
>  			opp-peak-kBps = <1134000>;
> +			opp-microvolt-speed1-pvs0 = <1175000 1175000 1200000>;
> +			opp-microvolt-speed1-pvs1 = <1175000 1150000 1200000>;
> +			opp-microvolt-speed1-pvs2 = <1125000 1100000 1150000>;
> +			opp-microvolt-speed1-pvs3 = <1087500 1062500 1112500>;
> +			opp-microvolt-speed1-pvs4 = <1062500 1037500 1087500>;
> +			opp-microvolt-speed1-pvs5 = <1037500 1012500 1062500>;
> +			opp-microvolt-speed1-pvs6 = <1025000 1000000 1050000>;
> +			opp-microvolt-speed2-pvs0 = <1125000 1125000 1150000>;
> +			opp-microvolt-speed2-pvs1 = <1100000 1100000 1100000>;
> +			opp-microvolt-speed2-pvs2 = <1100000 1075000 1125000>;
> +			opp-microvolt-speed2-pvs3 = <1075000 1050000 1100000>;
> +			opp-microvolt-speed2-pvs4 = <1062500 1037500 1087500>;
> +			opp-microvolt-speed2-pvs5 = <1037500 1012500 1062500>;
> +			opp-microvolt-speed2-pvs6 = <1025000 1000000 1050000>;
>  			opp-supported-hw = <0x06>;
>  		};
>  
>  		opp-1674000000 {
>  			opp-hz = /bits/ 64 <1674000000>;
>  			opp-peak-kBps = <1134000>;
> +			opp-microvolt-speed1-pvs0 = <1225000 1225000 1250000>;
> +			opp-microvolt-speed1-pvs1 = <1212500 1187500 1237500>;
> +			opp-microvolt-speed1-pvs2 = <1162500 1137500 1187500>;
> +			opp-microvolt-speed1-pvs3 = <1125000 1100000 1150000>;
> +			opp-microvolt-speed1-pvs4 = <1100000 1075000 1125000>;
> +			opp-microvolt-speed1-pvs5 = <1075000 1050000 1100000>;
> +			opp-microvolt-speed1-pvs6 = <1050000 1025000 1075000>;
> +			opp-microvolt-speed2-pvs0 = <1175000 1175000 1200000>;
> +			opp-microvolt-speed2-pvs1 = <1137500 1137500 1137500>;
> +			opp-microvolt-speed2-pvs2 = <1137500 1112500 1162500>;
> +			opp-microvolt-speed2-pvs3 = <1112500 1087500 1137500>;
> +			opp-microvolt-speed2-pvs4 = <1100000 1075000 1125000>;
> +			opp-microvolt-speed2-pvs5 = <1075000 1050000 1100000>;
> +			opp-microvolt-speed2-pvs6 = <1050000 1025000 1075000>;
>  			opp-supported-hw = <0x06>;
>  		};
>  
>  		opp-1728000000 {
>  			opp-hz = /bits/ 64 <1728000000>;
>  			opp-peak-kBps = <1134000>;
> +			opp-microvolt-speed1-pvs0 = <1250000 1250000 1275000>;
> +			opp-microvolt-speed1-pvs1 = <1225000 1200000 1250000>;
> +			opp-microvolt-speed1-pvs2 = <1187500 1162500 1212500>;
> +			opp-microvolt-speed1-pvs3 = <1150000 1125000 1175000>;
> +			opp-microvolt-speed1-pvs4 = <1125000 1100000 1150000>;
> +			opp-microvolt-speed1-pvs5 = <1100000 1075000 1125000>;
> +			opp-microvolt-speed1-pvs6 = <1075000 1050000 1100000>;
>  			opp-supported-hw = <0x02>;
>  		};
>  
>  		opp-1782000000 {
>  			opp-hz = /bits/ 64 <1782000000>;
>  			opp-peak-kBps = <1134000>;
> +			opp-microvolt-speed2-pvs0 = <1225000 1225000 1250000>;
> +			opp-microvolt-speed2-pvs1 = <1187500 1187500 1187500>;
> +			opp-microvolt-speed2-pvs2 = <1187500 1162500 1212500>;
> +			opp-microvolt-speed2-pvs3 = <1162500 1137500 1187500>;
> +			opp-microvolt-speed2-pvs4 = <1137500 1112500 1162500>;
> +			opp-microvolt-speed2-pvs5 = <1112500 1087500 1137500>;
> +			opp-microvolt-speed2-pvs6 = <1087500 1062500 1112500>;
>  			opp-supported-hw = <0x04>;
>  		};
>  
>  		opp-1890000000 {
>  			opp-hz = /bits/ 64 <1890000000>;
>  			opp-peak-kBps = <1134000>;
> +			opp-microvolt-speed2-pvs0 = <1287500 1287500 1312500>;
> +			opp-microvolt-speed2-pvs1 = <1250000 1250000 1250000>;
> +			opp-microvolt-speed2-pvs2 = <1237500 1212500 1262500>;
> +			opp-microvolt-speed2-pvs3 = <1200000 1175000 1225000>;
> +			opp-microvolt-speed2-pvs4 = <1175000 1150000 1200000>;
> +			opp-microvolt-speed2-pvs5 = <1150000 1125000 1175000>;
> +			opp-microvolt-speed2-pvs6 = <1125000 1100000 1150000>;
>  			opp-supported-hw = <0x04>;
>  		};
>  	};

Re: [PATCH v2 19/26] ARM: dts: qcom: apq8064: enable passive CPU cooling

[Konrad Dybcio]

On 25.06.2023 22:25, Dmitry Baryshkov wrote:
> Wire up CPUs and thermal trip points to save the SoC from overheating by
> lowering the CPU frequency.
> 
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>

Konrad
>  arch/arm/boot/dts/qcom/qcom-apq8064.dtsi | 29 ++++++++++++++++++++++++
>  1 file changed, 29 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi
> index b97d88517805..f38e3394b422 100644
> --- a/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi
> +++ b/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi
> @@ -11,6 +11,7 @@
>  #include <dt-bindings/soc/qcom,krait-l2-cache.h>
>  #include <dt-bindings/interrupt-controller/irq.h>
>  #include <dt-bindings/interrupt-controller/arm-gic.h>
> +#include <dt-bindings/thermal/thermal.h>
>  / {
>  	#address-cells = <1>;
>  	#size-cells = <1>;
> @@ -701,6 +702,13 @@ cpu_crit0: trip1 {
>  					type = "critical";
>  				};
>  			};
> +
> +			cooling-maps {
> +				map0 {
> +					trip = <&cpu_alert0>;
> +					cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
> +				};
> +			};
>  		};
>  
>  		cpu1-thermal {
> @@ -722,6 +730,13 @@ cpu_crit1: trip1 {
>  					type = "critical";
>  				};
>  			};
> +
> +			cooling-maps {
> +				map0 {
> +					trip = <&cpu_alert1>;
> +					cooling-device = <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
> +				};
> +			};
>  		};
>  
>  		cpu2-thermal {
> @@ -743,6 +758,13 @@ cpu_crit2: trip1 {
>  					type = "critical";
>  				};
>  			};
> +
> +			cooling-maps {
> +				map0 {
> +					trip = <&cpu_alert2>;
> +					cooling-device = <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
> +				};
> +			};
>  		};
>  
>  		cpu3-thermal {
> @@ -764,6 +786,13 @@ cpu_crit3: trip1 {
>  					type = "critical";
>  				};
>  			};
> +
> +			cooling-maps {
> +				map0 {
> +					trip = <&cpu_alert3>;
> +					cooling-device = <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
> +				};
> +			};
>  		};
>  	};
>  

Re: [PATCH v2 20/26] ARM: dts: qcom: apq8064-asus-nexus7-flo: constraint cpufreq regulators

[Konrad Dybcio]

On 25.06.2023 22:25, Dmitry Baryshkov wrote:
> Add additional constraints to the CPUfreq-related regulators, it is
> better be safe than sorry there.
> 
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
I'd say this and similar patches could go earlier in the series..

fwiw:

Acked-by: Konrad Dybcio <konrad.dybcio@linaro.org>

Konrad
>  .../boot/dts/qcom/qcom-apq8064-asus-nexus7-flo.dts | 14 ++++++++++++--
>  1 file changed, 12 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/arm/boot/dts/qcom/qcom-apq8064-asus-nexus7-flo.dts b/arch/arm/boot/dts/qcom/qcom-apq8064-asus-nexus7-flo.dts
> index c57c27cd8a20..9f5d72727356 100644
> --- a/arch/arm/boot/dts/qcom/qcom-apq8064-asus-nexus7-flo.dts
> +++ b/arch/arm/boot/dts/qcom/qcom-apq8064-asus-nexus7-flo.dts
> @@ -218,9 +218,9 @@ s1 {
>  			bias-pull-down;
>  		};
>  
> -		/* msm otg HSUSB_VDDCX */
> +		/* msm otg HSUSB_VDDCX and VDD_DIG */
>  		s3 {
> -			regulator-min-microvolt = <500000>;
> +			regulator-min-microvolt = <950000>;
>  			regulator-max-microvolt = <1150000>;
>  			qcom,switch-mode-frequency = <4800000>;
>  		};
> @@ -301,6 +301,12 @@ l23 {
>  			bias-pull-down;
>  		};
>  
> +		/* VDD_MEM */
> +		l24 {
> +			regulator-min-microvolt = <1050000>;
> +			regulator-max-microvolt = <1150000>;
> +		};
> +
>  		/*
>  		 * tabla2x-slim-CDC_VDDA_A_1P2V
>  		 * tabla2x-slim-VDDD_CDC_D
> @@ -329,8 +335,12 @@ lvs6 {
>  		/*
>  		 * mipi_dsi.1-dsi1_vddio
>  		 * pil_riva-pll_vdd
> +		 * HFPLL regulator
>  		 */
>  		lvs7 {
> +			regulator-min-microvolt = <1800000>;
> +			regulator-max-microvolt = <1800000>;
> +			regulator-boot-on;
>  			bias-pull-down;
>  		};
>  	};

Re: [PATCH v2 21/26] ARM: dts: qcom: apq8064-ifc6410: constraint cpufreq regulators

[Konrad Dybcio]

On 25.06.2023 22:25, Dmitry Baryshkov wrote:
> Add additional constraints to the CPUfreq-related regulators, it is
> better be safe than sorry there.
> 
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
same comment as in p20

Acked-by: Konrad Dybcio <konrad.dybcio@linaro.org>

Konrad
>  .../arm/boot/dts/qcom/qcom-apq8064-ifc6410.dts | 18 ++++++++++++++++--
>  1 file changed, 16 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/arm/boot/dts/qcom/qcom-apq8064-ifc6410.dts b/arch/arm/boot/dts/qcom/qcom-apq8064-ifc6410.dts
> index 96307550523a..ad3cd45362df 100644
> --- a/arch/arm/boot/dts/qcom/qcom-apq8064-ifc6410.dts
> +++ b/arch/arm/boot/dts/qcom/qcom-apq8064-ifc6410.dts
> @@ -215,8 +215,8 @@ s1 {
>  		};
>  
>  		s3 {
> -			regulator-min-microvolt = <1000000>;
> -			regulator-max-microvolt = <1400000>;
> +			regulator-min-microvolt = <950000>;
> +			regulator-max-microvolt = <1150000>;
>  			qcom,switch-mode-frequency = <4800000>;
>  		};
>  
> @@ -262,6 +262,12 @@ l23 {
>  			bias-pull-down;
>  		};
>  
> +		l24 {
> +			regulator-min-microvolt = <1050000>;
> +			regulator-max-microvolt = <1150000>;
> +			bias-pull-down;
> +		};
> +
>  		lvs1 {
>  			bias-pull-down;
>  		};
> @@ -269,6 +275,14 @@ lvs1 {
>  		lvs6 {
>  			bias-pull-down;
>  		};
> +
> +		/* HFPLL regulator */
> +		lvs7 {
> +			regulator-min-microvolt = <1800000>;
> +			regulator-max-microvolt = <1800000>;
> +			regulator-boot-on;
> +			regulator-always-on;
> +		};
>  	};
>  };
>  

Re: [PATCH v2 16/26] ARM: dts: qcom: apq8064: add L2 cache scaling

[Konrad Dybcio]

On 26.06.2023 18:37, Konrad Dybcio wrote:
> On 25.06.2023 22:25, Dmitry Baryshkov wrote:
>> Populate L2 cache node with clock, supplies and OPP information to
>> facilitate scaling L2 frequency.
>>
>> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
>> ---
> Are the L2 voltage ranges independent of speedbin?
> 
> Konrad
>>  arch/arm/boot/dts/qcom/qcom-apq8064.dtsi | 101 ++++++++++++++++++++++-
>>  1 file changed, 100 insertions(+), 1 deletion(-)
>>
>> diff --git a/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi
>> index 1eb6d752ebae..ac07170c702f 100644
>> --- a/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi
>> +++ b/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi
>> @@ -81,9 +81,108 @@ CPU3: cpu@3 {
>>  		};
>>  
>>  		L2: l2-cache {
>> -			compatible = "cache";
>> +			compatible = "qcom,krait-l2-cache", "cache";
>>  			cache-level = <2>;
>>  			cache-unified;
>> +			vdd-mem-supply = <&pm8921_l24>;
>> +			vdd-dig-supply = <&pm8921_s3>;
Another thing I've noticed.. we've grown out of referencing
PMIC specifics in the SoC dtsi..

Do we know what PMIC configurations has this one shipped with?

Konrad
>> +			clocks = <&kraitcc KRAIT_L2>;
>> +			#interconnect-cells = <1>;
>> +			operating-points-v2 = <&l2_opp_table>;
>> +
>> +			l2_opp_table: opp-table-l2 {
>> +				compatible = "operating-points-v2";
>> +
>> +				opp-384000000 {
>> +					opp-hz = /bits/ 64 <384000000>;
>> +					opp-microvolt = <1050000 1050000 1150000>,
>> +							<950000 950000 1150000>;
>> +				};
>> +
>> +				opp-432000000 {
>> +					opp-hz = /bits/ 64 <432000000>;
>> +					opp-microvolt = <1050000 1050000 1150000>,
>> +							<1050000 1050000 1150000>;
>> +				};
>> +
>> +				opp-486000000 {
>> +					opp-hz = /bits/ 64 <486000000>;
>> +					opp-microvolt = <1050000 1050000 1150000>,
>> +							<1050000 1050000 1150000>;
>> +				};
>> +
>> +				opp-540000000 {
>> +					opp-hz = /bits/ 64 <540000000>;
>> +					opp-microvolt = <1050000 1050000 1150000>,
>> +							<1050000 1050000 1150000>;
>> +				};
>> +
>> +				opp-594000000 {
>> +					opp-hz = /bits/ 64 <594000000>;
>> +					opp-microvolt = <1050000 1050000 1150000>,
>> +							<1050000 1050000 1150000>;
>> +				};
>> +
>> +				opp-648000000 {
>> +					opp-hz = /bits/ 64 <648000000>;
>> +					opp-microvolt = <1050000 1050000 1150000>,
>> +							<1050000 1050000 1150000>;
>> +				};
>> +
>> +				opp-702000000 {
>> +					opp-hz = /bits/ 64 <702000000>;
>> +					opp-microvolt = <1150000 1150000 1150000>,
>> +							<1150000 1150000 1150000>;
>> +				};
>> +
>> +				opp-756000000 {
>> +					opp-hz = /bits/ 64 <756000000>;
>> +					opp-microvolt = <1150000 1150000 1150000>,
>> +							<1150000 1150000 1150000>;
>> +				};
>> +
>> +				opp-810000000 {
>> +					opp-hz = /bits/ 64 <810000000>;
>> +					opp-microvolt = <1150000 1150000 1150000>,
>> +							<1150000 1150000 1150000>;
>> +				};
>> +
>> +				opp-864000000 {
>> +					opp-hz = /bits/ 64 <864000000>;
>> +					opp-microvolt = <1150000 1150000 1150000>,
>> +							<1150000 1150000 1150000>;
>> +				};
>> +
>> +				opp-918000000 {
>> +					opp-hz = /bits/ 64 <918000000>;
>> +					opp-microvolt = <1150000 1150000 1150000>,
>> +							<1150000 1150000 1150000>;
>> +				};
>> +
>> +				opp-972000000 {
>> +					opp-hz = /bits/ 64 <972000000>;
>> +					opp-microvolt = <1150000 1150000 1150000>,
>> +							<1150000 1150000 1150000>;
>> +				};
>> +
>> +				opp-1026000000 {
>> +					opp-hz = /bits/ 64 <1026000000>;
>> +					opp-microvolt = <1150000 1150000 1150000>,
>> +							<1150000 1150000 1150000>;
>> +				};
>> +
>> +				opp-1080000000 {
>> +					opp-hz = /bits/ 64 <1080000000>;
>> +					opp-microvolt = <1150000 1150000 1150000>,
>> +							<1150000 1150000 1150000>;
>> +				};
>> +
>> +				opp-1134000000 {
>> +					opp-hz = /bits/ 64 <1134000000>;
>> +					opp-microvolt = <1150000 1150000 1150000>,
>> +							<1150000 1150000 1150000>;
>> +				};
>> +			};
>>  		};
>>  
>>  		idle-states {

Re: [PATCH v2 06/26] interconnect: icc-clk: add support for scaling using OPP

[Konrad Dybcio]

On 26.06.2023 15:44, Dmitry Baryshkov wrote:
> On 26/06/2023 14:28, Konrad Dybcio wrote:
>> On 25.06.2023 22:25, Dmitry Baryshkov wrote:
>>> Sometimes it might be required to scale the clock using the OPP
>>> framework (e.g. to scale regulators following the required clock rate).
>>> Extend the interconnec
>> 't'
>>
>>> -clk framework to handle OPP case in addition to
>>> scaling the clock.
>>>
>>> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
>>> ---
>> I think we should check for OPP at the icc-clk registration time,
>> instead of passing it as a parameter, e.g.:
>>
>> qn.opp = IS_ERR(dev_pm_opp_get_opp_count)
>>
>> Not sure if there's a more idiomatic way.
> 
> No. icc-clk is not limited to a single clock->icc conversion. So it is possible to create several interconnect links, only one of which should be the OPP-based one.
Ugh. Right.

Konrad
> 
>>
>> Konrad
>>>   drivers/interconnect/icc-clk.c   | 13 +++++++++++--
>>>   include/linux/interconnect-clk.h |  1 +
>>>   2 files changed, 12 insertions(+), 2 deletions(-)
>>>
>>> diff --git a/drivers/interconnect/icc-clk.c b/drivers/interconnect/icc-clk.c
>>> index 4d43ebff4257..c7962acdcee7 100644
>>> --- a/drivers/interconnect/icc-clk.c
>>> +++ b/drivers/interconnect/icc-clk.c
>>> @@ -7,10 +7,13 @@
>>>   #include <linux/device.h>
>>>   #include <linux/interconnect-clk.h>
>>>   #include <linux/interconnect-provider.h>
>>> +#include <linux/pm_opp.h>
>>>     struct icc_clk_node {
>>> +    struct device *dev;
>>>       struct clk *clk;
>>>       bool enabled;
>>> +    bool opp;
>>>   };
>>>     struct icc_clk_provider {
>>> @@ -25,12 +28,16 @@ struct icc_clk_provider {
>>>   static int icc_clk_set(struct icc_node *src, struct icc_node *dst)
>>>   {
>>>       struct icc_clk_node *qn = src->data;
>>> +    unsigned long rate = icc_units_to_bps(src->peak_bw);
>>>       int ret;
>>>         if (!qn || !qn->clk)
>>>           return 0;
>>>   -    if (!src->peak_bw) {
>>> +    if (qn->opp)
>>> +        return dev_pm_opp_set_rate(qn->dev, rate);
>>> +
>>> +    if (!rate) {
>>>           if (qn->enabled)
>>>               clk_disable_unprepare(qn->clk);
>>>           qn->enabled = false;
>>> @@ -45,7 +52,7 @@ static int icc_clk_set(struct icc_node *src, struct icc_node *dst)
>>>           qn->enabled = true;
>>>       }
>>>   -    return clk_set_rate(qn->clk, icc_units_to_bps(src->peak_bw));
>>> +    return clk_set_rate(qn->clk, rate);
>>>   }
>>>     static int icc_clk_get_bw(struct icc_node *node, u32 *avg, u32 *peak)
>>> @@ -106,7 +113,9 @@ struct icc_provider *icc_clk_register(struct device *dev,
>>>       icc_provider_init(provider);
>>>         for (i = 0, j = 0; i < num_clocks; i++) {
>>> +        qp->clocks[i].dev = dev;
>>>           qp->clocks[i].clk = data[i].clk;
>>> +        qp->clocks[i].opp = data[i].opp;
>>>             node = icc_node_create(first_id + j);
>>>           if (IS_ERR(node)) {
>>> diff --git a/include/linux/interconnect-clk.h b/include/linux/interconnect-clk.h
>>> index 0cd80112bea5..c695e5099901 100644
>>> --- a/include/linux/interconnect-clk.h
>>> +++ b/include/linux/interconnect-clk.h
>>> @@ -11,6 +11,7 @@ struct device;
>>>   struct icc_clk_data {
>>>       struct clk *clk;
>>>       const char *name;
>>> +    bool opp;
>>>   };
>>>     struct icc_provider *icc_clk_register(struct device *dev,
> 

Re: [PATCH v2 16/26] ARM: dts: qcom: apq8064: add L2 cache scaling

[Dmitry Baryshkov]

On 26/06/2023 19:46, Konrad Dybcio wrote:
> On 26.06.2023 18:37, Konrad Dybcio wrote:
>> On 25.06.2023 22:25, Dmitry Baryshkov wrote:
>>> Populate L2 cache node with clock, supplies and OPP information to
>>> facilitate scaling L2 frequency.
>>>
>>> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
>>> ---
>> Are the L2 voltage ranges independent of speedbin?

Yes. Only Core freq and voltage seem to be a matter of speedbin/pvs 
classification.

>>
>> Konrad
>>>   arch/arm/boot/dts/qcom/qcom-apq8064.dtsi | 101 ++++++++++++++++++++++-
>>>   1 file changed, 100 insertions(+), 1 deletion(-)
>>>
>>> diff --git a/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi
>>> index 1eb6d752ebae..ac07170c702f 100644
>>> --- a/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi
>>> +++ b/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi
>>> @@ -81,9 +81,108 @@ CPU3: cpu@3 {
>>>   		};
>>>   
>>>   		L2: l2-cache {
>>> -			compatible = "cache";
>>> +			compatible = "qcom,krait-l2-cache", "cache";
>>>   			cache-level = <2>;
>>>   			cache-unified;
>>> +			vdd-mem-supply = <&pm8921_l24>;
>>> +			vdd-dig-supply = <&pm8921_s3>;
> Another thing I've noticed.. we've grown out of referencing
> PMIC specifics in the SoC dtsi..
> 
> Do we know what PMIC configurations has this one shipped with?

It is either pm8921+pm8821, or pmm8920, which integrates pm8921 and 
pm8921 dies in a single module (but keeps software interface).
In theory splitting pm8921 to a separate file would allow somewhat more 
sharing between msm8960 and apq8064. Let me take a look.

-- 
With best wishes
Dmitry

Re: [PATCH v2 17/26] ARM: dts: qcom: apq8064: add simple CPUFreq support

[Dmitry Baryshkov]

On 26/06/2023 19:40, Konrad Dybcio wrote:
> On 25.06.2023 22:25, Dmitry Baryshkov wrote:
>> Declare CPU frequency-scaling properties. Each CPU has its own clock,
>> how
> however?

yes

> 
>> all CPUs have the same OPP table. Voltage scaling is not (yet)
>> enabled with this patch. It will be enabled later.
> Risky business.

But it works :D

> 
>>
>> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
>> ---
>>   arch/arm/boot/dts/qcom/qcom-apq8064.dtsi | 170 +++++++++++++++++++++++
>>   1 file changed, 170 insertions(+)
>>
>> diff --git a/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi
>> index ac07170c702f..e4d2fd48d843 100644
>> --- a/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi
>> +++ b/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi
>> @@ -2,11 +2,13 @@
>>   /dts-v1/;
>>   
>>   #include <dt-bindings/clock/qcom,gcc-msm8960.h>
>> +#include <dt-bindings/clock/qcom,krait-cc.h>
>>   #include <dt-bindings/clock/qcom,lcc-msm8960.h>
>>   #include <dt-bindings/reset/qcom,gcc-msm8960.h>
>>   #include <dt-bindings/clock/qcom,mmcc-msm8960.h>
>>   #include <dt-bindings/clock/qcom,rpmcc.h>
>>   #include <dt-bindings/soc/qcom,gsbi.h>
>> +#include <dt-bindings/soc/qcom,krait-l2-cache.h>
>>   #include <dt-bindings/interrupt-controller/irq.h>
>>   #include <dt-bindings/interrupt-controller/arm-gic.h>
>>   / {
>> @@ -45,6 +47,12 @@ CPU0: cpu@0 {
>>   			qcom,acc = <&acc0>;
>>   			qcom,saw = <&saw0>;
>>   			cpu-idle-states = <&CPU_SPC>;
>> +			clocks = <&kraitcc KRAIT_CPU_0>;
>> +			clock-names = "cpu";
>> +			clock-latency = <100000>;
>> +			interconnects = <&L2 MASTER_KRAIT_L2 &L2 SLAVE_KRAIT_L2>;
>> +			operating-points-v2 = <&cpu_opp_table>;
>> +			#cooling-cells = <2>;
>>   		};
>>   
>>   		CPU1: cpu@1 {
>> @@ -56,6 +64,12 @@ CPU1: cpu@1 {
>>   			qcom,acc = <&acc1>;
>>   			qcom,saw = <&saw1>;
>>   			cpu-idle-states = <&CPU_SPC>;
>> +			clocks = <&kraitcc KRAIT_CPU_1>;
>> +			clock-names = "cpu";
>> +			clock-latency = <100000>;
>> +			interconnects = <&L2 MASTER_KRAIT_L2 &L2 SLAVE_KRAIT_L2>;
>> +			operating-points-v2 = <&cpu_opp_table>;
>> +			#cooling-cells = <2>;
>>   		};
>>   
>>   		CPU2: cpu@2 {
>> @@ -67,6 +81,12 @@ CPU2: cpu@2 {
>>   			qcom,acc = <&acc2>;
>>   			qcom,saw = <&saw2>;
>>   			cpu-idle-states = <&CPU_SPC>;
>> +			clocks = <&kraitcc KRAIT_CPU_2>;
>> +			clock-names = "cpu";
>> +			clock-latency = <100000>;
>> +			interconnects = <&L2 MASTER_KRAIT_L2 &L2 SLAVE_KRAIT_L2>;
>> +			operating-points-v2 = <&cpu_opp_table>;
>> +			#cooling-cells = <2>;
>>   		};
>>   
>>   		CPU3: cpu@3 {
>> @@ -78,6 +98,12 @@ CPU3: cpu@3 {
>>   			qcom,acc = <&acc3>;
>>   			qcom,saw = <&saw3>;
>>   			cpu-idle-states = <&CPU_SPC>;
>> +			clocks = <&kraitcc KRAIT_CPU_3>;
>> +			clock-names = "cpu";
>> +			clock-latency = <100000>;
>> +			interconnects = <&L2 MASTER_KRAIT_L2 &L2 SLAVE_KRAIT_L2>;
>> +			operating-points-v2 = <&cpu_opp_table>;
>> +			#cooling-cells = <2>;
>>   		};
>>   
>>   		L2: l2-cache {
>> @@ -196,6 +222,121 @@ CPU_SPC: spc {
>>   		};
>>   	};
>>   
>> +        cpu_opp_table: opp-table-cpu {
>> +		compatible = "operating-points-v2-krait-cpu";
>> +		nvmem-cells = <&speedbin_efuse>;
>> +
>> +		/*
>> +		 * Voltage thresholds are <target min max>
>> +		 */
> What voltage thresholds?

Ack, should be moved to the next patch.

> 
>> +		opp-384000000 {
>> +			opp-hz = /bits/ 64 <384000000>;
>> +			opp-peak-kBps = <384000>;
>> +			opp-supported-hw = <0x4007>;
>> +			/*
>> +			 * higher latency as it requires switching between
>> +			 * clock sources
>> +			 */
>> +			clock-latency-ns = <244144>;
>> +		};
>> +
>> +		opp-486000000 {
>> +			opp-hz = /bits/ 64 <486000000>;
>> +			opp-peak-kBps = <648000>;
>> +			opp-supported-hw = <0x4007>;
>> +		};
>> +
>> +		opp-594000000 {
>> +			opp-hz = /bits/ 64 <594000000>;
>> +			opp-peak-kBps = <648000>;
>> +			opp-supported-hw = <0x4007>;
>> +		};
>> +
>> +		opp-702000000 {
>> +			opp-hz = /bits/ 64 <702000000>;
>> +			opp-peak-kBps = <648000>;
>> +			opp-supported-hw = <0x4007>;
>> +		};
>> +
>> +		opp-810000000 {
>> +			opp-hz = /bits/ 64 <810000000>;
>> +			opp-peak-kBps = <648000>;
>> +			opp-supported-hw = <0x4007>;
>> +		};
>> +
>> +		opp-918000000 {
>> +			opp-hz = /bits/ 64 <918000000>;
>> +			opp-peak-kBps = <648000>;
>> +			opp-supported-hw = <0x4007>;
>> +		};
>> +
>> +		opp-1026000000 {
>> +			opp-hz = /bits/ 64 <1026000000>;
>> +			opp-peak-kBps = <648000>;
>> +			opp-supported-hw = <0x4007>;
>> +		};
>> +
>> +		opp-1134000000 {
>> +			opp-hz = /bits/ 64 <1134000000>;
>> +			opp-peak-kBps = <1134000>;
>> +			opp-supported-hw = <0x4007>;
>> +		};
>> +
>> +		opp-1242000000 {
>> +			opp-hz = /bits/ 64 <1242000000>;
>> +			opp-peak-kBps = <1134000>;
>> +			opp-supported-hw = <0x4007>;
>> +		};
>> +
>> +		opp-1350000000 {
>> +			opp-hz = /bits/ 64 <1350000000>;
>> +			opp-peak-kBps = <1134000>;
>> +			opp-supported-hw = <0x4007>;
>> +		};
>> +
>> +		opp-1458000000 {
>> +			opp-hz = /bits/ 64 <1458000000>;
>> +			opp-peak-kBps = <1134000>;
>> +			opp-supported-hw = <0x4007>;
>> +		};
>> +
>> +		opp-1512000000 {
>> +			opp-hz = /bits/ 64 <1512000000>;
>> +			opp-peak-kBps = <1134000>;
>> +			opp-supported-hw = <0x4001>;
>> +		};
>> +
>> +		opp-1566000000 {
>> +			opp-hz = /bits/ 64 <1566000000>;
>> +			opp-peak-kBps = <1134000>;
>> +			opp-supported-hw = <0x06>;
>> +		};
>> +
>> +		opp-1674000000 {
>> +			opp-hz = /bits/ 64 <1674000000>;
>> +			opp-peak-kBps = <1134000>;
>> +			opp-supported-hw = <0x06>;
>> +		};
>> +
>> +		opp-1728000000 {
>> +			opp-hz = /bits/ 64 <1728000000>;
>> +			opp-peak-kBps = <1134000>;
>> +			opp-supported-hw = <0x02>;
>> +		};
>> +
>> +		opp-1782000000 {
>> +			opp-hz = /bits/ 64 <1782000000>;
>> +			opp-peak-kBps = <1134000>;
>> +			opp-supported-hw = <0x04>;
>> +		};
>> +
>> +		opp-1890000000 {
>> +			opp-hz = /bits/ 64 <1890000000>;
>> +			opp-peak-kBps = <1134000>;
>> +			opp-supported-hw = <0x04>;
>> +		};
>> +	};
>> +
>>   	memory@0 {
>>   		device_type = "memory";
>>   		reg = <0x0 0x0>;
>> @@ -312,6 +453,32 @@ sleep_clk: sleep_clk {
>>   		};
>>   	};
>>   
>> +	kraitcc: clock-controller {
>> +		compatible = "qcom,krait-cc-v1";
> Are we sure we don't wanna rework this compatible? Check the comment in
> drivers/clk/qcom/krait-cc.c : krait_add_sec_mux()

I remember that comment. I'd rather not introduce another compat string 
for such old hw. Would there be any direct benefits?

> 
> 
>> +		clocks = <&gcc PLL9>, /* hfpll0 */
>> +			 <&gcc PLL10>, /* hfpll1 */
>> +			 <&gcc PLL16>, /* hfpll2 */
>> +			 <&gcc PLL17>, /* hfpll3 */
>> +			 <&gcc PLL12>, /* hfpll_l2 */
>> +			 <&acc0>,
>> +			 <&acc1>,
>> +			 <&acc2>,
>> +			 <&acc3>,
>> +			 <&l2cc>;
>> +		clock-names = "hfpll0",
>> +			      "hfpll1",
>> +			      "hfpll2",
>> +			      "hfpll3",
>> +			      "hfpll_l2",
>> +			      "acpu0_aux",
>> +			      "acpu1_aux",
>> +			      "acpu2_aux",
>> +			      "acpu3_aux",
>> +			      "acpu_l2_aux";
>> +		#clock-cells = <1>;
>> +		#interconnect-cells = <1>;
>> +	};
>> +
>>   	sfpb_mutex: hwmutex {
>>   		compatible = "qcom,sfpb-mutex";
>>   		syscon = <&sfpb_wrapper_mutex 0x604 0x4>;
>> @@ -933,6 +1100,9 @@ qfprom: qfprom@700000 {
>>   			#address-cells = <1>;
>>   			#size-cells = <1>;
>>   			ranges;
>> +			speedbin_efuse: speedbin@c0 {
>> +				reg = <0x0c0 0x4>;
>> +			};
> Newline between properties and subnodes & between individual subnodes,
> please

ack.

> 
> Konrad
>>   			tsens_calib: calib@404 {
>>   				reg = <0x404 0x10>;
>>   			};

-- 
With best wishes
Dmitry

Re: [PATCH v2 17/26] ARM: dts: qcom: apq8064: add simple CPUFreq support

[Konrad Dybcio]

On 26.06.2023 21:49, Dmitry Baryshkov wrote:
> On 26/06/2023 19:40, Konrad Dybcio wrote:
>> On 25.06.2023 22:25, Dmitry Baryshkov wrote:
>>> Declare CPU frequency-scaling properties. Each CPU has its own clock,
>>> how
>> however?
> 
> yes
> 
>>
>>> all CPUs have the same OPP table. Voltage scaling is not (yet)
>>> enabled with this patch. It will be enabled later.
>> Risky business.
> 
> But it works :D
On your machine ;)

[...]

>>>   +    kraitcc: clock-controller {
>>> +        compatible = "qcom,krait-cc-v1";
>> Are we sure we don't wanna rework this compatible? Check the comment in
>> drivers/clk/qcom/krait-cc.c : krait_add_sec_mux()
> 
> I remember that comment. I'd rather not introduce another compat string for such old hw. Would there be any direct benefits?
> 
I'd say that the one we have here never made much sense.. Perhaps (since
nobody used it for 10 years) it would make sense to remodel it..

Konrad
>>
>>
>>> +        clocks = <&gcc PLL9>, /* hfpll0 */
>>> +             <&gcc PLL10>, /* hfpll1 */
>>> +             <&gcc PLL16>, /* hfpll2 */
>>> +             <&gcc PLL17>, /* hfpll3 */
>>> +             <&gcc PLL12>, /* hfpll_l2 */
>>> +             <&acc0>,
>>> +             <&acc1>,
>>> +             <&acc2>,
>>> +             <&acc3>,
>>> +             <&l2cc>;
>>> +        clock-names = "hfpll0",
>>> +                  "hfpll1",
>>> +                  "hfpll2",
>>> +                  "hfpll3",
>>> +                  "hfpll_l2",
>>> +                  "acpu0_aux",
>>> +                  "acpu1_aux",
>>> +                  "acpu2_aux",
>>> +                  "acpu3_aux",
>>> +                  "acpu_l2_aux";
>>> +        #clock-cells = <1>;
>>> +        #interconnect-cells = <1>;
>>> +    };
>>> +
>>>       sfpb_mutex: hwmutex {
>>>           compatible = "qcom,sfpb-mutex";
>>>           syscon = <&sfpb_wrapper_mutex 0x604 0x4>;
>>> @@ -933,6 +1100,9 @@ qfprom: qfprom@700000 {
>>>               #address-cells = <1>;
>>>               #size-cells = <1>;
>>>               ranges;
>>> +            speedbin_efuse: speedbin@c0 {
>>> +                reg = <0x0c0 0x4>;
>>> +            };
>> Newline between properties and subnodes & between individual subnodes,
>> please
> 
> ack.
> 
>>
>> Konrad
>>>               tsens_calib: calib@404 {
>>>                   reg = <0x404 0x10>;
>>>               };
> 

Re: [PATCH v2 17/26] ARM: dts: qcom: apq8064: add simple CPUFreq support

[Dmitry Baryshkov]

On Tue, 27 Jun 2023 at 15:13, Konrad Dybcio <konrad.dybcio@linaro.org> wrote:
>
> On 26.06.2023 21:49, Dmitry Baryshkov wrote:
> > On 26/06/2023 19:40, Konrad Dybcio wrote:
> >> On 25.06.2023 22:25, Dmitry Baryshkov wrote:
> >>> Declare CPU frequency-scaling properties. Each CPU has its own clock,
> >>> how
> >> however?
> >
> > yes
> >
> >>
> >>> all CPUs have the same OPP table. Voltage scaling is not (yet)
> >>> enabled with this patch. It will be enabled later.
> >> Risky business.
> >
> > But it works :D
> On your machine ;)

On two nexus-7 and one ifc6410.

>
> [...]
>
> >>>   +    kraitcc: clock-controller {
> >>> +        compatible = "qcom,krait-cc-v1";
> >> Are we sure we don't wanna rework this compatible? Check the comment in
> >> drivers/clk/qcom/krait-cc.c : krait_add_sec_mux()
> >
> > I remember that comment. I'd rather not introduce another compat string for such old hw. Would there be any direct benefits?
> >
> I'd say that the one we have here never made much sense.. Perhaps (since
> nobody used it for 10 years) it would make sense to remodel it..

Well we have the bindings for this driver. And also it was used by the
OpenWRT people, IIRC.
Thus I don't feel comfortable with throwing out old compat strings.

>
> Konrad
> >>
> >>
> >>> +        clocks = <&gcc PLL9>, /* hfpll0 */
> >>> +             <&gcc PLL10>, /* hfpll1 */
> >>> +             <&gcc PLL16>, /* hfpll2 */
> >>> +             <&gcc PLL17>, /* hfpll3 */
> >>> +             <&gcc PLL12>, /* hfpll_l2 */
> >>> +             <&acc0>,
> >>> +             <&acc1>,
> >>> +             <&acc2>,
> >>> +             <&acc3>,
> >>> +             <&l2cc>;
> >>> +        clock-names = "hfpll0",
> >>> +                  "hfpll1",
> >>> +                  "hfpll2",
> >>> +                  "hfpll3",
> >>> +                  "hfpll_l2",
> >>> +                  "acpu0_aux",
> >>> +                  "acpu1_aux",
> >>> +                  "acpu2_aux",
> >>> +                  "acpu3_aux",
> >>> +                  "acpu_l2_aux";
> >>> +        #clock-cells = <1>;
> >>> +        #interconnect-cells = <1>;
> >>> +    };
> >>> +
> >>>       sfpb_mutex: hwmutex {
> >>>           compatible = "qcom,sfpb-mutex";
> >>>           syscon = <&sfpb_wrapper_mutex 0x604 0x4>;
> >>> @@ -933,6 +1100,9 @@ qfprom: qfprom@700000 {
> >>>               #address-cells = <1>;
> >>>               #size-cells = <1>;
> >>>               ranges;
> >>> +            speedbin_efuse: speedbin@c0 {
> >>> +                reg = <0x0c0 0x4>;
> >>> +            };
> >> Newline between properties and subnodes & between individual subnodes,
> >> please
> >
> > ack.
> >
> >>
> >> Konrad
> >>>               tsens_calib: calib@404 {
> >>>                   reg = <0x404 0x10>;
> >>>               };
> >



-- 
With best wishes
Dmitry

Re: [PATCH v2 17/26] ARM: dts: qcom: apq8064: add simple CPUFreq support

[Konrad Dybcio]

On 27.06.2023 16:11, Dmitry Baryshkov wrote:
> On Tue, 27 Jun 2023 at 15:13, Konrad Dybcio <konrad.dybcio@linaro.org> wrote:
>>
>> On 26.06.2023 21:49, Dmitry Baryshkov wrote:
>>> On 26/06/2023 19:40, Konrad Dybcio wrote:
>>>> On 25.06.2023 22:25, Dmitry Baryshkov wrote:
>>>>> Declare CPU frequency-scaling properties. Each CPU has its own clock,
>>>>> how
>>>> however?
>>>
>>> yes
>>>
>>>>
>>>>> all CPUs have the same OPP table. Voltage scaling is not (yet)
>>>>> enabled with this patch. It will be enabled later.
>>>> Risky business.
>>>
>>> But it works :D
>> On your machine ;)
> 
> On two nexus-7 and one ifc6410.
> 
>>
>> [...]
>>
>>>>>   +    kraitcc: clock-controller {
>>>>> +        compatible = "qcom,krait-cc-v1";
>>>> Are we sure we don't wanna rework this compatible? Check the comment in
>>>> drivers/clk/qcom/krait-cc.c : krait_add_sec_mux()
>>>
>>> I remember that comment. I'd rather not introduce another compat string for such old hw. Would there be any direct benefits?
>>>
>> I'd say that the one we have here never made much sense.. Perhaps (since
>> nobody used it for 10 years) it would make sense to remodel it..
> 
> Well we have the bindings for this driver. And also it was used by the
> OpenWRT people, IIRC.
> Thus I don't feel comfortable with throwing out old compat strings.
Oh, OK

Konrad
> 
>>
>> Konrad
>>>>
>>>>
>>>>> +        clocks = <&gcc PLL9>, /* hfpll0 */
>>>>> +             <&gcc PLL10>, /* hfpll1 */
>>>>> +             <&gcc PLL16>, /* hfpll2 */
>>>>> +             <&gcc PLL17>, /* hfpll3 */
>>>>> +             <&gcc PLL12>, /* hfpll_l2 */
>>>>> +             <&acc0>,
>>>>> +             <&acc1>,
>>>>> +             <&acc2>,
>>>>> +             <&acc3>,
>>>>> +             <&l2cc>;
>>>>> +        clock-names = "hfpll0",
>>>>> +                  "hfpll1",
>>>>> +                  "hfpll2",
>>>>> +                  "hfpll3",
>>>>> +                  "hfpll_l2",
>>>>> +                  "acpu0_aux",
>>>>> +                  "acpu1_aux",
>>>>> +                  "acpu2_aux",
>>>>> +                  "acpu3_aux",
>>>>> +                  "acpu_l2_aux";
>>>>> +        #clock-cells = <1>;
>>>>> +        #interconnect-cells = <1>;
>>>>> +    };
>>>>> +
>>>>>       sfpb_mutex: hwmutex {
>>>>>           compatible = "qcom,sfpb-mutex";
>>>>>           syscon = <&sfpb_wrapper_mutex 0x604 0x4>;
>>>>> @@ -933,6 +1100,9 @@ qfprom: qfprom@700000 {
>>>>>               #address-cells = <1>;
>>>>>               #size-cells = <1>;
>>>>>               ranges;
>>>>> +            speedbin_efuse: speedbin@c0 {
>>>>> +                reg = <0x0c0 0x4>;
>>>>> +            };
>>>> Newline between properties and subnodes & between individual subnodes,
>>>> please
>>>
>>> ack.
>>>
>>>>
>>>> Konrad
>>>>>               tsens_calib: calib@404 {
>>>>>                   reg = <0x404 0x10>;
>>>>>               };
>>>
> 
> 
> 

Re: [PATCH v2 01/26] dt-bindings: opp: opp-v2-kryo-cpu: support Qualcomm Krait SoCs

[Rob Herring]

On Sun, 25 Jun 2023 23:25:22 +0300, Dmitry Baryshkov wrote:
> Exted the opp-v2-kryo-cpu.yaml to support defining OPP tables for the
> previous generation of Qualcomm CPUs, 32-bit Krait-based platforms.
> 
> It makes no sense to use 'operating-points-v2-kryo-cpu' compatibility
> node for the Krait cores. Add support for the Krait-specific
> 'operating-points-v2-krait-cpu' compatibility string and the relevant
> opp-microvolt subclasses properties.
> 
> The listed opp-supported-hw values are applicable only to msm8996 /
> msm8996pro platforms. Remove the enum as other platforms will use other
> bit values. It makes little sense to list all possible values for all
> the platforms here.
> 
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
>  .../devicetree/bindings/opp/opp-v2-kryo-cpu.yaml     | 12 ++++++++----
>  1 file changed, 8 insertions(+), 4 deletions(-)
> 

Acked-by: Rob Herring <robh@kernel.org>

Re: [PATCH v2 02/26] dt-bindings: soc: qcom: merge qcom,saw2.txt into qcom,spm.yaml

[Rob Herring]

On Sun, Jun 25, 2023 at 11:25:23PM +0300, Dmitry Baryshkov wrote:
> The Qualcomm SPM / SAW2 device is described in two bindigns files:

bindings

> arm/msm/qcom,saw2.txt and soc/qcom/qcom,spm.yaml. Merge the former into
> the latter, adding detailed device node description. While we are at it,
> also rename qcom,spm.yaml to qcom,saw2.yaml to follow the actual
> compatible used for these devices.
> 
> The regulator property is retained as is. It will be changed in the
> later patches.
> 
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
>  .../devicetree/bindings/arm/msm/qcom,saw2.txt | 58 -------------------
>  .../qcom/{qcom,spm.yaml => qcom,saw2.yaml}    | 26 +++++++--
>  2 files changed, 20 insertions(+), 64 deletions(-)
>  delete mode 100644 Documentation/devicetree/bindings/arm/msm/qcom,saw2.txt
>  rename Documentation/devicetree/bindings/soc/qcom/{qcom,spm.yaml => qcom,saw2.yaml} (64%)

Reviewed-by: Rob Herring <robh@kernel.org>

Re: [PATCH v2 03/26] dt-bindings: soc: qcom: qcom,saw2: define optional regulator node

[Rob Herring]

On Sun, 25 Jun 2023 23:25:24 +0300, Dmitry Baryshkov wrote:
> The SAW2 device can optionally provide a voltage regulator supplying the
> CPU core, cluster or L2 cache. Change the boolean 'regulator' property
> into a proper regulator description. This breaks schema compatibility
> for the sake of properly describing the regulator.
> 
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
>  .../devicetree/bindings/soc/qcom/qcom,saw2.yaml   | 15 ++++++++++++++-
>  1 file changed, 14 insertions(+), 1 deletion(-)
> 

Reviewed-by: Rob Herring <robh@kernel.org>

Re: [PATCH v2 04/26] dt-bindings: clock: qcom,krait-cc: Krait core clock controller

[Rob Herring]

On Sun, 25 Jun 2023 23:25:25 +0300, Dmitry Baryshkov wrote:
> Define bindings for the Qualcomm Krait CPU and L2 clock controller. This
> device is used on old Qualcomm SoCs (APQ8064, MSM8960) and supports up
> to 4 core clocks and a separate L2 clock. Furthermore, L2 clock is
> represented as the interconnect to facilitate L2 frequency scaling
> together with scaling the CPU frequencies.
> 
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
>  include/dt-bindings/clock/qcom,krait-cc.h | 17 +++++++++++++++++
>  1 file changed, 17 insertions(+)
>  create mode 100644 include/dt-bindings/clock/qcom,krait-cc.h
> 

Acked-by: Rob Herring <robh@kernel.org>

Re: [PATCH v2 13/26] soc: qcom: Add driver for Qualcomm Krait L2 cache scaling

[Konrad Dybcio]

On 25.06.2023 22:25, Dmitry Baryshkov wrote:
> Add a simple driver that handles scaling of L2 frequency and voltages.
> 
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
>  drivers/soc/qcom/Kconfig          |   9 ++
>  drivers/soc/qcom/Makefile         |   1 +
>  drivers/soc/qcom/krait-l2-cache.c | 190 ++++++++++++++++++++++++++++++
>  3 files changed, 200 insertions(+)
>  create mode 100644 drivers/soc/qcom/krait-l2-cache.c
> 
> diff --git a/drivers/soc/qcom/Kconfig b/drivers/soc/qcom/Kconfig
> index e597799e8121..01090b7a3c06 100644
> --- a/drivers/soc/qcom/Kconfig
> +++ b/drivers/soc/qcom/Kconfig
> @@ -70,6 +70,15 @@ config QCOM_LLCC
>  	  SDM845. This provides interfaces to clients that use the LLCC.
>  	  Say yes here to enable LLCC slice driver.
>  
> +config QCOM_KRAIT_L2_CACHE
> +	tristate "Qualcomm Krait L2 cache scaling"
> +	depends on ARCH_QCOM && ARM || COMPILE_TEST
> +	select INTERCONNECT
> +	select INTERCONNECT_CLK
> +	default ARM_QCOM_CPUFREQ_NVMEM
> +	help
> +	  The driver for scaling the L2 cache frequency on Qualcomm Krait platforms.
> +
>  config QCOM_KRYO_L2_ACCESSORS
>  	bool
>  	depends on (ARCH_QCOM || COMPILE_TEST) && ARM64
> diff --git a/drivers/soc/qcom/Makefile b/drivers/soc/qcom/Makefile
> index 99114c71092b..cdd1cc96e9f9 100644
> --- a/drivers/soc/qcom/Makefile
> +++ b/drivers/soc/qcom/Makefile
> @@ -31,6 +31,7 @@ obj-$(CONFIG_QCOM_APR) += apr.o
>  obj-$(CONFIG_QCOM_LLCC) += llcc-qcom.o
>  obj-$(CONFIG_QCOM_RPMHPD) += rpmhpd.o
>  obj-$(CONFIG_QCOM_RPMPD) += rpmpd.o
> +obj-$(CONFIG_QCOM_KRAIT_L2_CACHE) += krait-l2-cache.o
>  obj-$(CONFIG_QCOM_KRYO_L2_ACCESSORS) +=	kryo-l2-accessors.o
>  obj-$(CONFIG_QCOM_ICC_BWMON)	+= icc-bwmon.o
>  qcom_ice-objs			+= ice.o
> diff --git a/drivers/soc/qcom/krait-l2-cache.c b/drivers/soc/qcom/krait-l2-cache.c
> new file mode 100644
> index 000000000000..af9e7b955daf
> --- /dev/null
> +++ b/drivers/soc/qcom/krait-l2-cache.c
> @@ -0,0 +1,190 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (c) 2023, Linaro Ltd.
> + */
> +
> +#include <linux/clk.h>
> +#include <linux/interconnect-clk.h>
> +#include <linux/interconnect-provider.h>
> +#include <linux/of_device.h>
> +#include <linux/platform_device.h>
> +#include <linux/pm_opp.h>
> +#include <linux/regulator/consumer.h>
> +
> +#include <dt-bindings/soc/qcom,krait-l2-cache.h>
> +
> +/* Random ID that doesn't clash with main qnoc and OSM */
> +#define L2_MASTER_NODE 2000
> +
> +/* vdd-mem and vdd-dig */
> +#define NUM_SUPPLIES 2
I *think* the code would be much, much simpler if you made the
debug print, regulator set and error message a separate function
and then called them explicitly, without a for-loop.

> +static int krait_l2_config_regulators(struct device *dev,
> +				      struct dev_pm_opp *old_opp,
> +				      struct dev_pm_opp *new_opp,
> +				      struct regulator **regulators,
> +				      unsigned int count)
> +{
> +	struct dev_pm_opp_supply supplies[NUM_SUPPLIES];
> +	unsigned long old_freq, freq;
> +	unsigned int i;
> +	int ret;
> +
> +	if (WARN_ON_ONCE(count != NUM_SUPPLIES))
> +		return -EINVAL;
> +
> +	ret = dev_pm_opp_get_supplies(new_opp, supplies);
> +	if (WARN_ON(ret))
> +		return ret;
> +
> +	old_freq = dev_pm_opp_get_freq(old_opp);
> +	freq = dev_pm_opp_get_freq(new_opp);
> +
> +	WARN_ON(!old_freq || !freq);
> +	if (freq > old_freq) {
> +		for (i = 0; i < count; i++) {
> +			struct regulator *reg = regulators[i];
> +			struct dev_pm_opp_supply *supply = &supplies[i];
> +
> +			dev_dbg(dev, "%s: voltages (mV): %lu %lu %lu\n", __func__,
> +				supply->u_volt_min, supply->u_volt, supply->u_volt_max);
> +
> +			ret = regulator_set_voltage_triplet(reg,
> +							    supply->u_volt_min,
> +							    supply->u_volt,
> +							    supply->u_volt_max);
> +			if (ret) {
> +				dev_err(dev, "%s: failed to set voltage (%lu %lu %lu mV): %d\n",
> +					__func__, supply->u_volt_min, supply->u_volt,
> +					supply->u_volt_max, ret);
> +				goto restore_backwards;
> +			}
> +		}
> +	} else {
> +		for (i = count; i > 0; i--) {
> +			struct regulator *reg = regulators[i - 1];
> +			struct dev_pm_opp_supply *supply = &supplies[i - 1];
> +
> +			dev_dbg(dev, "%s: voltages (mV): %lu %lu %lu\n", __func__,
> +				supply->u_volt_min, supply->u_volt, supply->u_volt_max);
> +
> +			ret = regulator_set_voltage_triplet(reg,
> +							    supply->u_volt_min,
> +							    supply->u_volt,
> +							    supply->u_volt_max);
> +			if (ret) {
> +				dev_err(dev, "%s: failed to set voltage (%lu %lu %lu mV): %d\n",
> +					__func__, supply->u_volt_min, supply->u_volt,
> +					supply->u_volt_max, ret);
> +				goto restore_forward;
> +			}
> +		}
> +	}
> +
> +	return 0;
> +
> +restore_backwards:
> +
> +	dev_pm_opp_get_supplies(old_opp, supplies);
> +
> +	for (; i > 0; i--) {
> +		struct regulator *reg = regulators[i - 1];
> +		struct dev_pm_opp_supply *supply = &supplies[i - 1];
> +
> +		dev_dbg(dev, "%s: voltages (mV): %lu %lu %lu\n", __func__,
> +			supply->u_volt_min, supply->u_volt, supply->u_volt_max);
> +
> +		regulator_set_voltage_triplet(reg,
> +					      supply->u_volt_min,
> +					      supply->u_volt,
> +					      supply->u_volt_max);
> +	}
> +
> +	return ret;
> +
> +restore_forward:
> +
> +	dev_pm_opp_get_supplies(old_opp, supplies);
> +
> +	for ( ; i < count; i++) {
> +		struct regulator *reg = regulators[i];
> +		struct dev_pm_opp_supply *supply = &supplies[i];
> +
> +		dev_dbg(dev, "%s: voltages (mV): %lu %lu %lu\n", __func__,
> +			supply->u_volt_min, supply->u_volt, supply->u_volt_max);
> +
> +		regulator_set_voltage_triplet(reg,
> +					      supply->u_volt_min,
> +					      supply->u_volt,
> +					      supply->u_volt_max);
> +	}
> +
> +	return ret;
> +}
> +
> +static int krait_l2_probe(struct platform_device *pdev)
> +{
> +	struct dev_pm_opp_config krait_l2_cfg = {
> +		.clk_names = (const char * const[]) { NULL, NULL },
> +		.config_regulators = krait_l2_config_regulators,
> +		.regulator_names = (const char * const[]) { "vdd-mem", "vdd-dig", NULL },
> +	};
> +	struct icc_clk_data data[] = {
> +		{ .name = "l2", .opp = true},
true} -> true }

Konrad
> +	};
> +
> +	struct device *dev = &pdev->dev;
> +	struct icc_provider *provider;
> +	struct clk *clk;
> +	int ret;
> +
> +	clk = devm_clk_get(dev, NULL);
> +	if (IS_ERR(clk))
> +		return PTR_ERR(clk);
> +
> +	ret = devm_pm_opp_set_config(dev, &krait_l2_cfg);
> +	if (ret)
> +		return ret;
> +
> +	ret = devm_pm_opp_of_add_table(dev);
> +	if (ret)
> +		return ret;
> +
> +	data[0].clk = clk;
> +	provider = icc_clk_register(dev, L2_MASTER_NODE, ARRAY_SIZE(data), data);
> +	if (IS_ERR(provider))
> +		return PTR_ERR(provider);
> +
> +	platform_set_drvdata(pdev, provider);
> +
> +	return 0;
> +}
> +
> +static int krait_l2_remove(struct platform_device *pdev)
> +{
> +	struct icc_provider *provider = platform_get_drvdata(pdev);
> +
> +	icc_clk_unregister(provider);
> +
> +	return 0;
> +}
> +
> +static const struct of_device_id krait_l2_match_table[] = {
> +	{ .compatible = "qcom,krait-l2-cache" },
> +	{}
> +};
> +MODULE_DEVICE_TABLE(of, krait_l2_match_table);
> +
> +static struct platform_driver krait_l2_driver = {
> +	.probe = krait_l2_probe,
> +	.remove = krait_l2_remove,
> +	.driver = {
> +		.name = "qcom-krait-l2",
> +		.of_match_table = krait_l2_match_table,
> +		.sync_state = icc_sync_state,
> +	},
> +};
> +
> +module_platform_driver(krait_l2_driver);
> +
> +MODULE_DESCRIPTION("Qualcomm Krait L2 scaling driver");
> +MODULE_LICENSE("GPL v2");

Re: [PATCH v2 09/26] cpufreq: qcom-nvmem: create L2 cache device

[Dmitry Baryshkov]

On 26/06/2023 14:50, Konrad Dybcio wrote:
> On 25.06.2023 22:25, Dmitry Baryshkov wrote:
>> Scaling the frequencies on some of Qualcomm Krait platforms (e.g.
>> APQ8064) also requires scaling of the L2 cache frequency. As the
>> l2-cache device node is places under /cpus/ path, it is not created by
>> default by the OF code. Create corresponding device here.
>>
>> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
>> ---
> I think a generic solution (i.e. for each cpu node call
> of_platform_populate in drivers/of/platform.c :
> of_platform_default_populate_init) could be beneficial

After giving it a lot of thought, I'm not brave enough to register all 
CPU-like devices (especially since some of them are registered by other 
means). So let's keep it this way, unless we see a bigger demand of 
populating cache devices.

-- 
With best wishes
Dmitry