From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6DF5BEB64DA for ; Mon, 26 Jun 2023 15:34:15 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231139AbjFZPeO (ORCPT ); Mon, 26 Jun 2023 11:34:14 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50866 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230047AbjFZPeI (ORCPT ); Mon, 26 Jun 2023 11:34:08 -0400 Received: from mail-lj1-x233.google.com (mail-lj1-x233.google.com [IPv6:2a00:1450:4864:20::233]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DE0B410CA for ; Mon, 26 Jun 2023 08:34:06 -0700 (PDT) Received: by mail-lj1-x233.google.com with SMTP id 38308e7fff4ca-2b698371937so28600191fa.3 for ; Mon, 26 Jun 2023 08:34:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1687793645; x=1690385645; h=in-reply-to:content-disposition:mime-version:references:message-id :subject:cc:to:from:date:from:to:cc:subject:date:message-id:reply-to; bh=TOcE0YUWkUmrq+/gOrSOJce+pS6FVzX4REjlVMYSaG4=; b=M130AEjsr8m4ZygKaFa7Kq8JtikEYaSZoJ6OyZg0p4wCF7Kiww9ZtERLNS4uL6SSiE TtEgtEOQpwvMW0Z+UbMPP0Uf3GbBy7BLasS9qGJ0m+kQlPWsg7b7A7XzNJxg1vvCGdw2 Z3InxowJ53ImdnxUDsrHzj6D4JXPUEuux9i6pgAP0QR+7I7JWmTXJqPoJV+HamwX+o4W EGRRmx/DjDR7UQohfJWxybydg7UPxWsj/PzQMJUTT0jW1lTXGntWXwex6LkYxPBx6k5E /tF0Ni7eZ/i6Mf/INswt/oyvWs4lcI+zPyxmgucsmFBeUsQE7M8vNEqhNZt28i5I3uKr hCnA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1687793645; x=1690385645; h=in-reply-to:content-disposition:mime-version:references:message-id :subject:cc:to:from:date:x-gm-message-state:from:to:cc:subject:date :message-id:reply-to; bh=TOcE0YUWkUmrq+/gOrSOJce+pS6FVzX4REjlVMYSaG4=; b=Px1AsbIvmmpXktstJM8CkfzEgeWDsmr05amcmn4OrkKxewLCySRxXBuFvut1i2dMF+ TyO/HUMA2gEdZZ/BK4xqhCoearMCFP69jXU1pX0rFM2VPJpF6Hr10F4perMe712/dhM4 iMyY1HBgtT9xYczkQEZdlQ2wcK0XjR1/HstbmGybcOxS+JYoIQnVfGc1dzVE5CP2Ti17 686+tgdAZpYXbTZpdNXhDlh5mzm1tq38OfNOh5128/vTmAXzjAQTl4pZIgDZBiNPp62k o+8DuYmhXzwX7j3Udr0oP0RQQORC4Wyi4sUKgqlhU3kNQF/X23KC6kRFbi/8k/eY1bSM BXnA== X-Gm-Message-State: AC+VfDzapFLX/3oj9b8lpPeLEJdxule9B1w/sFikZoE6IFErBZtSUH9K S/yyyLOP/kEtRNzJ6exisHpW2Q== X-Google-Smtp-Source: ACHHUZ5e9WFlfbtA2OGlPIGauJXFT0rXT3O/YtYVBHy4uTdeZSa4mLoM4vGGOAZsSHpw1/K1jlUbNA== X-Received: by 2002:a2e:3202:0:b0:2b5:9d78:213e with SMTP id y2-20020a2e3202000000b002b59d78213emr5596880ljy.22.1687793645097; Mon, 26 Jun 2023 08:34:05 -0700 (PDT) Received: from localhost (2001-1ae9-1c2-4c00-20f-c6b4-1e57-7965.ip6.tmcz.cz. [2001:1ae9:1c2:4c00:20f:c6b4:1e57:7965]) by smtp.gmail.com with ESMTPSA id hk8-20020a170906c9c800b00987316d1585sm3421374ejb.145.2023.06.26.08.34.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 26 Jun 2023 08:34:04 -0700 (PDT) Date: Mon, 26 Jun 2023 17:34:03 +0200 From: Andrew Jones To: Conor Dooley Cc: palmer@dabbelt.com, conor@kernel.org, Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Albert Ou , Heiko Stuebner , Evan Green , Sunil V L , linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v1 5/9] RISC-V: add missing single letter extension definitions Message-ID: <20230626-2943390be412d044fff507e0@orel> References: <20230626-provable-angrily-81760e8c3cc6@wendy> <20230626-possible-poet-ae4afce0a525@wendy> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20230626-possible-poet-ae4afce0a525@wendy> Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On Mon, Jun 26, 2023 at 12:19:43PM +0100, Conor Dooley wrote: > To facilitate adding single letter extensions to riscv_isa_ext, add > definitions for the extensions present in base_riscv_exts that do not > already have them. > > Signed-off-by: Conor Dooley > --- > arch/riscv/include/asm/hwcap.h | 5 +++++ > 1 file changed, 5 insertions(+) > > diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h > index 36f46dfd2b87..a35bee219dd7 100644 > --- a/arch/riscv/include/asm/hwcap.h > +++ b/arch/riscv/include/asm/hwcap.h > @@ -14,12 +14,17 @@ > #include > > #define RISCV_ISA_EXT_a ('a' - 'a') > +#define RISCV_ISA_EXT_b ('b' - 'a') > #define RISCV_ISA_EXT_c ('c' - 'a') > #define RISCV_ISA_EXT_d ('d' - 'a') > #define RISCV_ISA_EXT_f ('f' - 'a') > #define RISCV_ISA_EXT_h ('h' - 'a') > #define RISCV_ISA_EXT_i ('i' - 'a') > +#define RISCV_ISA_EXT_j ('j' - 'a') > +#define RISCV_ISA_EXT_k ('k' - 'a') > #define RISCV_ISA_EXT_m ('m' - 'a') > +#define RISCV_ISA_EXT_p ('p' - 'a') > +#define RISCV_ISA_EXT_q ('q' - 'a') > #define RISCV_ISA_EXT_s ('s' - 'a') > #define RISCV_ISA_EXT_u ('u' - 'a') > #define RISCV_ISA_EXT_v ('v' - 'a') > -- > 2.40.1 > Reviewed-by: Andrew Jones