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* [PATCH v1 0/9] RISC-V: Probe DT extension support using riscv,isa-extensions & riscv,isa-base
@ 2023-06-26 11:19 Conor Dooley
  2023-06-26 11:19 ` [PATCH v1 1/9] RISC-V: don't parse dt/acpi isa string to get rv32/rv64 Conor Dooley
                   ` (8 more replies)
  0 siblings, 9 replies; 33+ messages in thread
From: Conor Dooley @ 2023-06-26 11:19 UTC (permalink / raw)
  To: palmer
  Cc: conor, conor.dooley, Rob Herring, Krzysztof Kozlowski,
	Paul Walmsley, Albert Ou, Andrew Jones, Heiko Stuebner,
	Evan Green, Sunil V L, linux-riscv, devicetree, linux-kernel

Hey,

Based on my latest iteration of deprecating riscv,isa [1], here's an
implementation of the new properties for Linux. The first few patches,
up to "RISC-V: split riscv_fill_hwcap() in 3", are all prep work that
further tames some of the extension related code, on top of my already
applied series that cleans up the ISA string parser.
Perhaps "RISC-V: shunt isa_ext_arr to cpufeature.c" is a bit gratuitous,
but I figured a bit of coalescing of extension related data structures
would be a good idea. I certainly would not be against putting this
stuff in hwcap.h instead.

Note that riscv,isa will still be used in the absence of the new
properties:
	if (!acpi_disabled) {
		riscv_fill_hwcap_from_isa_string(isa2hwcap);
	} else {
		int ret = riscv_fill_hwcap_new(isa2hwcap);
		if (ret) {
			pr_info("Falling back to deprecated \"riscv,isa\"\n");
			riscv_fill_hwcap_from_isa_string(isa2hwcap);
		}
	}

Also, I could not come up with a good name for the new function,
suggestions welcome on that front for sure.

Cheers,
Conor.

As a side note, I tried some macro fiddling to remove the need for a
\#define for each extension that ends up conflicting a bunch between
different people, but didn't come up with anything I was happy with that
worked. I'll keep tinkering with that.

[1] https://lore.kernel.org/all/20230626-unmarked-atom-70b4d624a386@wendy/

CC: Rob Herring <robh+dt@kernel.org>
CC: Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>
CC: Paul Walmsley <paul.walmsley@sifive.com>
CC: Palmer Dabbelt <palmer@dabbelt.com>
CC: Albert Ou <aou@eecs.berkeley.edu>
CC: Andrew Jones <ajones@ventanamicro.com>
CC: Heiko Stuebner <heiko.stuebner@vrull.eu>
CC: Evan Green <evan@rivosinc.com>
CC: Sunil V L <sunilvl@ventanamicro.com>
CC: linux-riscv@lists.infradead.org
CC: devicetree@vger.kernel.org
CC: linux-kernel@vger.kernel.org

Conor Dooley (8):
  RISC-V: drop a needless check in print_isa_ext()
  RISC-V: shunt isa_ext_arr to cpufeature.c
  RISC-V: repurpose riscv_isa_ext array in riscv_fill_hwcap()
  RISC-V: add missing single letter extension definitions
  RISC-V: add single letter extensions to riscv_isa_ext
  RISC-V: split riscv_fill_hwcap() in 3
  RISC-V: enable extension detection from new properties
  RISC-V: try new extension properties in of_early_processor_hartid()

Heiko Stuebner (1):
  RISC-V: don't parse dt/acpi isa string to get rv32/rv64

 arch/riscv/include/asm/hwcap.h |  16 +-
 arch/riscv/kernel/cpu.c        | 149 +++-------
 arch/riscv/kernel/cpufeature.c | 508 +++++++++++++++++++++------------
 3 files changed, 379 insertions(+), 294 deletions(-)

-- 
2.40.1


^ permalink raw reply	[flat|nested] 33+ messages in thread
end of thread, other threads:[~2023-06-28 17:51 UTC | newest]

Thread overview: 33+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2023-06-26 11:19 [PATCH v1 0/9] RISC-V: Probe DT extension support using riscv,isa-extensions & riscv,isa-base Conor Dooley
2023-06-26 11:19 ` [PATCH v1 1/9] RISC-V: don't parse dt/acpi isa string to get rv32/rv64 Conor Dooley
2023-06-26 15:14   ` Andrew Jones
2023-06-26 15:51     ` Conor Dooley
2023-06-26 16:05       ` Andrew Jones
2023-06-26 16:16         ` Conor Dooley
2023-06-27  8:02           ` Sunil V L
2023-06-27  8:51             ` Conor Dooley
2023-06-27  9:20               ` Sunil V L
2023-06-26 11:19 ` [PATCH v1 2/9] RISC-V: drop a needless check in print_isa_ext() Conor Dooley
2023-06-26 15:19   ` Andrew Jones
2023-06-26 16:08     ` Conor Dooley
2023-06-26 16:29       ` Andrew Jones
2023-06-26 11:19 ` [PATCH v1 3/9] RISC-V: shunt isa_ext_arr to cpufeature.c Conor Dooley
2023-06-26 15:29   ` Andrew Jones
2023-06-26 15:44     ` Andrew Jones
2023-06-26 15:59       ` Conor Dooley
2023-06-26 11:19 ` [PATCH v1 4/9] RISC-V: repurpose riscv_isa_ext array in riscv_fill_hwcap() Conor Dooley
2023-06-26 15:33   ` Andrew Jones
2023-06-26 11:19 ` [PATCH v1 5/9] RISC-V: add missing single letter extension definitions Conor Dooley
2023-06-26 15:34   ` Andrew Jones
2023-06-26 11:19 ` [PATCH v1 6/9] RISC-V: add single letter extensions to riscv_isa_ext Conor Dooley
2023-06-26 15:42   ` Andrew Jones
2023-06-28 17:33   ` Evan Green
2023-06-28 17:43     ` Conor Dooley
2023-06-28 17:50       ` Evan Green
2023-06-26 11:19 ` [PATCH v1 7/9] RISC-V: split riscv_fill_hwcap() in 3 Conor Dooley
2023-06-26 16:17   ` Andrew Jones
2023-06-27 17:42     ` Conor Dooley
2023-06-26 11:19 ` [PATCH v1 8/9] RISC-V: enable extension detection from new properties Conor Dooley
2023-06-26 16:24   ` Andrew Jones
2023-06-26 11:19 ` [PATCH v1 9/9] RISC-V: try new extension properties in of_early_processor_hartid() Conor Dooley
2023-06-26 16:25   ` Andrew Jones

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