From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 84239EB64DA for ; Mon, 26 Jun 2023 11:21:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230368AbjFZLVM (ORCPT ); Mon, 26 Jun 2023 07:21:12 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56740 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230290AbjFZLVJ (ORCPT ); Mon, 26 Jun 2023 07:21:09 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 98795E7A; Mon, 26 Jun 2023 04:20:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1687778459; x=1719314459; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=7P2ZuLVh/mHZ6Q4BNnYCrGzK8DdnxNYlyk5flnLKkc8=; b=cHILVaRVQrQNiHDtUFoF03bPU/H0ALPdH5ddPJeHTTAINhey0zBrvHPW jndP+ArScGVRvef+FSgBu5UV7rrhiJPv+94TlJPu3UmGJZPKgwfCQ8jsZ n61JFO8BOxEuxr2OAPE96dWdOkMZI27X24VzjE1q/37zkKy7c6p5IkhmI xVO0nLJ+c2cVPko7yfazIPhMOzf0PHFsXyXGVTfTzr7NxB5wOeFrnooE0 fyeL3crlOc3H6ULV7rNqZH6rBZ27KQuT35NGotXDUTHPfHXjoV8ZLAlYH kUuTfD/8jkdvL+uDF8wbRwCpFftqOEqQzHufy9r0sJRtAFcb6XtKmyLeb g==; X-IronPort-AV: E=Sophos;i="6.01,159,1684825200"; d="scan'208";a="232170783" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa1.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 26 Jun 2023 04:20:59 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.21; Mon, 26 Jun 2023 04:20:58 -0700 Received: from wendy.microchip.com (10.10.115.15) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.21 via Frontend Transport; Mon, 26 Jun 2023 04:20:56 -0700 From: Conor Dooley To: CC: , , Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Albert Ou , Andrew Jones , Heiko Stuebner , "Evan Green" , Sunil V L , , , Subject: [PATCH v1 5/9] RISC-V: add missing single letter extension definitions Date: Mon, 26 Jun 2023 12:19:43 +0100 Message-ID: <20230626-possible-poet-ae4afce0a525@wendy> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230626-provable-angrily-81760e8c3cc6@wendy> References: <20230626-provable-angrily-81760e8c3cc6@wendy> MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=1151; i=conor.dooley@microchip.com; h=from:subject:message-id; bh=7P2ZuLVh/mHZ6Q4BNnYCrGzK8DdnxNYlyk5flnLKkc8=; b=owGbwMvMwCFWscWwfUFT0iXG02pJDCkzS/xE6xX23F074e9rMbcVQp8tu+YXyBy/sSt3+qSI3okt tbITOkpZGMQ4GGTFFFkSb/e1SK3/47LDuectzBxWJpAhDFycAjAR//MM/yNNa9dwJvmkacy1rj2x/n MTq7zVA7vpn1OurJVwNg59fIORYWPFuu+zBZZ/uTYx+h7/2avbjWesEnSN/tA/+ZyoyxqzcywA X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C Content-Transfer-Encoding: 8bit Content-Type: text/plain Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org To facilitate adding single letter extensions to riscv_isa_ext, add definitions for the extensions present in base_riscv_exts that do not already have them. Signed-off-by: Conor Dooley --- arch/riscv/include/asm/hwcap.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h index 36f46dfd2b87..a35bee219dd7 100644 --- a/arch/riscv/include/asm/hwcap.h +++ b/arch/riscv/include/asm/hwcap.h @@ -14,12 +14,17 @@ #include #define RISCV_ISA_EXT_a ('a' - 'a') +#define RISCV_ISA_EXT_b ('b' - 'a') #define RISCV_ISA_EXT_c ('c' - 'a') #define RISCV_ISA_EXT_d ('d' - 'a') #define RISCV_ISA_EXT_f ('f' - 'a') #define RISCV_ISA_EXT_h ('h' - 'a') #define RISCV_ISA_EXT_i ('i' - 'a') +#define RISCV_ISA_EXT_j ('j' - 'a') +#define RISCV_ISA_EXT_k ('k' - 'a') #define RISCV_ISA_EXT_m ('m' - 'a') +#define RISCV_ISA_EXT_p ('p' - 'a') +#define RISCV_ISA_EXT_q ('q' - 'a') #define RISCV_ISA_EXT_s ('s' - 'a') #define RISCV_ISA_EXT_u ('u' - 'a') #define RISCV_ISA_EXT_v ('v' - 'a') -- 2.40.1