[PATCH v3 0/2] mtd: spi-nor: Avoid setting SRWD bit in SR

[PATCH v3 0/2] mtd: spi-nor: Avoid setting SRWD bit in SR

[Amit Kumar Mahapatra]

Setting the status register write disable (SRWD) bit in the status
register (SR) with WP# signal of the flash not connected or wrongly tied to
GND (that includes internal pull-downs), will configure the SR permanently 
as read-only. To avoid this a boolean type DT property "no-wp" is 
introduced. If this property is defined, the spi-nor doesn't set the SRWD 
bit in SR while performing flash protection operation.
---
BRANCH: for-next

Changes in v3:
- Updated DT property name to "no-wp".
- Removed Reviewed-by tag from 1/2 as the DT property name has changed.
- Updated spi-nor flag name to SNOR_F_NO_WP.
- Updated DT property description.
- Updated patch description.
- Updated comments in swp.c file.
- Replaced WP with WP# in patch descriptions, comments & DT property 
  description.

Changes in v2:
- Modified DT property description to add information about a
  valid use case.
- Added Reviewed-by tag in 1/2.
- Updated comment description in 2/2.
---
Amit Kumar Mahapatra (2):
  dt-bindings: mtd: jedec, spi-nor: Add DT property to avoid setting
    SRWD bit in status register
  mtd: spi-nor: Avoid setting SRWD bit in SR if WP# signal not connected

 .../devicetree/bindings/mtd/jedec,spi-nor.yaml    | 15 +++++++++++++++
 drivers/mtd/spi-nor/core.c                        |  3 +++
 drivers/mtd/spi-nor/core.h                        |  1 +
 drivers/mtd/spi-nor/swp.c                         |  9 +++++++--
 4 files changed, 26 insertions(+), 2 deletions(-)

-- 
2.17.1

[PATCH v3 1/2] dt-bindings: mtd: jedec, spi-nor: Add DT property to avoid setting SRWD bit in status register

[Amit Kumar Mahapatra]

If the WP# signal of the flash device is either not connected or is wrongly
tied to GND (that includes internal pull-downs), and the software sets the
status register write disable (SRWD) bit in the status register then the
status register permanently becomes read-only. To avoid this added a new
boolean DT property "no-wp". If this property is set in the DT then the
software avoids setting the SRWD during status register write operation.

Signed-off-by: Amit Kumar Mahapatra <amit.kumar-mahapatra@amd.com>
---
As the DT property name has changed so, removed Reviewed-by tag.
@Cornor if possible, could you please review this updated patch.
---
 .../devicetree/bindings/mtd/jedec,spi-nor.yaml    | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

diff --git a/Documentation/devicetree/bindings/mtd/jedec,spi-nor.yaml b/Documentation/devicetree/bindings/mtd/jedec,spi-nor.yaml
index 89959e5c47ba..97344969b02d 100644
--- a/Documentation/devicetree/bindings/mtd/jedec,spi-nor.yaml
+++ b/Documentation/devicetree/bindings/mtd/jedec,spi-nor.yaml
@@ -70,6 +70,21 @@ properties:
       be used on such systems, to denote the absence of a reliable reset
       mechanism.
 
+  no-wp:
+    type: boolean
+    description:
+      The status register write disable (SRWD) bit in status register, combined
+      with the WP# signal, provides hardware data protection for the device. When
+      the SRWD bit is set to 1, and the WP# signal is either driven LOW or hard
+      strapped to LOW, the status register nonvolatile bits become read-only and
+      the WRITE STATUS REGISTER operation will not execute. The only way to exit
+      this hardware-protected mode is to drive WP# HIGH. If the WP# signal of the
+      flash device is not connected or is wrongly tied to GND (that includes internal
+      pull-downs) then status register permanently becomes read-only as the SRWD bit
+      cannot be reset. This boolean flag can be used on such systems to avoid setting
+      the SRWD bit while writing the status register. WP# signal hard strapped to GND
+      can be a valid use case.
+
   reset-gpios:
     description:
       A GPIO line connected to the RESET (active low) signal of the device.
-- 
2.17.1

[PATCH v3 2/2] mtd: spi-nor: Avoid setting SRWD bit in SR if WP# signal not connected

[Amit Kumar Mahapatra]

Setting the status register write disable (SRWD) bit in the status
register (SR) with WP# signal of the flash left floating or wrongly tied to
GND (that includes internal pull-downs), will configure the SR permanently
as read-only. If WP# signal is left floating or wrongly tied to GND, avoid
setting SRWD bit while writing the SR during flash protection.

Signed-off-by: Amit Kumar Mahapatra <amit.kumar-mahapatra@amd.com>
---
 drivers/mtd/spi-nor/core.c | 3 +++
 drivers/mtd/spi-nor/core.h | 1 +
 drivers/mtd/spi-nor/swp.c  | 9 +++++++--
 3 files changed, 11 insertions(+), 2 deletions(-)

diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c
index 0bb0ad14a2fc..520f5ab86d2b 100644
--- a/drivers/mtd/spi-nor/core.c
+++ b/drivers/mtd/spi-nor/core.c
@@ -2864,6 +2864,9 @@ static void spi_nor_init_flags(struct spi_nor *nor)
 	if (flags & NO_CHIP_ERASE)
 		nor->flags |= SNOR_F_NO_OP_CHIP_ERASE;
 
+	if (of_property_read_bool(np, "no-wp"))
+		nor->flags |= SNOR_F_NO_WP;
+
 	if (flags & SPI_NOR_RWW && nor->info->n_banks > 1 &&
 	    !nor->controller_ops)
 		nor->flags |= SNOR_F_RWW;
diff --git a/drivers/mtd/spi-nor/core.h b/drivers/mtd/spi-nor/core.h
index 4fb5ff09c63a..55b5e7abce6e 100644
--- a/drivers/mtd/spi-nor/core.h
+++ b/drivers/mtd/spi-nor/core.h
@@ -132,6 +132,7 @@ enum spi_nor_option_flags {
 	SNOR_F_SWP_IS_VOLATILE	= BIT(13),
 	SNOR_F_RWW		= BIT(14),
 	SNOR_F_ECC		= BIT(15),
+	SNOR_F_NO_WP		= BIT(16),
 };
 
 struct spi_nor_read_command {
diff --git a/drivers/mtd/spi-nor/swp.c b/drivers/mtd/spi-nor/swp.c
index 0ba716e84377..cfaba41d74d6 100644
--- a/drivers/mtd/spi-nor/swp.c
+++ b/drivers/mtd/spi-nor/swp.c
@@ -214,8 +214,13 @@ static int spi_nor_sr_lock(struct spi_nor *nor, loff_t ofs, uint64_t len)
 
 	status_new = (status_old & ~mask & ~tb_mask) | val;
 
-	/* Disallow further writes if WP pin is asserted */
-	status_new |= SR_SRWD;
+	/*
+	 * Disallow further writes if WP# pin is neither left floating nor
+	 * wrongly tied to GND(that includes internal pull-downs).
+	 * WP# pin hard strapped to GND can be a valid use case.
+	 */
+	if (!(nor->flags & SNOR_F_NO_WP))
+		status_new |= SR_SRWD;
 
 	if (!use_top)
 		status_new |= tb_mask;
-- 
2.17.1

Re: [PATCH v3 1/2] dt-bindings: mtd: jedec, spi-nor: Add DT property to avoid setting SRWD bit in status register

[Conor Dooley]

[-- Attachment #1: Type: text/plain, Size: 2672 bytes --]

On Sun, Jun 25, 2023 at 03:32:50PM +0530, Amit Kumar Mahapatra wrote:
> If the WP# signal of the flash device is either not connected or is wrongly
> tied to GND (that includes internal pull-downs), and the software sets the
> status register write disable (SRWD) bit in the status register then the
> status register permanently becomes read-only. To avoid this added a new
> boolean DT property "no-wp". If this property is set in the DT then the
> software avoids setting the SRWD during status register write operation.
> 
> Signed-off-by: Amit Kumar Mahapatra <amit.kumar-mahapatra@amd.com>
> ---
> As the DT property name has changed so, removed Reviewed-by tag.
> @Cornor if possible, could you please review this updated patch.

Rob was the one who objected to the property name.
Old & new names are fine by me, it was the text I think I cared about.
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>

Thanks for actually explaining why you dropped the tag,
Conor.

> ---
>  .../devicetree/bindings/mtd/jedec,spi-nor.yaml    | 15 +++++++++++++++
>  1 file changed, 15 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/mtd/jedec,spi-nor.yaml b/Documentation/devicetree/bindings/mtd/jedec,spi-nor.yaml
> index 89959e5c47ba..97344969b02d 100644
> --- a/Documentation/devicetree/bindings/mtd/jedec,spi-nor.yaml
> +++ b/Documentation/devicetree/bindings/mtd/jedec,spi-nor.yaml
> @@ -70,6 +70,21 @@ properties:
>        be used on such systems, to denote the absence of a reliable reset
>        mechanism.
>  
> +  no-wp:
> +    type: boolean
> +    description:
> +      The status register write disable (SRWD) bit in status register, combined
> +      with the WP# signal, provides hardware data protection for the device. When
> +      the SRWD bit is set to 1, and the WP# signal is either driven LOW or hard
> +      strapped to LOW, the status register nonvolatile bits become read-only and
> +      the WRITE STATUS REGISTER operation will not execute. The only way to exit
> +      this hardware-protected mode is to drive WP# HIGH. If the WP# signal of the
> +      flash device is not connected or is wrongly tied to GND (that includes internal
> +      pull-downs) then status register permanently becomes read-only as the SRWD bit
> +      cannot be reset. This boolean flag can be used on such systems to avoid setting
> +      the SRWD bit while writing the status register. WP# signal hard strapped to GND
> +      can be a valid use case.
> +
>    reset-gpios:
>      description:
>        A GPIO line connected to the RESET (active low) signal of the device.
> -- 
> 2.17.1
> 

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Re: [PATCH v3 1/2] dt-bindings: mtd: jedec, spi-nor: Add DT property to avoid setting SRWD bit in status register

[Rob Herring]

On Sun, 25 Jun 2023 15:32:50 +0530, Amit Kumar Mahapatra wrote:
> If the WP# signal of the flash device is either not connected or is wrongly
> tied to GND (that includes internal pull-downs), and the software sets the
> status register write disable (SRWD) bit in the status register then the
> status register permanently becomes read-only. To avoid this added a new
> boolean DT property "no-wp". If this property is set in the DT then the
> software avoids setting the SRWD during status register write operation.
> 
> Signed-off-by: Amit Kumar Mahapatra <amit.kumar-mahapatra@amd.com>
> ---
> As the DT property name has changed so, removed Reviewed-by tag.
> @Cornor if possible, could you please review this updated patch.
> ---
>  .../devicetree/bindings/mtd/jedec,spi-nor.yaml    | 15 +++++++++++++++
>  1 file changed, 15 insertions(+)
> 

Reviewed-by: Rob Herring <robh@kernel.org>

Re: [PATCH v3 1/2] dt-bindings: mtd: jedec, spi-nor: Add DT property to avoid setting SRWD bit in status register

[Michael Walle]

Am 2023-06-25 12:02, schrieb Amit Kumar Mahapatra:
> If the WP# signal of the flash device is either not connected or is 
> wrongly
> tied to GND (that includes internal pull-downs), and the software sets 
> the
> status register write disable (SRWD) bit in the status register then 
> the
> status register permanently becomes read-only. To avoid this added a 
> new
> boolean DT property "no-wp". If this property is set in the DT then the
> software avoids setting the SRWD during status register write 
> operation.
> 
> Signed-off-by: Amit Kumar Mahapatra <amit.kumar-mahapatra@amd.com>
> ---
> As the DT property name has changed so, removed Reviewed-by tag.
> @Cornor if possible, could you please review this updated patch.
> ---
>  .../devicetree/bindings/mtd/jedec,spi-nor.yaml    | 15 +++++++++++++++
>  1 file changed, 15 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/mtd/jedec,spi-nor.yaml 
> b/Documentation/devicetree/bindings/mtd/jedec,spi-nor.yaml
> index 89959e5c47ba..97344969b02d 100644
> --- a/Documentation/devicetree/bindings/mtd/jedec,spi-nor.yaml
> +++ b/Documentation/devicetree/bindings/mtd/jedec,spi-nor.yaml
> @@ -70,6 +70,21 @@ properties:
>        be used on such systems, to denote the absence of a reliable 
> reset
>        mechanism.
> 
> +  no-wp:
> +    type: boolean
> +    description:
> +      The status register write disable (SRWD) bit in status register, 
> combined
> +      with the WP# signal, provides hardware data protection for the 
> device. When
> +      the SRWD bit is set to 1, and the WP# signal is either driven 
> LOW or hard
> +      strapped to LOW, the status register nonvolatile bits become 
> read-only and
> +      the WRITE STATUS REGISTER operation will not execute. The only 
> way to exit
> +      this hardware-protected mode is to drive WP# HIGH. If the WP# 
> signal of the
> +      flash device is not connected or is wrongly tied to GND (that 
> includes internal
> +      pull-downs) then status register permanently becomes read-only 
> as the SRWD bit
> +      cannot be reset. This boolean flag can be used on such systems 
> to avoid setting
> +      the SRWD bit while writing the status register. WP# signal hard 
> strapped to GND
> +      can be a valid use case.
> +

Sounds good! Thank you.

Reviewed-by: Michael Walle <michael@walle.cc>

-michael

Re: [PATCH v3 2/2] mtd: spi-nor: Avoid setting SRWD bit in SR if WP# signal not connected

[Michael Walle]

Am 2023-06-25 12:02, schrieb Amit Kumar Mahapatra:
> Setting the status register write disable (SRWD) bit in the status
> register (SR) with WP# signal of the flash left floating or wrongly 
> tied to
> GND (that includes internal pull-downs), will configure the SR 
> permanently
> as read-only. If WP# signal is left floating or wrongly tied to GND, 
> avoid
> setting SRWD bit while writing the SR during flash protection.
> 
> Signed-off-by: Amit Kumar Mahapatra <amit.kumar-mahapatra@amd.com>
> ---
>  drivers/mtd/spi-nor/core.c | 3 +++
>  drivers/mtd/spi-nor/core.h | 1 +
>  drivers/mtd/spi-nor/swp.c  | 9 +++++++--
>  3 files changed, 11 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c
> index 0bb0ad14a2fc..520f5ab86d2b 100644
> --- a/drivers/mtd/spi-nor/core.c
> +++ b/drivers/mtd/spi-nor/core.c
> @@ -2864,6 +2864,9 @@ static void spi_nor_init_flags(struct spi_nor 
> *nor)
>  	if (flags & NO_CHIP_ERASE)
>  		nor->flags |= SNOR_F_NO_OP_CHIP_ERASE;
> 
> +	if (of_property_read_bool(np, "no-wp"))
> +		nor->flags |= SNOR_F_NO_WP;
> +

Please put it below the of_property_read_bool() which is already
there, just to keep things sorted.

>  	if (flags & SPI_NOR_RWW && nor->info->n_banks > 1 &&
>  	    !nor->controller_ops)
>  		nor->flags |= SNOR_F_RWW;
> diff --git a/drivers/mtd/spi-nor/core.h b/drivers/mtd/spi-nor/core.h
> index 4fb5ff09c63a..55b5e7abce6e 100644
> --- a/drivers/mtd/spi-nor/core.h
> +++ b/drivers/mtd/spi-nor/core.h
> @@ -132,6 +132,7 @@ enum spi_nor_option_flags {
>  	SNOR_F_SWP_IS_VOLATILE	= BIT(13),
>  	SNOR_F_RWW		= BIT(14),
>  	SNOR_F_ECC		= BIT(15),
> +	SNOR_F_NO_WP		= BIT(16),

See the comment right above this enum :/

>  };
> 
>  struct spi_nor_read_command {
> diff --git a/drivers/mtd/spi-nor/swp.c b/drivers/mtd/spi-nor/swp.c
> index 0ba716e84377..cfaba41d74d6 100644
> --- a/drivers/mtd/spi-nor/swp.c
> +++ b/drivers/mtd/spi-nor/swp.c
> @@ -214,8 +214,13 @@ static int spi_nor_sr_lock(struct spi_nor *nor, 
> loff_t ofs, uint64_t len)
> 
>  	status_new = (status_old & ~mask & ~tb_mask) | val;
> 
> -	/* Disallow further writes if WP pin is asserted */
> -	status_new |= SR_SRWD;
> +	/*
> +	 * Disallow further writes if WP# pin is neither left floating nor
> +	 * wrongly tied to GND(that includes internal pull-downs).

nit: space missing

Otherwise looks good.

Thanks,
-michael

> +	 * WP# pin hard strapped to GND can be a valid use case.
> +	 */
> +	if (!(nor->flags & SNOR_F_NO_WP))
> +		status_new |= SR_SRWD;
> 
>  	if (!use_top)
>  		status_new |= tb_mask;

Re: [PATCH v3 2/2] mtd: spi-nor: Avoid setting SRWD bit in SR if WP# signal not connected

[Tudor Ambarus]

On 6/27/23 07:14, Michael Walle wrote:
> Am 2023-06-25 12:02, schrieb Amit Kumar Mahapatra:
>> Setting the status register write disable (SRWD) bit in the status
>> register (SR) with WP# signal of the flash left floating or wrongly tied to
>> GND (that includes internal pull-downs), will configure the SR permanently
>> as read-only. If WP# signal is left floating or wrongly tied to GND, avoid
>> setting SRWD bit while writing the SR during flash protection.
>>
>> Signed-off-by: Amit Kumar Mahapatra <amit.kumar-mahapatra@amd.com>
>> ---
>>  drivers/mtd/spi-nor/core.c | 3 +++
>>  drivers/mtd/spi-nor/core.h | 1 +
>>  drivers/mtd/spi-nor/swp.c  | 9 +++++++--
>>  3 files changed, 11 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c
>> index 0bb0ad14a2fc..520f5ab86d2b 100644
>> --- a/drivers/mtd/spi-nor/core.c
>> +++ b/drivers/mtd/spi-nor/core.c
>> @@ -2864,6 +2864,9 @@ static void spi_nor_init_flags(struct spi_nor *nor)
>>      if (flags & NO_CHIP_ERASE)
>>          nor->flags |= SNOR_F_NO_OP_CHIP_ERASE;
>>
>> +    if (of_property_read_bool(np, "no-wp"))
>> +        nor->flags |= SNOR_F_NO_WP;
>> +
> 
> Please put it below the of_property_read_bool() which is already
> there, just to keep things sorted.
> 
>>      if (flags & SPI_NOR_RWW && nor->info->n_banks > 1 &&
>>          !nor->controller_ops)
>>          nor->flags |= SNOR_F_RWW;
>> diff --git a/drivers/mtd/spi-nor/core.h b/drivers/mtd/spi-nor/core.h
>> index 4fb5ff09c63a..55b5e7abce6e 100644
>> --- a/drivers/mtd/spi-nor/core.h
>> +++ b/drivers/mtd/spi-nor/core.h
>> @@ -132,6 +132,7 @@ enum spi_nor_option_flags {
>>      SNOR_F_SWP_IS_VOLATILE    = BIT(13),
>>      SNOR_F_RWW        = BIT(14),
>>      SNOR_F_ECC        = BIT(15),
>> +    SNOR_F_NO_WP        = BIT(16),
> 
> See the comment right above this enum :/
> 
>>  };
>>
>>  struct spi_nor_read_command {
>> diff --git a/drivers/mtd/spi-nor/swp.c b/drivers/mtd/spi-nor/swp.c
>> index 0ba716e84377..cfaba41d74d6 100644
>> --- a/drivers/mtd/spi-nor/swp.c
>> +++ b/drivers/mtd/spi-nor/swp.c
>> @@ -214,8 +214,13 @@ static int spi_nor_sr_lock(struct spi_nor *nor, loff_t ofs, uint64_t len)
>>
>>      status_new = (status_old & ~mask & ~tb_mask) | val;
>>
>> -    /* Disallow further writes if WP pin is asserted */
>> -    status_new |= SR_SRWD;
>> +    /*
>> +     * Disallow further writes if WP# pin is neither left floating nor
>> +     * wrongly tied to GND(that includes internal pull-downs).
> 
> nit: space missing
> 
> Otherwise looks good.
> 

Thanks, Michael.

Amit, would be good if you can address Michael's comments and
resubmit. If not, I'll amend the patch by myself when applying.

Cheers,
ta

RE: [PATCH v3 2/2] mtd: spi-nor: Avoid setting SRWD bit in SR if WP# signal not connected

[Mahapatra, Amit Kumar]

Hello Tudor,

> -----Original Message-----
> From: Tudor Ambarus <tudor.ambarus@linaro.org>
> Sent: Friday, June 30, 2023 2:18 PM
> To: Michael Walle <michael@walle.cc>; Mahapatra, Amit Kumar
> <amit.kumar-mahapatra@amd.com>
> Cc: pratyush@kernel.org; miquel.raynal@bootlin.com; richard@nod.at;
> vigneshr@ti.com; robh+dt@kernel.org; krzysztof.kozlowski+dt@linaro.org;
> conor+dt@kernel.org; git (AMD-Xilinx) <git@amd.com>; linux-
> mtd@lists.infradead.org; devicetree@vger.kernel.org; linux-
> kernel@vger.kernel.org; amitrkcian2002@gmail.com
> Subject: Re: [PATCH v3 2/2] mtd: spi-nor: Avoid setting SRWD bit in SR if WP#
> signal not connected
> 
> 
> 
> On 6/27/23 07:14, Michael Walle wrote:
> > Am 2023-06-25 12:02, schrieb Amit Kumar Mahapatra:
> >> Setting the status register write disable (SRWD) bit in the status
> >> register (SR) with WP# signal of the flash left floating or wrongly
> >> tied to GND (that includes internal pull-downs), will configure the
> >> SR permanently as read-only. If WP# signal is left floating or
> >> wrongly tied to GND, avoid setting SRWD bit while writing the SR during
> flash protection.
> >>
> >> Signed-off-by: Amit Kumar Mahapatra <amit.kumar-
> mahapatra@amd.com>
> >> ---
> >>  drivers/mtd/spi-nor/core.c | 3 +++
> >>  drivers/mtd/spi-nor/core.h | 1 +
> >>  drivers/mtd/spi-nor/swp.c  | 9 +++++++--
> >>  3 files changed, 11 insertions(+), 2 deletions(-)
> >>
> >> diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c
> >> index 0bb0ad14a2fc..520f5ab86d2b 100644
> >> --- a/drivers/mtd/spi-nor/core.c
> >> +++ b/drivers/mtd/spi-nor/core.c
> >> @@ -2864,6 +2864,9 @@ static void spi_nor_init_flags(struct spi_nor
> >> *nor)
> >>      if (flags & NO_CHIP_ERASE)
> >>          nor->flags |= SNOR_F_NO_OP_CHIP_ERASE;
> >>
> >> +    if (of_property_read_bool(np, "no-wp"))
> >> +        nor->flags |= SNOR_F_NO_WP;
> >> +
> >
> > Please put it below the of_property_read_bool() which is already
> > there, just to keep things sorted.
> >
> >>      if (flags & SPI_NOR_RWW && nor->info->n_banks > 1 &&
> >>          !nor->controller_ops)
> >>          nor->flags |= SNOR_F_RWW;
> >> diff --git a/drivers/mtd/spi-nor/core.h b/drivers/mtd/spi-nor/core.h
> >> index 4fb5ff09c63a..55b5e7abce6e 100644
> >> --- a/drivers/mtd/spi-nor/core.h
> >> +++ b/drivers/mtd/spi-nor/core.h
> >> @@ -132,6 +132,7 @@ enum spi_nor_option_flags {
> >>      SNOR_F_SWP_IS_VOLATILE    = BIT(13),
> >>      SNOR_F_RWW        = BIT(14),
> >>      SNOR_F_ECC        = BIT(15),
> >> +    SNOR_F_NO_WP        = BIT(16),
> >
> > See the comment right above this enum :/
> >
> >>  };
> >>
> >>  struct spi_nor_read_command {
> >> diff --git a/drivers/mtd/spi-nor/swp.c b/drivers/mtd/spi-nor/swp.c
> >> index 0ba716e84377..cfaba41d74d6 100644
> >> --- a/drivers/mtd/spi-nor/swp.c
> >> +++ b/drivers/mtd/spi-nor/swp.c
> >> @@ -214,8 +214,13 @@ static int spi_nor_sr_lock(struct spi_nor *nor,
> >> loff_t ofs, uint64_t len)
> >>
> >>      status_new = (status_old & ~mask & ~tb_mask) | val;
> >>
> >> -    /* Disallow further writes if WP pin is asserted */
> >> -    status_new |= SR_SRWD;
> >> +    /*
> >> +     * Disallow further writes if WP# pin is neither left floating
> >> +nor
> >> +     * wrongly tied to GND(that includes internal pull-downs).
> >
> > nit: space missing
> >
> > Otherwise looks good.
> >
> 
> Thanks, Michael.
> 
> Amit, would be good if you can address Michael's comments and resubmit. If
> not, I'll amend the patch by myself when applying.

I will address Michael's comments and send the next series.

Regards,
Amit
> 
> Cheers,
> ta