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From: Andrew Jones <ajones@ventanamicro.com>
To: Conor Dooley <conor.dooley@microchip.com>
Cc: palmer@dabbelt.com, conor@kernel.org,
	Rob Herring <robh+dt@kernel.org>,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	Albert Ou <aou@eecs.berkeley.edu>,
	Heiko Stuebner <heiko.stuebner@vrull.eu>,
	Evan Green <evan@rivosinc.com>,
	Sunil V L <sunilvl@ventanamicro.com>,
	linux-riscv@lists.infradead.org, devicetree@vger.kernel.org,
	linux-kernel@vger.kernel.org,
	Palmer Dabbelt <palmer@rivosinc.com>
Subject: Re: [PATCH v2 10/10] RISC-V: provide a Kconfig option to disable parsing "riscv,isa"
Date: Thu, 29 Jun 2023 11:31:33 +0200	[thread overview]
Message-ID: <20230629-a80f112e6ed4158080867694@orel> (raw)
In-Reply-To: <20230629-resilient-grievance-d782163b09d6@wendy>

On Thu, Jun 29, 2023 at 09:28:56AM +0100, Conor Dooley wrote:
> As it says on the tin, provide a Kconfig option to disabling parsing the
> "riscv,isa" devicetree property. Hide the option behind NONPORTABLE so
> that only those willing to keep the pieces enable it, and make sure the
> default kernel contains the fallback code.
> 
> Suggested-by: Palmer Dabbelt <palmer@rivosinc.com>
> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
> ---
>  arch/riscv/Kconfig             | 16 ++++++++++++++++
>  arch/riscv/kernel/cpu.c        |  3 +++
>  arch/riscv/kernel/cpufeature.c |  2 +-
>  3 files changed, 20 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
> index 1d39efe2b940..0e1909ac5947 100644
> --- a/arch/riscv/Kconfig
> +++ b/arch/riscv/Kconfig
> @@ -291,6 +291,22 @@ config NONPORTABLE
>  
>  	  If unsure, say N.
>  
> +config NO_RISCV_ISA_FALLBACK
> +	bool "Permit falling back to parsing riscv,isa for extension support"
> +	depends on NONPORTABLE
> +	help
> +	  Parsing the "riscv,isa" devicetree property has been deprecated and
> +	  replaced by a list of explicitly defined strings. For compatibility
> +	  with existing platforms, the kernel will fall back to parsing the
> +	  "riscv,isa" property if the replacements are not found.
> +
> +	  Selecting Y here will result in a kernel without this fallback, and
> +	  will not work on platforms where the devicetree does not contain the
> +	  replacement 	  properties of "riscv,isa-base" and
                     ^ spacing issue

> +	  "riscv,isa-extensions". Please see the dt-binding, located at
> +	  Documentation/devicetree/bindings/riscv/extensions.yaml for details
> +	  on the replacement properties.
> +
>  choice
>  	prompt "Base ISA"
>  	default ARCH_RV64I
> diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c
> index 9a4f4a23afcd..86a1d98b8b3b 100644
> --- a/arch/riscv/kernel/cpu.c
> +++ b/arch/riscv/kernel/cpu.c
> @@ -81,6 +81,9 @@ int riscv_early_of_processor_hartid(struct device_node *node, unsigned long *har
>  	return 0;
>  
>  old_interface:
> +	if (IS_ENABLED(CONFIG_NO_RISCV_ISA_FALLBACK))
> +		return -ENODEV;
> +
>  	if (of_property_read_string(node, "riscv,isa", &isa)) {
>  		pr_warn("CPU with hartid=%lu has no \"riscv,isa-base\" or \"riscv,isa\" property\n",
>  			*hart);
> diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
> index 2c4503fa984f..f6fb18d2af84 100644
> --- a/arch/riscv/kernel/cpufeature.c
> +++ b/arch/riscv/kernel/cpufeature.c
> @@ -490,7 +490,7 @@ void __init riscv_fill_hwcap(void)
>  	} else {
>  		int ret = riscv_fill_hwcap_from_ext_list(isa2hwcap);
>  
> -		if (ret) {
> +		if (ret && !IS_ENABLED(CONFIG_NO_RISCV_ISA_FALLBACK)) {
>  			pr_info("Falling back to deprecated \"riscv,isa\"\n");
>  			riscv_fill_hwcap_from_isa_string(isa2hwcap);
>  		}
> -- 
> 2.40.1
>

Should we also have a kernel command line option, 'isa_fallback', where
without this config the command line option is not necessary to fallback,
but, with this config, no fallback will be done unless 'isa_fallback' is
provided?

Thanks,
drew

  reply	other threads:[~2023-06-29  9:32 UTC|newest]

Thread overview: 26+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-06-29  8:28 [PATCH v2 00/10] RISC-V: Probe DT extension support using riscv,isa-extensions & riscv,isa-base Conor Dooley
2023-06-29  8:28 ` [PATCH v2 01/10] RISC-V: don't parse dt/acpi isa string to get rv32/rv64 Conor Dooley
2023-06-29 23:10   ` Evan Green
2023-06-29 23:13     ` Conor Dooley
2023-06-29  8:28 ` [PATCH v2 02/10] RISC-V: drop a needless check in print_isa_ext() Conor Dooley
2023-06-29  8:28 ` [PATCH v2 03/10] RISC-V: shunt isa_ext_arr to cpufeature.c Conor Dooley
2023-06-29 23:11   ` Evan Green
2023-06-30  7:28   ` Andrew Jones
2023-06-29  8:28 ` [PATCH v2 04/10] RISC-V: repurpose riscv_isa_ext array in riscv_fill_hwcap() Conor Dooley
2023-06-29  8:28 ` [PATCH v2 05/10] RISC-V: add missing single letter extension definitions Conor Dooley
2023-06-29  8:28 ` [PATCH v2 06/10] RISC-V: add single letter extensions to riscv_isa_ext Conor Dooley
2023-06-29 23:11   ` Evan Green
2023-06-29  8:28 ` [PATCH v2 07/10] RISC-V: split riscv_fill_hwcap() in 3 Conor Dooley
2023-06-29  8:28 ` [PATCH v2 08/10] RISC-V: enable extension detection from new properties Conor Dooley
2023-06-29  8:28 ` [PATCH v2 09/10] RISC-V: try new extension properties in of_early_processor_hartid() Conor Dooley
2023-06-29  8:28 ` [PATCH v2 10/10] RISC-V: provide a Kconfig option to disable parsing "riscv,isa" Conor Dooley
2023-06-29  9:31   ` Andrew Jones [this message]
2023-06-29 11:39     ` Conor Dooley
2023-06-29 13:53       ` Andrew Jones
2023-06-29 20:20         ` Conor Dooley
2023-06-29 21:16           ` Palmer Dabbelt
2023-06-29 21:44             ` Conor Dooley
2023-06-29 22:47               ` Palmer Dabbelt
2023-06-30  7:46               ` Andrew Jones
2023-06-30 13:19                 ` Conor Dooley
2023-07-01 10:49                   ` Andrew Jones

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