Re: [PATCH v5 3/3] riscv: dts: starfive: Add TRNG node for VisionFive 2

[Conor Dooley <conor@kernel.org>]

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On Sat, Jul 01, 2023 at 11:53:34PM +0200, Aurelien Jarno wrote:
> On 2023-03-14 18:45, Palmer Dabbelt wrote:
> > On Mon, 16 Jan 2023 17:54:45 PST (-0800), jiajie.ho@starfivetech.com wrote:
> > > Adding StarFive TRNG controller node to VisionFive 2 SoC.
> > > 
> > > Co-developed-by: Jenny Zhang <jenny.zhang@starfivetech.com>
> > > Signed-off-by: Jenny Zhang <jenny.zhang@starfivetech.com>
> > > Signed-off-by: Jia Jie Ho <jiajie.ho@starfivetech.com>
> > > ---
> > >  arch/riscv/boot/dts/starfive/jh7110.dtsi | 10 ++++++++++
> > >  1 file changed, 10 insertions(+)
> > > 
> > > diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi
> > > index 4ac159d79d66..3c29e0bc6246 100644
> > > --- a/arch/riscv/boot/dts/starfive/jh7110.dtsi
> > > +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
> > > @@ -455,5 +455,15 @@ uart5: serial@12020000 {
> > >  			reg-shift = <2>;
> > >  			status = "disabled";
> > >  		};
> > > +
> > > +		rng: rng@1600c000 {
> > > +			compatible = "starfive,jh7110-trng";
> > > +			reg = <0x0 0x1600C000 0x0 0x4000>;
> > > +			clocks = <&stgcrg JH7110_STGCLK_SEC_HCLK>,
> > > +				 <&stgcrg JH7110_STGCLK_SEC_MISCAHB>;
> > > +			clock-names = "hclk", "ahb";
> > > +			resets = <&stgcrg JH7110_STGRST_SEC_TOP_HRESETN>;
> > > +			interrupts = <30>;
> > > +		};
> > >  	};
> > >  };
> > 
> > Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
> 
> It appears that this patch has never been applied, although the rest of
> the series has already been merged.

Ditto here, depends on the stgcrg, so it can't be applied yet.

> Unfortunately it doesn't apply
> anymore due to other changes to that file.
> 
> Could you please rebase and resend it?

No harm in a resend of course, given it doesn't apply.

Cheers,
Conor.

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