Re: [RFC PATCH 8/8] ARM: dts: qcom: apq8064: add simple CPUFreq support

Dmitry Baryshkov
2023-07-04T13:44:34Z

On Tue, 4 Jul 2023 at 16:05, Konrad Dybcio <konrad.dybcio@linaro.org> wrote:
>
> On 2.07.2023 19:50, Dmitry Baryshkov wrote:
>
> Subject: wrong soc
>
> > Declare CPU frequency-scaling properties. Each CPU has its own clock,
> > how all CPUs have the same OPP table. Voltage scaling is not (yet)
> > enabled with this patch. It will be enabled later.
> >
> > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---Same concern as patch 4, can't see where these values came from.

Explained below.

Please use https://android.googlesource.com/kernel/msm/+/android-msm-hammerhead-3.4-marshmallow-mr2/arch/arm/mach-msm/acpuclock-8960.c
as a reference.

>
> Konrad
> > arch/arm/boot/dts/qcom/qcom-msm8960.dtsi | 147 +++++++++++++++++++++++
> > 1 file changed, 147 insertions(+)
> >
> > diff --git a/arch/arm/boot/dts/qcom/qcom-msm8960.dtsi b/arch/arm/boot/dts/qcom/qcom-msm8960.dtsi
> > index 48b3962dd4fb..995ea32f8d66 100644
> > --- a/arch/arm/boot/dts/qcom/qcom-msm8960.dtsi
> > +++ b/arch/arm/boot/dts/qcom/qcom-msm8960.dtsi
> > @@ -8,6 +8,7 @@
> > #include <dt-bindings/clock/qcom,lcc-msm8960.h>
> > #include <dt-bindings/mfd/qcom-rpm.h>
> > #include <dt-bindings/soc/qcom,gsbi.h>
> > +#include <dt-bindings/soc/qcom,krait-l2-cache.h>
> >
> > / {
> > #address-cells = <1>;
> > @@ -29,6 +30,13 @@ cpu@0 {
> > next-level-cache = <&L2>;
> > qcom,acc = <&acc0>;
> > qcom,saw = <&saw0>;
> > + clocks = <&kraitcc KRAIT_CPU_0>;
> > + clock-names = "cpu";
> > + clock-latency = <100000>;
> > + vdd-core-supply = <&saw0_vreg>;
> > + interconnects = <&L2 MASTER_KRAIT_L2 &L2 SLAVE_KRAIT_L2>;
> > + operating-points-v2 = <&cpu_opp_table>;
> > + #cooling-cells = <2>;
> > };
> >
> > cpu@1 {
> > @@ -39,6 +47,13 @@ cpu@1 {
> > next-level-cache = <&L2>;
> > qcom,acc = <&acc1>;
> > qcom,saw = <&saw1>;
> > + clocks = <&kraitcc KRAIT_CPU_0>;
> > + clock-names = "cpu";
> > + clock-latency = <100000>;
> > + vdd-core-supply = <&saw1_vreg>;
> > + interconnects = <&L2 MASTER_KRAIT_L2 &L2 SLAVE_KRAIT_L2>;
> > + operating-points-v2 = <&cpu_opp_table>;
> > + #cooling-cells = <2>;
> > };
> >
> > L2: l2-cache {
> > @@ -169,6 +184,127 @@ opp-1350000000 {
> > };
> > };
> >
> > + cpu_opp_table: opp-table-cpu {
> > + compatible = "operating-points-v2-krait-cpu";
> > + nvmem-cells = <&speedbin_efuse>;
> > +
> > + /*
> > + * Voltage thresholds are <target min max>
> > + */
> > + opp-384000000 {
> > + opp-hz = /bits/ 64 <384000000>;
> > + opp-peak-kBps = <384000>;
> > + opp-microvolt-speed0-pvs0 = <950000 950000 950000>;

acpu_freq_tbl_slow, the voltage column.
For the PVS_SLOW the pvs_tables doesn't list turbo boost, so all three
voltages are the same.

> > + opp-microvolt-speed0-pvs1 = <925000 900000 950000>;

This comes from acpu_freq_tbl_nom. The voltage from the table becomes
the middle value (min).
For PVS_NOM the pvs_tables has the turbo value (25000), which
acpuclock-krait applied by default, this becomes the first (target)
value.
For maximum I added another 25 mV to account for this exact value not
being supported by the core (SAW) regulator.

> > + opp-microvolt-speed0-pvs3 = <875000 850000 900000>;
> > + opp-supported-hw = <0x1>;
> > + /*
> > + * higher latency as it requires switching between
> > + * clock sources
> > + */
> > + clock-latency-ns = <244144>;
> > + };
> > +
> > + opp-486000000 {
> > + opp-hz = /bits/ 64 <486000000>;
> > + opp-peak-kBps = <702000>;
> > + opp-microvolt-speed0-pvs0 = <975000 975000 975000>;
> > + opp-microvolt-speed0-pvs1 = <950000 925000 975000>;
> > + opp-microvolt-speed0-pvs3 = <900000 875000 925000>;
> > + opp-supported-hw = <0x1>;
> > + };
> > +
> > + opp-594000000 {
> > + opp-hz = /bits/ 64 <594000000>;
> > + opp-peak-kBps = <702000>;
> > + opp-microvolt-speed0-pvs0 = <1000000 1000000 1000000>;
> > + opp-microvolt-speed0-pvs1 = <975000 950000 1000000>;
> > + opp-microvolt-speed0-pvs3 = <925000 900000 950000>;
> > + opp-supported-hw = <0x1>;
> > + };
> > +
> > + opp-702000000 {
> > + opp-hz = /bits/ 64 <702000000>;
> > + opp-peak-kBps = <702000>;
> > + opp-microvolt-speed0-pvs0 = <1025000 1025000 1025000>;
> > + opp-microvolt-speed0-pvs1 = <1000000 975000 1025000>;
> > + opp-microvolt-speed0-pvs3 = <950000 925000 975000>;
> > + opp-supported-hw = <0x1>;
> > + };
> > +
> > + opp-810000000 {
> > + opp-hz = /bits/ 64 <810000000>;
> > + opp-peak-kBps = <702000>;
> > + opp-microvolt-speed0-pvs0 = <1075000 1075000 1075000>;
> > + opp-microvolt-speed0-pvs1 = <1050000 1025000 1075000>;
> > + opp-microvolt-speed0-pvs3 = <1000000 975000 1025000>;
> > + opp-supported-hw = <0x1>;
> > + };
> > +
> > + opp-918000000 {
> > + opp-hz = /bits/ 64 <918000000>;
> > + opp-peak-kBps = <702000>;
> > + opp-microvolt-speed0-pvs0 = <1100000 1100000 1100000>;
> > + opp-microvolt-speed0-pvs1 = <1075000 1050000 1100000>;
> > + opp-microvolt-speed0-pvs3 = <1025000 1000000 1050000>;
> > + opp-supported-hw = <0x1>;
> > + };
> > +
> > + opp-1026000000 {
> > + opp-hz = /bits/ 64 <1026000000>;
> > + opp-peak-kBps = <702000>;
> > + opp-microvolt-speed0-pvs0 = <1125000 1125000 1125000>;
> > + opp-microvolt-speed0-pvs1 = <1100000 1075000 1125000>;
> > + opp-microvolt-speed0-pvs3 = <1050000 1025000 1075000>;
> > + opp-supported-hw = <0x1>;
> > + };
> > +
> > + opp-1134000000 {
> > + opp-hz = /bits/ 64 <1134000000>;
> > + opp-peak-kBps = <1350000>;
> > + opp-microvolt-speed0-pvs0 = <1175000 1175000 1175000>;
> > + opp-microvolt-speed0-pvs1 = <1150000 1125000 1175000>;
> > + opp-microvolt-speed0-pvs3 = <1100000 1075000 1125000>;
> > + opp-supported-hw = <0x1>;
> > + };
> > +
> > + opp-1242000000 {
> > + opp-hz = /bits/ 64 <1242000000>;
> > + opp-peak-kBps = <1350000>;
> > + opp-microvolt-speed0-pvs0 = <1200000 1200000 1200000>;
> > + opp-microvolt-speed0-pvs1 = <1175000 1150000 1200000>;
> > + opp-microvolt-speed0-pvs3 = <1125000 1100000 1150000>;
> > + opp-supported-hw = <0x1>;
> > + };
> > +
> > + opp-1350000000 {
> > + opp-hz = /bits/ 64 <1350000000>;
> > + opp-peak-kBps = <1350000>;
> > + opp-microvolt-speed0-pvs0 = <1225000 1225000 1225000>;
> > + opp-microvolt-speed0-pvs1 = <1200000 1175000 1225000>;
> > + opp-microvolt-speed0-pvs3 = <1150000 1125000 1175000>;
> > + opp-supported-hw = <0x1>;
> > + };
> > +
> > + opp-1458000000 {
> > + opp-hz = /bits/ 64 <1458000000>;
> > + opp-peak-kBps = <1350000>;
> > + opp-microvolt-speed0-pvs0 = <1237500 1237500 1237500>;
> > + opp-microvolt-speed0-pvs1 = <1212500 1187500 1237500>;
> > + opp-microvolt-speed0-pvs3 = <1162500 1137500 1187500>;
> > + opp-supported-hw = <0x1>;
> > + };
> > +
> > + opp-1512000000 {
> > + opp-hz = /bits/ 64 <1512000000>;
> > + opp-peak-kBps = <1350000>;
> > + opp-microvolt-speed0-pvs0 = <1250000 1250000 1250000>;
> > + opp-microvolt-speed0-pvs1 = <1225000 1200000 1250000>;
> > + opp-microvolt-speed0-pvs3 = <1175000 1150000 1200000>;
> > + opp-supported-hw = <0x1>;
> > + };
> > + };
> > +
> > memory {
> > device_type = "memory";
> > reg = <0x0 0x0>;
> > @@ -266,6 +402,17 @@ msmgpio: pinctrl@800000 {
> > reg = <0x800000 0x4000>;
> > };
> >
> > + qfprom: qfprom@700000 {
> > + compatible = "qcom,msm8960-qfprom", "qcom,qfprom";
> > + reg = <0x00700000 0x1000>;
> > + #address-cells = <1>;
> > + #size-cells = <1>;
> > + ranges;
> > + speedbin_efuse: speedbin@c0 {
> > + reg = <0x0c0 0x4>;
> > + };
> > + };
> > +
> > gcc: clock-controller@900000 {
> > compatible = "qcom,gcc-msm8960";
> > #clock-cells = <1>;

--
With best wishes
Dmitry