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From: Conor Dooley <conor@kernel.org>
To: guoniu.zhou@oss.nxp.com
Cc: linux-media@vger.kernel.org, devicetree@vger.kernel.org,
	linux-imx@nxp.com, mchehab@kernel.org,
	laurent.pinchart@ideasonboard.com, robh+dt@kernel.org,
	krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org,
	jacopo.mondi@ideasonboard.com
Subject: Re: [PATCH 1/2] media: dt-bindings: Add binding doc for i.MX93 MIPI CSI-2
Date: Tue, 4 Jul 2023 17:53:38 +0100	[thread overview]
Message-ID: <20230704-unnamable-sandpaper-01fd3631e1df@spud> (raw)
In-Reply-To: <20230703113734.762307-2-guoniu.zhou@oss.nxp.com>

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Hey,

I know little about media bindings, so only got a single comment for
you.

On Mon, Jul 03, 2023 at 07:37:33PM +0800, guoniu.zhou@oss.nxp.com wrote:
> From: "Guoniu.zhou" <guoniu.zhou@nxp.com>
> 
> Add new binding documentation for DesignWare Core MIPI CSI-2 receiver
> and DPHY found on NXP i.MX93.
> 
> Signed-off-by: Guoniu.zhou <guoniu.zhou@nxp.com>
> ---
>  .../bindings/media/nxp,dwc-mipi-csi2.yaml     | 140 ++++++++++++++++++
>  1 file changed, 140 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/media/nxp,dwc-mipi-csi2.yaml b/Documentation/devicetree/bindings/media/nxp,dwc-mipi-csi2.yaml
> new file mode 100644
> index 000000000000..ece6fb8991d4
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/media/nxp,dwc-mipi-csi2.yaml

The filename of the binding should match the compatible.

> @@ -0,0 +1,140 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/media/nxp,dwc-mipi-csi2.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: NXP i.MX93 MIPI CSI-2 Host Controller receiver
> +
> +maintainers:
> +  - G.N. Zhou <guoniu.zhou@nxp.com>
> +
> +description: |-
> +  The MIPI CSI-2 receiver found on i.MX93 originates from Synopsys
> +  DesignWare Core and it implements the CSI-2 protocol on the host
> +  side and a DPHY configured as a Slave acts as the physical layer.
> +  Two data lanes are supported on i.MX93 family devices and the data
> +  rate of each lane support up to 1.5Gbps.
> +
> +  While the CSI-2 receiver is separate from the MIPI D-PHY IP core,
> +  the PHY is completely wrapped by the CSI-2 controller and expose
> +  a control interface which only can communicate with CSI-2 controller
> +  This binding thus covers both IP cores.
> +
> +properties:
> +  compatible:
> +    enum:
> +      - fsl,imx93-mipi-csi2

Everywhere else you say NXP, why use Freescale here?

Cheers,
Conor.

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  parent reply	other threads:[~2023-07-04 16:54 UTC|newest]

Thread overview: 13+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-07-03 11:37 [PATCH 0/2] media: nxp: add i.MX93 MIPI CSI-2 support guoniu.zhou
2023-07-03 11:37 ` [PATCH 1/2] media: dt-bindings: Add binding doc for i.MX93 MIPI CSI-2 guoniu.zhou
2023-07-04  8:38   ` Alexander Stein
2023-07-05  1:36     ` G.N. Zhou (OSS)
2023-07-05 21:23       ` Laurent Pinchart
2023-07-06 10:08         ` G.N. Zhou (OSS)
2023-07-04 16:53   ` Conor Dooley [this message]
2023-07-05  1:30     ` G.N. Zhou (OSS)
2023-07-05 21:08       ` Conor Dooley
2023-07-03 11:37 ` [PATCH 2/2] media: nxp: add driver for i.MX93 MIPI CSI-2 controller and D-PHY guoniu.zhou
2023-07-04  9:23   ` Alexander Stein
2023-07-05  3:52     ` G.N. Zhou (OSS)
2023-07-05  6:50       ` Alexander Stein

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