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[2003:e4:1f4b:7100:f22f:74ff:fe1f:3a53]) by smtp.gmail.com with ESMTPSA id b3-20020adfe303000000b0030fd03e3d25sm31371656wrj.75.2023.07.05.08.30.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 05 Jul 2023 08:30:57 -0700 (PDT) From: Thierry Reding To: Daniel Lezcano , Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Jon Hunter , devicetree@vger.kernel.org, linux-tegra@vger.kernel.org Subject: [PATCH] dt-bindings: timer: tegra: Convert to json-schema Date: Wed, 5 Jul 2023 17:30:56 +0200 Message-ID: <20230705153056.2514908-1-thierry.reding@gmail.com> X-Mailer: git-send-email 2.41.0 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Thierry Reding Convert the Tegra timer bindings from the free-form text format to json-schema. Signed-off-by: Thierry Reding --- .../bindings/timer/nvidia,tegra20-timer.yaml | 121 ++++++++++++++++++ .../bindings/timer/nvidia,tegra210-timer.yaml | 70 ++++++++++ 2 files changed, 191 insertions(+) create mode 100644 Documentation/devicetree/bindings/timer/nvidia,tegra20-timer.yaml create mode 100644 Documentation/devicetree/bindings/timer/nvidia,tegra210-timer.yaml diff --git a/Documentation/devicetree/bindings/timer/nvidia,tegra20-timer.yaml b/Documentation/devicetree/bindings/timer/nvidia,tegra20-timer.yaml new file mode 100644 index 000000000000..d57663d73095 --- /dev/null +++ b/Documentation/devicetree/bindings/timer/nvidia,tegra20-timer.yaml @@ -0,0 +1,121 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/timer/nvidia,tegra20-timer.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NVIDIA Tegra20 (and later) Timer + +maintainers: + - Thierry Reding + - Jon Hunter + +description: The Tegra20 timer provides four 29-bit timer channels and a single 32-bit free + running counter. The first two channels may also trigger a watchdog reset. + + The timer found on Tegra30 provides ten 29-bit timer channels, a single 32-bit free running + counter, and 5 watchdog modules. The first two channels may also trigger a legacy watchdog + reset. + +properties: + compatible: + oneOf: + - items: + - enum: + - nvidia,tegra114-timer + - nvidia,tegra124-timer + - const: nvidia,tegra30-timer + + - items: + - const: nvidia,tegra30-timer + - const: nvidia,tegra20-timer + + - const: nvidia,tegra20-timer + + reg: + maxItems: 1 + + interrupts: + minItems: 4 + maxItems: 6 + + clocks: + items: + - description: module clock + + clock-names: + items: + - const: timer + +allOf: + - if: + properties: + compatible: + contains: + const: nvidia,tegra30-timer + then: + properties: + interrupts: + description: One interrupt per each of timer channels 1 through 5 and one shared + interrupt for the remaining channels. + minItems: 6 + else: + properties: + interrupts: + description: One interrupt for each timer channel. + maxItems: 4 + +additionalProperties: false + +required: + - compatible + - reg + - interrupts + - clocks + +examples: + - | + #include + #include + + timer@60005000 { + compatible = "nvidia,tegra20-timer"; + reg = <0x60005000 0x60>; + interrupts = , + , + , + ; + clocks = <&tegra_car TEGRA20_CLK_TWD>; + }; + + - | + #include + #include + + timer@60005000 { + compatible = "nvidia,tegra30-timer", "nvidia,tegra20-timer"; + reg = <0x60005000 0x400>; + interrupts = , + , + , + , + , + ; + clocks = <&tegra_car TEGRA30_CLK_TWD>; + }; + + - | + #include + #include + + timer@60005000 { + compatible = "nvidia,tegra114-timer", "nvidia,tegra30-timer"; + reg = <0x60005000 0x400>; + interrupts = , + , + , + , + , + ; + clocks = <&tegra_car TEGRA114_CLK_TIMER>; + }; diff --git a/Documentation/devicetree/bindings/timer/nvidia,tegra210-timer.yaml b/Documentation/devicetree/bindings/timer/nvidia,tegra210-timer.yaml new file mode 100644 index 000000000000..2b42d8d03b7b --- /dev/null +++ b/Documentation/devicetree/bindings/timer/nvidia,tegra210-timer.yaml @@ -0,0 +1,70 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/timer/nvidia,tegra210-timer.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NVIDIA Tegra210 Timer + +maintainers: + - Thierry Reding + - Jon Hunter + +description: The Tegra210 timer provides fourteen 29-bit timer counters and one 32-bit timestamp + counter. The TMRs run at either a fixed 1 MHz clock rate derived from the oscillator clock + (TMR0-TMR9) or directly at the oscillator clock (TMR10-TMR13). Each TMR can be programmed to + generate one-shot, periodic, or watchdog interrupts. + +properties: + compatible: + const: nvidia,tegra210-timer + + reg: + maxItems: 1 + + interrupts: + description: One interrupt per each timer channels 0 through 13. + minItems: 14 + maxItems: 14 + + clocks: + items: + - description: module clock + + clock-names: + items: + - const: timer + +additionalProperties: false + +required: + - compatible + - reg + - interrupts + - clocks + +examples: + - | + #include + #include + + timer@60005000 { + compatible = "nvidia,tegra210-timer"; + reg = <0x60005000 0x400>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + ; + clocks = <&tegra_car TEGRA210_CLK_TIMER>; + clock-names = "timer"; + }; -- 2.41.0