From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0C32AC001B0 for ; Sat, 8 Jul 2023 15:23:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230226AbjGHPXh (ORCPT ); Sat, 8 Jul 2023 11:23:37 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57034 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229682AbjGHPXb (ORCPT ); Sat, 8 Jul 2023 11:23:31 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [IPv6:2604:1380:4641:c500::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7665C1709; Sat, 8 Jul 2023 08:23:30 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 0A5E460DBD; Sat, 8 Jul 2023 15:23:30 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 0B4FEC433CA; Sat, 8 Jul 2023 15:23:22 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1688829809; bh=LRKuU4wR21FSTMd32UkZLDmh6O5X3KbUUhZ6esX8nWA=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=OkWBrDLThWtCE511INbneL4ICaMtIobUriY1mQMfu2lXzvcRX2PfFMGCt98OYWLzZ vowzfrJQtvcudEafsFzuh7qui5Q1slDosfaqVyvj5dwz8nD+Ptw7jOivqV5G5bF2YA N+eVP6XGo1N5oItiDUgNhfNw8EC9/GhlcxjGAD3LUE+iTmxD2siSztefUyY70safiI QlPalmFDoHMVa0dPmWgo4CU6eQx+fCqhkLtMF5xj/6QS9Ix0m+CLRcc6u74Eiiz4cR FNGU+yHPj1MlV2JwxWZ4RDdlKmD/2DAbjhqo9sqY1YQGqxisL970O0wed3CISh83pk x1DMqMXtHUmxw== Date: Sat, 8 Jul 2023 16:23:18 +0100 From: Jonathan Cameron To: Jishnu Prakash Cc: , , , , , , , , , , , , , , "Bjorn Andersson" , Konrad Dybcio , Lars-Peter Clausen , , , Subject: Re: [PATCH 09/11] iio: adc: Update QCOM ADC drivers for bindings path change Message-ID: <20230708162318.1e2b169f@jic23-huawei> In-Reply-To: <20230708072835.3035398-10-quic_jprakash@quicinc.com> References: <20230708072835.3035398-1-quic_jprakash@quicinc.com> <20230708072835.3035398-10-quic_jprakash@quicinc.com> X-Mailer: Claws Mail 4.1.1 (GTK 3.24.38; x86_64-pc-linux-gnu) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On Sat, 8 Jul 2023 12:58:33 +0530 Jishnu Prakash wrote: > Update ADC dt-bindings file paths in QCOM ADC driver files to > match the dt-bindings change moving the files from 'iio' to > 'iio/adc' folder. > > Signed-off-by: Jishnu Prakash Do the move in one go. Diff rename detection will make the resulting patch more trivial to look at than this multistep version. Jonathan > --- > drivers/iio/adc/qcom-spmi-adc5-gen3.c | 2 +- > drivers/iio/adc/qcom-spmi-adc5.c | 2 +- > drivers/iio/adc/qcom-spmi-vadc.c | 2 +- > 3 files changed, 3 insertions(+), 3 deletions(-) > > diff --git a/drivers/iio/adc/qcom-spmi-adc5-gen3.c b/drivers/iio/adc/qcom-spmi-adc5-gen3.c > index fe5515ee8451..78ece8fccbae 100644 > --- a/drivers/iio/adc/qcom-spmi-adc5-gen3.c > +++ b/drivers/iio/adc/qcom-spmi-adc5-gen3.c > @@ -23,7 +23,7 @@ > #include > #include > > -#include > +#include > > #define ADC5_GEN3_HS 0x45 > #define ADC5_GEN3_HS_BUSY BIT(7) > diff --git a/drivers/iio/adc/qcom-spmi-adc5.c b/drivers/iio/adc/qcom-spmi-adc5.c > index 6cebeaa69a75..5dfcb770d663 100644 > --- a/drivers/iio/adc/qcom-spmi-adc5.c > +++ b/drivers/iio/adc/qcom-spmi-adc5.c > @@ -21,7 +21,7 @@ > #include > #include > > -#include > +#include > > #define ADC5_USR_REVISION1 0x0 > #define ADC5_USR_STATUS1 0x8 > diff --git a/drivers/iio/adc/qcom-spmi-vadc.c b/drivers/iio/adc/qcom-spmi-vadc.c > index f5c6f1f27b2c..c3602c53968a 100644 > --- a/drivers/iio/adc/qcom-spmi-vadc.c > +++ b/drivers/iio/adc/qcom-spmi-vadc.c > @@ -20,7 +20,7 @@ > #include > #include > > -#include > +#include > > /* VADC register and bit definitions */ > #define VADC_REVISION2 0x1