From: Conor Dooley <conor.dooley@microchip.com>
To: <palmer@dabbelt.com>
Cc: <conor@kernel.org>, <conor.dooley@microchip.com>,
Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Paul Walmsley <paul.walmsley@sifive.com>,
Albert Ou <aou@eecs.berkeley.edu>,
"Jonathan Corbet" <corbet@lwn.net>,
Andrew Jones <ajones@ventanamicro.com>,
"Heiko Stuebner" <heiko.stuebner@vrull.eu>,
Evan Green <evan@rivosinc.com>,
Sunil V L <sunilvl@ventanamicro.com>, <linux-doc@vger.kernel.org>,
<linux-riscv@lists.infradead.org>, <devicetree@vger.kernel.org>,
<linux-kernel@vger.kernel.org>
Subject: [PATCH v4 10/11] RISC-V: try new extension properties in of_early_processor_hartid()
Date: Mon, 10 Jul 2023 10:35:45 +0100 [thread overview]
Message-ID: <20230710-multitude-badly-1c149269766f@wendy> (raw)
In-Reply-To: <20230710-equipment-stained-dd042d66ba5d@wendy>
To fully deprecate the kernel's use of "riscv,isa",
of_early_processor_hartid() needs to first try using the new properties,
before falling back to "riscv,isa".
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
Changes in v3:
- Add some printouts to explain what went wrong while parsing harts,
so that if none are found there's at least a hint before we hit a
BUG()
---
arch/riscv/kernel/cpu.c | 29 ++++++++++++++++++++++++++++-
1 file changed, 28 insertions(+), 1 deletion(-)
diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c
index 4f1f12f34b63..28d5af21f544 100644
--- a/arch/riscv/kernel/cpu.c
+++ b/arch/riscv/kernel/cpu.c
@@ -61,8 +61,35 @@ int riscv_early_of_processor_hartid(struct device_node *node, unsigned long *har
return -ENODEV;
}
+ if (of_property_read_string(node, "riscv,isa-base", &isa))
+ goto old_interface;
+
+ if (IS_ENABLED(CONFIG_32BIT) && strncasecmp(isa, "rv32i", 5)) {
+ pr_warn("CPU with hartid=%lu does not support rv32i", *hart);
+ return -ENODEV;
+ }
+
+ if (IS_ENABLED(CONFIG_64BIT) && strncasecmp(isa, "rv64i", 5)) {
+ pr_warn("CPU with hartid=%lu does not support rv64i", *hart);
+ return -ENODEV;
+ }
+
+ if (!of_property_present(node, "riscv,isa-extensions"))
+ return -ENODEV;
+
+ if (of_property_match_string(node, "riscv,isa-extensions", "i") < 0 ||
+ of_property_match_string(node, "riscv,isa-extensions", "m") < 0 ||
+ of_property_match_string(node, "riscv,isa-extensions", "a") < 0) {
+ pr_warn("CPU with hartid=%lu does not support ima", *hart);
+ return -ENODEV;
+ }
+
+ return 0;
+
+old_interface:
if (of_property_read_string(node, "riscv,isa", &isa)) {
- pr_warn("CPU with hartid=%lu has no \"riscv,isa\" property\n", *hart);
+ pr_warn("CPU with hartid=%lu has no \"riscv,isa-base\" or \"riscv,isa\" property\n",
+ *hart);
return -ENODEV;
}
--
2.40.1
next prev parent reply other threads:[~2023-07-10 9:41 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-07-10 9:35 [PATCH v4 00/11] RISC-V: Probe DT extension support using riscv,isa-extensions & riscv,isa-base Conor Dooley
2023-07-10 9:35 ` [PATCH v4 01/11] RISC-V: Provide a more helpful error message on invalid ISA strings Conor Dooley
2023-07-10 9:35 ` [PATCH v4 02/11] RISC-V: don't parse dt/acpi isa string to get rv32/rv64 Conor Dooley
2023-07-10 9:35 ` [PATCH v4 03/11] RISC-V: drop a needless check in print_isa_ext() Conor Dooley
2023-07-10 9:35 ` [PATCH v4 04/11] RISC-V: shunt isa_ext_arr to cpufeature.c Conor Dooley
2023-07-10 9:35 ` [PATCH v4 05/11] RISC-V: repurpose riscv_isa_ext array in riscv_fill_hwcap() Conor Dooley
2023-07-12 17:34 ` Evan Green
2023-07-10 9:35 ` [PATCH v4 06/11] RISC-V: add missing single letter extension definitions Conor Dooley
2023-07-10 9:35 ` [PATCH v4 07/11] RISC-V: add single letter extensions to riscv_isa_ext Conor Dooley
2023-07-10 9:35 ` [PATCH v4 08/11] RISC-V: split riscv_fill_hwcap() in 3 Conor Dooley
2023-07-10 9:35 ` [PATCH v4 09/11] RISC-V: enable extension detection from new properties Conor Dooley
2023-07-10 9:35 ` Conor Dooley [this message]
2023-07-10 9:35 ` [PATCH v4 11/11] RISC-V: provide Kconfig & commandline options to control parsing "riscv,isa" Conor Dooley
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