From: guoniu.zhou@oss.nxp.com
To: linux-media@vger.kernel.org, devicetree@vger.kernel.org,
linux-imx@nxp.com
Cc: mchehab@kernel.org, laurent.pinchart@ideasonboard.com,
alexander.stein@ew.tq-group.com,
krzysztof.kozlowski+dt@linaro.org, robh+dt@kernel.org,
conor+dt@kernel.org, jacopo.mondi@ideasonboard.com
Subject: [PATCH v2 1/2] media: dt-bindings: Add binding doc for i.MX93 MIPI CSI-2
Date: Mon, 10 Jul 2023 14:03:51 +0800 [thread overview]
Message-ID: <20230710060352.584286-2-guoniu.zhou@oss.nxp.com> (raw)
In-Reply-To: <20230710060352.584286-1-guoniu.zhou@oss.nxp.com>
From: "Guoniu.zhou" <guoniu.zhou@nxp.com>
Add new binding documentation for DesignWare Core MIPI CSI-2 receiver
and DPHY found on NXP i.MX93.
Signed-off-by: Guoniu.zhou <guoniu.zhou@nxp.com>
---
.../bindings/media/nxp,dwc-mipi-csi2.yaml | 130 ++++++++++++++++++
1 file changed, 130 insertions(+)
diff --git a/Documentation/devicetree/bindings/media/nxp,dwc-mipi-csi2.yaml b/Documentation/devicetree/bindings/media/nxp,dwc-mipi-csi2.yaml
new file mode 100644
index 000000000000..aa5d79ada9b9
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/nxp,dwc-mipi-csi2.yaml
@@ -0,0 +1,130 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/media/nxp,dwc-mipi-csi2.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NXP i.MX93 MIPI CSI-2 Host Controller receiver
+
+maintainers:
+ - G.N. Zhou <guoniu.zhou@nxp.com>
+
+description: |-
+ The MIPI CSI-2 receiver found on i.MX93 originates from Synopsys
+ DesignWare Core and it implements the CSI-2 protocol on the host
+ side and a DPHY configured as a Slave acts as the physical layer.
+ Two data lanes are supported on i.MX93 family devices and the data
+ rate of each lane support up to 1.5Gbps.
+
+ While the CSI-2 receiver is separate from the MIPI D-PHY IP core,
+ the PHY is completely wrapped by the CSI-2 controller and expose
+ a control interface which only can communicate with CSI-2 controller
+ This binding thus covers both IP cores.
+
+properties:
+ compatible:
+ enum:
+ - fsl,imx93-mipi-csi2
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: The peripheral clock (a.k.a. APB clock)
+ - description: The pixel clock
+ - description: The MIPI D-PHY clock
+
+ clock-names:
+ items:
+ - const: per
+ - const: pixel
+ - const: phy_cfg
+
+ power-domains:
+ maxItems: 1
+
+ ports:
+ $ref: /schemas/graph.yaml#/properties/ports
+
+ properties:
+ port@0:
+ $ref: /schemas/graph.yaml#/$defs/port-base
+ unevaluatedProperties: false
+ description:
+ Input port node, single endpoint describing the CSI-2 transmitter.
+
+ properties:
+ endpoint:
+ $ref: video-interfaces.yaml#
+ unevaluatedProperties: false
+
+ properties:
+ data-lanes:
+ minItems: 1
+ items:
+ - const: 1
+ - const: 2
+
+ required:
+ - data-lanes
+
+ port@1:
+ $ref: /schemas/graph.yaml#/properties/port
+ description:
+ Output port node
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+ - clock-names
+ - power-domains
+ - ports
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/imx93-clock.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/interrupt-controller/irq.h>
+ #include <dt-bindings/power/fsl,imx93-power.h>
+
+ mipi-csi@4ae00000 {
+ compatible = "fsl,imx93-mipi-csi2";
+ reg = <0x4ae00000 0x10000>;
+ interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX93_CLK_MIPI_CSI_GATE>,
+ <&clks IMX93_CLK_CAM_PIX>,
+ <&clks IMX93_CLK_MIPI_PHY_CFG>;
+ clock-names = "per", "pixel", "phy_cfg";
+ power-domains = <&media_blk_ctrl IMX93_MEDIABLK_PD_MIPI_CSI>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ mipi_from_sensor: endpoint {
+ remote-endpoint = <&ap1302_to_mipi>;
+ data-lanes = <1 2>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ mipi_to_isi: endpoint {
+ remote-endpoint = <&isi_in>;
+ };
+ };
+ };
+ };
+...
--
2.37.1
next prev parent reply other threads:[~2023-07-10 5:59 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-07-10 6:03 [PATCH v2 0/2] media: nxp: add i.MX93 MIPI CSI-2 support guoniu.zhou
2023-07-10 6:03 ` guoniu.zhou [this message]
2023-07-10 15:27 ` [PATCH v2 1/2] media: dt-bindings: Add binding doc for i.MX93 MIPI CSI-2 Rob Herring
2023-09-17 20:46 ` Laurent Pinchart
2023-07-10 6:03 ` [PATCH v2 2/2] media: nxp: add driver for i.MX93 MIPI CSI-2 controller and D-PHY guoniu.zhou
2023-09-13 20:36 ` Sakari Ailus
2023-09-17 21:25 ` Laurent Pinchart
2023-09-21 18:45 ` Niklas Söderlund
2023-09-21 21:38 ` Laurent Pinchart
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20230710060352.584286-2-guoniu.zhou@oss.nxp.com \
--to=guoniu.zhou@oss.nxp.com \
--cc=alexander.stein@ew.tq-group.com \
--cc=conor+dt@kernel.org \
--cc=devicetree@vger.kernel.org \
--cc=jacopo.mondi@ideasonboard.com \
--cc=krzysztof.kozlowski+dt@linaro.org \
--cc=laurent.pinchart@ideasonboard.com \
--cc=linux-imx@nxp.com \
--cc=linux-media@vger.kernel.org \
--cc=mchehab@kernel.org \
--cc=robh+dt@kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).