From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8C37CEB64D9 for ; Mon, 10 Jul 2023 09:49:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231721AbjGJJtx (ORCPT ); Mon, 10 Jul 2023 05:49:53 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35180 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231738AbjGJJtK (ORCPT ); Mon, 10 Jul 2023 05:49:10 -0400 Received: from mail-io1-xd2a.google.com (mail-io1-xd2a.google.com [IPv6:2607:f8b0:4864:20::d2a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7D20349EB for ; Mon, 10 Jul 2023 02:44:13 -0700 (PDT) Received: by mail-io1-xd2a.google.com with SMTP id ca18e2360f4ac-78666f06691so132355839f.0 for ; Mon, 10 Jul 2023 02:44:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1688982253; x=1691574253; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=WcrEH8OhJJZAITXaKfZ/zoRtjGXDZoTtkGYiYC2zu4k=; b=k9I6V1IUS4US1apWUM7Biypnkl1j3cmwGs/+X8mONjgRQ0/mvTIFsLT5xlP2nSMe9U Zj8UQ5TW38KLf2+UFXp7URzCpnLlvdBt71DZonWt6vajN3vWx9PaN7vrHUnY8FXNmtId sM5/q2vhuf0KK5/xIF7IBJlFoCTi4RhgWYQcQ0lUUNkOD1/qH47+LfhtkbX66td1BnjE M/UlmhyYevubBtLAUXDfdXsOa2rf9DdPEd8U73JDtkPIShLKAbOdWGrsHZicPdrZLpnD oJlP1Mq7cZQzFvBkh5tsmMm8HL2GmO8dtYvQPrSW/502WOqvTGr5TORZUJgxSIBuxGbe IKsQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1688982253; x=1691574253; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=WcrEH8OhJJZAITXaKfZ/zoRtjGXDZoTtkGYiYC2zu4k=; b=YT4/PmvIroQ7XzttE6mx+DbHyxsyxe+2aFyFXKsfbCYlspdiJciZZAVPGZ/bBlTraA OgWJVtG/DrtujIe4DQ7QWWTt0XFEkrBMR8iJVoRR2OPewD+eRl2+jI5R647Kwd6C1IlB 3N6UZsDZWm2zecp58YC3g742nngP/5DplAAfs+baj1R4GonMtwcgXn6EMKmkvTFlp+fy QqTOopudf2xu0SO5C0Kd+OOqSDKqT13t7TSxxcU/xZq3g1B+4dreIpIgMfhWxUckg3yQ d2vfxk1jKSugwhflZabGBFwiSd9373OHPJFzmSCftlpwyp5yOn43F6tilW6R38m+2w8J NC2A== X-Gm-Message-State: ABy/qLZfSYgu+TCvTs8wNK8BGjspqoptMbKKjbzybzQ4SfJvRM1CrP0m KOONczXdsEVyg9jvKEzJ3AYP2A== X-Google-Smtp-Source: APBJJlFByc//esrREQrT/7t7e+ELFneay8aEl5p8Am6SDXZPF8z6e4ES81u5UEKeQZknUM1Z0b3Iqw== X-Received: by 2002:a6b:90b:0:b0:783:47cd:27b5 with SMTP id t11-20020a6b090b000000b0078347cd27b5mr11431490ioi.3.1688982252722; Mon, 10 Jul 2023 02:44:12 -0700 (PDT) Received: from anup-ubuntu-vm.localdomain ([103.97.165.210]) by smtp.gmail.com with ESMTPSA id k1-20020a6b7a41000000b007870c56387dsm936938iop.49.2023.07.10.02.44.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 Jul 2023 02:44:12 -0700 (PDT) From: Anup Patel To: Palmer Dabbelt , Paul Walmsley , Thomas Gleixner , Marc Zyngier , Rob Herring , Krzysztof Kozlowski Cc: Atish Patra , Andrew Jones , Sunil V L , Conor Dooley , Saravana Kannan , Anup Patel , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Anup Patel Subject: [PATCH v5 5/9] irqchip/riscv-imsic: Add support for PCI MSI irqdomain Date: Mon, 10 Jul 2023 15:13:17 +0530 Message-Id: <20230710094321.1378351-6-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230710094321.1378351-1-apatel@ventanamicro.com> References: <20230710094321.1378351-1-apatel@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The Linux PCI framework requires it's own dedicated MSI irqdomain so let us create PCI MSI irqdomain as child of the IMSIC base irqdomain. Signed-off-by: Anup Patel --- drivers/irqchip/Kconfig | 7 +++++ drivers/irqchip/irq-riscv-imsic.c | 49 +++++++++++++++++++++++++++++++ 2 files changed, 56 insertions(+) diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig index 8ef18be5f37b..d700980372ef 100644 --- a/drivers/irqchip/Kconfig +++ b/drivers/irqchip/Kconfig @@ -550,6 +550,13 @@ config RISCV_IMSIC select IRQ_DOMAIN_HIERARCHY select GENERIC_MSI_IRQ +config RISCV_IMSIC_PCI + bool + depends on RISCV_IMSIC + depends on PCI + depends on PCI_MSI + default RISCV_IMSIC + config EXYNOS_IRQ_COMBINER bool "Samsung Exynos IRQ combiner support" if COMPILE_TEST depends on (ARCH_EXYNOS && ARM) || COMPILE_TEST diff --git a/drivers/irqchip/irq-riscv-imsic.c b/drivers/irqchip/irq-riscv-imsic.c index ceb5e0fc883c..061bba1b69a2 100644 --- a/drivers/irqchip/irq-riscv-imsic.c +++ b/drivers/irqchip/irq-riscv-imsic.c @@ -17,6 +17,7 @@ #include #include #include +#include #include #include #include @@ -80,6 +81,7 @@ struct imsic_priv { /* IRQ domains */ struct irq_domain *base_domain; + struct irq_domain *pci_domain; struct irq_domain *plat_domain; }; @@ -530,6 +532,39 @@ static const struct irq_domain_ops imsic_base_domain_ops = { .free = imsic_irq_domain_free, }; +#ifdef CONFIG_RISCV_IMSIC_PCI + +static void imsic_pci_mask_irq(struct irq_data *d) +{ + pci_msi_mask_irq(d); + irq_chip_mask_parent(d); +} + +static void imsic_pci_unmask_irq(struct irq_data *d) +{ + pci_msi_unmask_irq(d); + irq_chip_unmask_parent(d); +} + +static struct irq_chip imsic_pci_irq_chip = { + .name = "RISC-V IMSIC-PCI", + .irq_mask = imsic_pci_mask_irq, + .irq_unmask = imsic_pci_unmask_irq, + .irq_eoi = irq_chip_eoi_parent, +}; + +static struct msi_domain_ops imsic_pci_domain_ops = { +}; + +static struct msi_domain_info imsic_pci_domain_info = { + .flags = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS | + MSI_FLAG_PCI_MSIX | MSI_FLAG_MULTI_PCI_MSI), + .ops = &imsic_pci_domain_ops, + .chip = &imsic_pci_irq_chip, +}; + +#endif + static struct irq_chip imsic_plat_irq_chip = { .name = "RISC-V IMSIC-PLAT", }; @@ -554,12 +589,26 @@ static int __init imsic_irq_domains_init(struct fwnode_handle *fwnode) } irq_domain_update_bus_token(imsic->base_domain, DOMAIN_BUS_NEXUS); +#ifdef CONFIG_RISCV_IMSIC_PCI + /* Create PCI MSI domain */ + imsic->pci_domain = pci_msi_create_irq_domain(fwnode, + &imsic_pci_domain_info, + imsic->base_domain); + if (!imsic->pci_domain) { + pr_err("Failed to create IMSIC PCI domain\n"); + irq_domain_remove(imsic->base_domain); + return -ENOMEM; + } +#endif + /* Create Platform MSI domain */ imsic->plat_domain = platform_msi_create_irq_domain(fwnode, &imsic_plat_domain_info, imsic->base_domain); if (!imsic->plat_domain) { pr_err("Failed to create IMSIC platform domain\n"); + if (imsic->pci_domain) + irq_domain_remove(imsic->pci_domain); irq_domain_remove(imsic->base_domain); return -ENOMEM; } -- 2.34.1