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From: Andrew Jones <ajones@ventanamicro.com>
To: Anup Patel <apatel@ventanamicro.com>
Cc: Palmer Dabbelt <palmer@dabbelt.com>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	Thomas Gleixner <tglx@linutronix.de>,
	Marc Zyngier <maz@kernel.org>, Rob Herring <robh+dt@kernel.org>,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
	Atish Patra <atishp@atishpatra.org>,
	Sunil V L <sunilvl@ventanamicro.com>,
	Conor Dooley <conor@kernel.org>,
	Saravana Kannan <saravanak@google.com>,
	Anup Patel <anup@brainfault.org>,
	linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
	devicetree@vger.kernel.org
Subject: Re: [PATCH v5 1/9] RISC-V: Add riscv_fw_parent_hartid() function
Date: Tue, 11 Jul 2023 15:26:12 +0200	[thread overview]
Message-ID: <20230711-3151a76400deb88b218e9f9b@orel> (raw)
In-Reply-To: <20230710094321.1378351-2-apatel@ventanamicro.com>

On Mon, Jul 10, 2023 at 03:13:13PM +0530, Anup Patel wrote:
> We add common riscv_fw_parent_hartid() which help device drivers
> to get parent hartid of the INTC (i.e. local interrupt controller)
> fwnode. This should work for both DT and ACPI.
> 
> Signed-off-by: Anup Patel <apatel@ventanamicro.com>
> ---
>  arch/riscv/include/asm/processor.h |  3 +++
>  arch/riscv/kernel/cpu.c            | 16 ++++++++++++++++
>  2 files changed, 19 insertions(+)
> 
> diff --git a/arch/riscv/include/asm/processor.h b/arch/riscv/include/asm/processor.h
> index c950a8d9edef..39dc23a18f88 100644
> --- a/arch/riscv/include/asm/processor.h
> +++ b/arch/riscv/include/asm/processor.h
> @@ -81,6 +81,9 @@ int riscv_of_processor_hartid(struct device_node *node, unsigned long *hartid);
>  int riscv_early_of_processor_hartid(struct device_node *node, unsigned long *hartid);
>  int riscv_of_parent_hartid(struct device_node *node, unsigned long *hartid);
>  
> +struct fwnode_handle;
> +int riscv_fw_parent_hartid(struct fwnode_handle *node, unsigned long *hartid);
> +
>  extern void riscv_fill_hwcap(void);
>  extern int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src);
>  
> diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c
> index a2fc952318e9..9be9b3b1f333 100644
> --- a/arch/riscv/kernel/cpu.c
> +++ b/arch/riscv/kernel/cpu.c
> @@ -96,6 +96,22 @@ int riscv_of_parent_hartid(struct device_node *node, unsigned long *hartid)
>  	return -1;
>  }
>  
> +/* Find hart ID of the CPU fwnode under which given fwnode falls. */

This comment matches the comment for riscv_of_parent_hartid(), but I don't
think it will be correct for the !is_of_node(node) case since
fwnode_property_read_u64_array() isn't obliged to walk up its tree.
Looking ahead it appears riscv_fw_parent_hartid() is only called with the
parent node, so we could just drop this function and use
fwnode_property_read_u64_array() directly at the two call sites.

Thanks,
drew

> +int riscv_fw_parent_hartid(struct fwnode_handle *node, unsigned long *hartid)
> +{
> +	int rc;
> +	u64 temp;
> +
> +	if (!is_of_node(node)) {
> +		rc = fwnode_property_read_u64_array(node, "hartid", &temp, 1);
> +		if (!rc)
> +			*hartid = temp;
> +	} else
> +		rc = riscv_of_parent_hartid(to_of_node(node), hartid);
> +
> +	return rc;
> +}
> +
>  DEFINE_PER_CPU(struct riscv_cpuinfo, riscv_cpuinfo);
>  
>  unsigned long riscv_cached_mvendorid(unsigned int cpu_id)
> -- 
> 2.34.1
> 

  reply	other threads:[~2023-07-11 13:26 UTC|newest]

Thread overview: 23+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-07-10  9:43 [PATCH v5 0/9] Linux RISC-V AIA Support Anup Patel
2023-07-10  9:43 ` [PATCH v5 1/9] RISC-V: Add riscv_fw_parent_hartid() function Anup Patel
2023-07-11 13:26   ` Andrew Jones [this message]
2023-07-17  5:04     ` Anup Patel
2023-07-10  9:43 ` [PATCH v5 2/9] irqchip/riscv-intc: Add support for RISC-V AIA Anup Patel
2023-07-11 14:12   ` Andrew Jones
2023-07-17  6:38     ` Anup Patel
2023-07-10  9:43 ` [PATCH v5 3/9] dt-bindings: interrupt-controller: Add RISC-V incoming MSI controller Anup Patel
2023-07-10  9:43 ` [PATCH v5 4/9] irqchip: Add RISC-V incoming MSI controller driver Anup Patel
2023-07-10  9:43 ` [PATCH v5 5/9] irqchip/riscv-imsic: Add support for PCI MSI irqdomain Anup Patel
2023-07-10  9:43 ` [PATCH v5 6/9] dt-bindings: interrupt-controller: Add RISC-V advanced PLIC Anup Patel
2023-07-10  9:43 ` [PATCH v5 7/9] irqchip: Add RISC-V advanced PLIC driver Anup Patel
2023-07-13 23:56   ` Saravana Kannan
2023-07-14  9:01     ` Marc Zyngier
2023-07-14  9:35       ` Anup Patel
2023-07-14 13:35         ` Marc Zyngier
2023-07-14 14:05           ` Anup Patel
2023-07-17  8:05             ` Marc Zyngier
2023-07-17  9:05               ` Anup Patel
2023-07-17  9:36                 ` Anup Patel
2023-07-17  9:48                 ` Marc Zyngier
2023-07-10  9:43 ` [PATCH v5 8/9] RISC-V: Select APLIC and IMSIC drivers Anup Patel
2023-07-10  9:43 ` [PATCH v5 9/9] MAINTAINERS: Add entry for RISC-V AIA drivers Anup Patel

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