From: Conor Dooley <conor.dooley@microchip.com>
To: <palmer@dabbelt.com>
Cc: <conor@kernel.org>, <conor.dooley@microchip.com>,
Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Paul Walmsley <paul.walmsley@sifive.com>,
Albert Ou <aou@eecs.berkeley.edu>,
"Jonathan Corbet" <corbet@lwn.net>,
Andrew Jones <ajones@ventanamicro.com>,
"Heiko Stuebner" <heiko.stuebner@vrull.eu>,
Evan Green <evan@rivosinc.com>,
Sunil V L <sunilvl@ventanamicro.com>, <linux-doc@vger.kernel.org>,
<linux-riscv@lists.infradead.org>, <devicetree@vger.kernel.org>,
<linux-kernel@vger.kernel.org>
Subject: [PATCH v5 06/11] RISC-V: add missing single letter extension definitions
Date: Thu, 13 Jul 2023 13:11:04 +0100 [thread overview]
Message-ID: <20230713-train-feisty-93de38250f98@wendy> (raw)
In-Reply-To: <20230713-target-much-8ac624e90df8@wendy>
To facilitate adding single letter extensions to riscv_isa_ext, add
definitions for the extensions present in base_riscv_exts that do not
already have them.
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Evan Green <evan@rivosinc.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
arch/riscv/include/asm/hwcap.h | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h
index 2460ac2fc7ed..a20e4ade1b53 100644
--- a/arch/riscv/include/asm/hwcap.h
+++ b/arch/riscv/include/asm/hwcap.h
@@ -14,12 +14,17 @@
#include <uapi/asm/hwcap.h>
#define RISCV_ISA_EXT_a ('a' - 'a')
+#define RISCV_ISA_EXT_b ('b' - 'a')
#define RISCV_ISA_EXT_c ('c' - 'a')
#define RISCV_ISA_EXT_d ('d' - 'a')
#define RISCV_ISA_EXT_f ('f' - 'a')
#define RISCV_ISA_EXT_h ('h' - 'a')
#define RISCV_ISA_EXT_i ('i' - 'a')
+#define RISCV_ISA_EXT_j ('j' - 'a')
+#define RISCV_ISA_EXT_k ('k' - 'a')
#define RISCV_ISA_EXT_m ('m' - 'a')
+#define RISCV_ISA_EXT_p ('p' - 'a')
+#define RISCV_ISA_EXT_q ('q' - 'a')
#define RISCV_ISA_EXT_s ('s' - 'a')
#define RISCV_ISA_EXT_u ('u' - 'a')
#define RISCV_ISA_EXT_v ('v' - 'a')
--
2.40.1
next prev parent reply other threads:[~2023-07-13 12:13 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-07-13 12:10 [PATCH v5 00/11] RISC-V: Probe DT extension support using riscv,isa-extensions & riscv,isa-base Conor Dooley
2023-07-13 12:10 ` [PATCH v5 01/11] RISC-V: Provide a more helpful error message on invalid ISA strings Conor Dooley
2023-07-13 12:11 ` [PATCH v5 02/11] RISC-V: don't parse dt/acpi isa string to get rv32/rv64 Conor Dooley
2023-07-13 12:11 ` [PATCH v5 03/11] RISC-V: drop a needless check in print_isa_ext() Conor Dooley
2023-07-13 12:11 ` [PATCH v5 04/11] RISC-V: shunt isa_ext_arr to cpufeature.c Conor Dooley
2023-07-13 12:11 ` [PATCH v5 05/11] RISC-V: repurpose riscv_isa_ext array in riscv_fill_hwcap() Conor Dooley
2023-07-13 12:11 ` Conor Dooley [this message]
2023-07-13 12:11 ` [PATCH v5 07/11] RISC-V: add single letter extensions to riscv_isa_ext Conor Dooley
2023-07-13 12:11 ` [PATCH v5 08/11] RISC-V: split riscv_fill_hwcap() in 3 Conor Dooley
2023-07-13 12:11 ` [PATCH v5 09/11] RISC-V: enable extension detection from dedicated properties Conor Dooley
2023-07-13 12:11 ` [PATCH v5 10/11] RISC-V: try new extension properties in of_early_processor_hartid() Conor Dooley
2023-07-13 12:11 ` [PATCH v5 11/11] RISC-V: provide Kconfig & commandline options to control parsing "riscv,isa" Conor Dooley
2023-08-09 14:20 ` [PATCH v5 00/11] RISC-V: Probe DT extension support using riscv,isa-extensions & riscv,isa-base patchwork-bot+linux-riscv
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