* [PATCH v1 0/2] RK3588 PCIe3 support @ 2023-07-14 17:53 Sebastian Reichel 2023-07-14 17:53 ` [PATCH v1 1/2] dt-bindings: phy: rockchip: add RK3588 PCIe v3 phy Sebastian Reichel 2023-07-14 17:53 ` [PATCH v1 2/2] arm64: dts: rockchip: rk3588: add PCIe3 support Sebastian Reichel 0 siblings, 2 replies; 5+ messages in thread From: Sebastian Reichel @ 2023-07-14 17:53 UTC (permalink / raw) To: linux-phy, linux-rockchip Cc: Jingoo Han, Gustavo Pimentel, Bjorn Helgaas, Lorenzo Pieralisi, Vinod Koul, Kishon Vijay Abraham I, Krzysztof Wilczyński, Rob Herring, Serge Semin, Krzysztof Kozlowski, Conor Dooley, Heiko Stuebner, Shawn Lin, Simon Xue, John Clark, Qu Wenruo, devicetree, linux-pci, linux-kernel, linux-arm-kernel, Sebastian Reichel, kernel Hi, This adds PCIe v3 support for RK3588. The series has been tested with Rockchip RK3588 EVB1 and a PCIe wlan card, I will also test Rock 5B next week. The series depends on the PCIe v2 series [0]. Note, that the PCIe3 PHY driver is currently missing bifurcation support for RK3588. Thus after this series only PCIe3x4 is usable (in aggregated x4 mode) without adding support for the PHY's "rockchip,pcie30-phymode" DT property, which allows configuring how the lanes are distributed. Apparently this seems to be the most common configuration. Both EVB1 and Rock 5B use it, so I cannot test anything else anyways. [0] https://lore.kernel.org/all/20230713171851.73052-1-sebastian.reichel@collabora.com/ -- Sebastian Sebastian Reichel (2): dt-bindings: phy: rockchip: add RK3588 PCIe v3 phy arm64: dts: rockchip: rk3588: add PCIe3 support .../bindings/phy/rockchip,pcie3-phy.yaml | 33 ++++- arch/arm64/boot/dts/rockchip/rk3588.dtsi | 128 ++++++++++++++++++ 2 files changed, 156 insertions(+), 5 deletions(-) -- 2.40.1 ^ permalink raw reply [flat|nested] 5+ messages in thread
* [PATCH v1 1/2] dt-bindings: phy: rockchip: add RK3588 PCIe v3 phy 2023-07-14 17:53 [PATCH v1 0/2] RK3588 PCIe3 support Sebastian Reichel @ 2023-07-14 17:53 ` Sebastian Reichel 2023-07-15 10:29 ` Conor Dooley 2023-07-14 17:53 ` [PATCH v1 2/2] arm64: dts: rockchip: rk3588: add PCIe3 support Sebastian Reichel 1 sibling, 1 reply; 5+ messages in thread From: Sebastian Reichel @ 2023-07-14 17:53 UTC (permalink / raw) To: linux-phy, linux-rockchip Cc: Jingoo Han, Gustavo Pimentel, Bjorn Helgaas, Lorenzo Pieralisi, Vinod Koul, Kishon Vijay Abraham I, Krzysztof Wilczyński, Rob Herring, Serge Semin, Krzysztof Kozlowski, Conor Dooley, Heiko Stuebner, Shawn Lin, Simon Xue, John Clark, Qu Wenruo, devicetree, linux-pci, linux-kernel, linux-arm-kernel, Sebastian Reichel, kernel When the RK3568 PCIe v3 PHY supported has been upstreamed, RK3588 support was included, but the DT binding does not reflect this. This adds the missing bits. Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com> --- .../bindings/phy/rockchip,pcie3-phy.yaml | 33 ++++++++++++++++--- 1 file changed, 28 insertions(+), 5 deletions(-) diff --git a/Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.yaml b/Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.yaml index 9f2d8d2cc7a5..c4fbffcde6e4 100644 --- a/Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.yaml +++ b/Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.yaml @@ -13,19 +13,18 @@ properties: compatible: enum: - rockchip,rk3568-pcie3-phy + - rockchip,rk3588-pcie3-phy reg: maxItems: 1 clocks: - minItems: 3 + minItems: 1 maxItems: 3 clock-names: - items: - - const: refclk_m - - const: refclk_n - - const: pclk + minItems: 1 + maxItems: 3 data-lanes: description: which lanes (by position) should be mapped to which @@ -61,6 +60,30 @@ required: - rockchip,phy-grf - "#phy-cells" +allOf: + - if: + properties: + compatible: + enum: + - rockchip,rk3588-pcie3-phy + then: + properties: + clocks: + maxItems: 1 + clock-names: + items: + - const: pclk + else: + properties: + clocks: + minItems: 3 + + clock-names: + items: + - const: refclk_m + - const: refclk_n + - const: pclk + additionalProperties: false examples: -- 2.40.1 ^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [PATCH v1 1/2] dt-bindings: phy: rockchip: add RK3588 PCIe v3 phy 2023-07-14 17:53 ` [PATCH v1 1/2] dt-bindings: phy: rockchip: add RK3588 PCIe v3 phy Sebastian Reichel @ 2023-07-15 10:29 ` Conor Dooley 0 siblings, 0 replies; 5+ messages in thread From: Conor Dooley @ 2023-07-15 10:29 UTC (permalink / raw) To: Sebastian Reichel Cc: linux-phy, linux-rockchip, Jingoo Han, Gustavo Pimentel, Bjorn Helgaas, Lorenzo Pieralisi, Vinod Koul, Kishon Vijay Abraham I, Krzysztof Wilczyński, Rob Herring, Serge Semin, Krzysztof Kozlowski, Conor Dooley, Heiko Stuebner, Shawn Lin, Simon Xue, John Clark, Qu Wenruo, devicetree, linux-pci, linux-kernel, linux-arm-kernel, kernel [-- Attachment #1: Type: text/plain, Size: 316 bytes --] On Fri, Jul 14, 2023 at 07:53:30PM +0200, Sebastian Reichel wrote: > When the RK3568 PCIe v3 PHY supported has been upstreamed, RK3588 > support was included, but the DT binding does not reflect this. > This adds the missing bits. Thanks for rectifying that! Reviewed-by: Conor Dooley <conor.dooley@microchip.com> [-- Attachment #2: signature.asc --] [-- Type: application/pgp-signature, Size: 228 bytes --] ^ permalink raw reply [flat|nested] 5+ messages in thread
* [PATCH v1 2/2] arm64: dts: rockchip: rk3588: add PCIe3 support 2023-07-14 17:53 [PATCH v1 0/2] RK3588 PCIe3 support Sebastian Reichel 2023-07-14 17:53 ` [PATCH v1 1/2] dt-bindings: phy: rockchip: add RK3588 PCIe v3 phy Sebastian Reichel @ 2023-07-14 17:53 ` Sebastian Reichel 2023-07-15 16:45 ` Serge Semin 1 sibling, 1 reply; 5+ messages in thread From: Sebastian Reichel @ 2023-07-14 17:53 UTC (permalink / raw) To: linux-phy, linux-rockchip Cc: Jingoo Han, Gustavo Pimentel, Bjorn Helgaas, Lorenzo Pieralisi, Vinod Koul, Kishon Vijay Abraham I, Krzysztof Wilczyński, Rob Herring, Serge Semin, Krzysztof Kozlowski, Conor Dooley, Heiko Stuebner, Shawn Lin, Simon Xue, John Clark, Qu Wenruo, devicetree, linux-pci, linux-kernel, linux-arm-kernel, Sebastian Reichel, kernel Add both PCIe3 controllers together with the shared PHY. Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com> --- arch/arm64/boot/dts/rockchip/rk3588.dtsi | 128 +++++++++++++++++++++++ 1 file changed, 128 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588.dtsi b/arch/arm64/boot/dts/rockchip/rk3588.dtsi index 4d66ca6c2e4c..af6f52afbaff 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588.dtsi @@ -7,6 +7,11 @@ #include "rk3588-pinctrl.dtsi" / { + pcie30_phy_grf: syscon@fd5b8000 { + compatible = "rockchip,rk3588-pcie3-phy-grf", "syscon"; + reg = <0x0 0xfd5b8000 0x0 0x10000>; + }; + pipe_phy1_grf: syscon@fd5c0000 { compatible = "rockchip,rk3588-pipe-phy-grf", "syscon"; reg = <0x0 0xfd5c0000 0x0 0x100>; @@ -80,6 +85,116 @@ i2s10_8ch: i2s@fde00000 { status = "disabled"; }; + pcie3x4: pcie@fe150000 { + compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie"; + #address-cells = <3>; + #size-cells = <2>; + bus-range = <0x00 0x0f>; + clocks = <&cru ACLK_PCIE_4L_MSTR>, <&cru ACLK_PCIE_4L_SLV>, + <&cru ACLK_PCIE_4L_DBI>, <&cru PCLK_PCIE_4L>, + <&cru CLK_PCIE_AUX0>, <&cru CLK_PCIE4L_PIPE>; + clock-names = "aclk_mst", "aclk_slv", + "aclk_dbi", "pclk", + "aux", "pipe"; + device_type = "pci"; + interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH 0>; + interrupt-names = "sys", "pmc", "msg", "legacy", "err"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie3x4_intc 0>, + <0 0 0 2 &pcie3x4_intc 1>, + <0 0 0 3 &pcie3x4_intc 2>, + <0 0 0 4 &pcie3x4_intc 3>; + linux,pci-domain = <0>; + num-ib-windows = <16>; + num-ob-windows = <16>; + num-viewport = <8>; + max-link-speed = <3>; + msi-map = <0x0000 &its1 0x0000 0x1000>; + num-lanes = <4>; + phys = <&pcie30phy>; + phy-names = "pcie-phy"; + power-domains = <&power RK3588_PD_PCIE>; + ranges = <0x01000000 0x0 0xf0100000 0x0 0xf0100000 0x0 0x00100000>, + <0x02000000 0x0 0xf0200000 0x0 0xf0200000 0x0 0x00e00000>, + <0x03000000 0x0 0x40000000 0x9 0x00000000 0x0 0x40000000>; + reg = <0xa 0x40000000 0x0 0x00400000>, + <0x0 0xfe150000 0x0 0x00010000>, + <0x0 0xf0000000 0x0 0x00100000>; + reg-names = "dbi", "apb", "config"; + resets = <&cru SRST_PCIE0_POWER_UP>, <&cru SRST_P_PCIE0>; + reset-names = "pwr", "pipe"; + rockchip,pipe-grf = <&php_grf>; + status = "disabled"; + + pcie3x4_intc: legacy-interrupt-controller { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-parent = <&gic>; + interrupts = <GIC_SPI 260 IRQ_TYPE_EDGE_RISING 0>; + }; + }; + + pcie3x2: pcie@fe160000 { + compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie"; + #address-cells = <3>; + #size-cells = <2>; + bus-range = <0x10 0x1f>; + clocks = <&cru ACLK_PCIE_2L_MSTR>, <&cru ACLK_PCIE_2L_SLV>, + <&cru ACLK_PCIE_2L_DBI>, <&cru PCLK_PCIE_2L>, + <&cru CLK_PCIE_AUX1>, <&cru CLK_PCIE2L_PIPE>; + clock-names = "aclk_mst", "aclk_slv", + "aclk_dbi", "pclk", + "aux", "pipe"; + device_type = "pci"; + interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH 0>; + interrupt-names = "sys", "pmc", "msg", "legacy", "err"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie3x2_intc 0>, + <0 0 0 2 &pcie3x2_intc 1>, + <0 0 0 3 &pcie3x2_intc 2>, + <0 0 0 4 &pcie3x2_intc 3>; + linux,pci-domain = <1>; + num-ib-windows = <16>; + num-ob-windows = <16>; + num-viewport = <8>; + max-link-speed = <3>; + msi-map = <0x1000 &its1 0x1000 0x1000>; + num-lanes = <2>; + phys = <&pcie30phy>; + phy-names = "pcie-phy"; + power-domains = <&power RK3588_PD_PCIE>; + ranges = <0x01000000 0x0 0xf1100000 0x0 0xf1100000 0x0 0x00100000>, + <0x02000000 0x0 0xf1200000 0x0 0xf1200000 0x0 0x00e00000>, + <0x03000000 0x0 0x40000000 0x9 0x40000000 0x0 0x40000000>; + reg = <0xa 0x40400000 0x0 0x00400000>, + <0x0 0xfe160000 0x0 0x00010000>, + <0x0 0xf1000000 0x0 0x00100000>; + reg-names = "dbi", "apb", "config"; + resets = <&cru SRST_PCIE1_POWER_UP>, <&cru SRST_P_PCIE1>; + reset-names = "pwr", "pipe"; + rockchip,pipe-grf = <&php_grf>; + status = "disabled"; + + pcie3x2_intc: legacy-interrupt-controller { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-parent = <&gic>; + interrupts = <GIC_SPI 255 IRQ_TYPE_EDGE_RISING 0>; + }; + }; + pcie2x1l0: pcie@fe170000 { compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie"; #address-cells = <3>; @@ -221,4 +336,17 @@ combphy1_ps: phy@fee10000 { rockchip,pipe-phy-grf = <&pipe_phy1_grf>; status = "disabled"; }; + + pcie30phy: phy@fee80000 { + compatible = "rockchip,rk3588-pcie3-phy"; + reg = <0x0 0xfee80000 0x0 0x20000>; + #phy-cells = <0>; + clocks = <&cru PCLK_PCIE_COMBO_PIPE_PHY>; + clock-names = "pclk"; + resets = <&cru SRST_PCIE30_PHY>; + reset-names = "phy"; + rockchip,pipe-grf = <&php_grf>; + rockchip,phy-grf = <&pcie30_phy_grf>; + status = "disabled"; + }; }; -- 2.40.1 ^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [PATCH v1 2/2] arm64: dts: rockchip: rk3588: add PCIe3 support 2023-07-14 17:53 ` [PATCH v1 2/2] arm64: dts: rockchip: rk3588: add PCIe3 support Sebastian Reichel @ 2023-07-15 16:45 ` Serge Semin 0 siblings, 0 replies; 5+ messages in thread From: Serge Semin @ 2023-07-15 16:45 UTC (permalink / raw) To: Sebastian Reichel Cc: linux-phy, linux-rockchip, Jingoo Han, Gustavo Pimentel, Bjorn Helgaas, Lorenzo Pieralisi, Vinod Koul, Kishon Vijay Abraham I, Krzysztof Wilczyński, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Heiko Stuebner, Shawn Lin, Simon Xue, John Clark, Qu Wenruo, devicetree, linux-pci, linux-kernel, linux-arm-kernel, kernel On Fri, Jul 14, 2023 at 07:53:31PM +0200, Sebastian Reichel wrote: > Add both PCIe3 controllers together with the shared PHY. > > Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com> > --- > arch/arm64/boot/dts/rockchip/rk3588.dtsi | 128 +++++++++++++++++++++++ > 1 file changed, 128 insertions(+) > > diff --git a/arch/arm64/boot/dts/rockchip/rk3588.dtsi b/arch/arm64/boot/dts/rockchip/rk3588.dtsi > index 4d66ca6c2e4c..af6f52afbaff 100644 > --- a/arch/arm64/boot/dts/rockchip/rk3588.dtsi > +++ b/arch/arm64/boot/dts/rockchip/rk3588.dtsi > @@ -7,6 +7,11 @@ > #include "rk3588-pinctrl.dtsi" > > / { > + pcie30_phy_grf: syscon@fd5b8000 { > + compatible = "rockchip,rk3588-pcie3-phy-grf", "syscon"; > + reg = <0x0 0xfd5b8000 0x0 0x10000>; > + }; > + > pipe_phy1_grf: syscon@fd5c0000 { > compatible = "rockchip,rk3588-pipe-phy-grf", "syscon"; > reg = <0x0 0xfd5c0000 0x0 0x100>; > @@ -80,6 +85,116 @@ i2s10_8ch: i2s@fde00000 { > status = "disabled"; > }; > > + pcie3x4: pcie@fe150000 { > + compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie"; > + #address-cells = <3>; > + #size-cells = <2>; > + bus-range = <0x00 0x0f>; > + clocks = <&cru ACLK_PCIE_4L_MSTR>, <&cru ACLK_PCIE_4L_SLV>, > + <&cru ACLK_PCIE_4L_DBI>, <&cru PCLK_PCIE_4L>, > + <&cru CLK_PCIE_AUX0>, <&cru CLK_PCIE4L_PIPE>; > + clock-names = "aclk_mst", "aclk_slv", > + "aclk_dbi", "pclk", > + "aux", "pipe"; > + device_type = "pci"; > + interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH 0>, > + <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH 0>, > + <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH 0>, > + <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH 0>, > + <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH 0>; > + interrupt-names = "sys", "pmc", "msg", "legacy", "err"; > + #interrupt-cells = <1>; > + interrupt-map-mask = <0 0 0 7>; > + interrupt-map = <0 0 0 1 &pcie3x4_intc 0>, > + <0 0 0 2 &pcie3x4_intc 1>, > + <0 0 0 3 &pcie3x4_intc 2>, > + <0 0 0 4 &pcie3x4_intc 3>; > + linux,pci-domain = <0>; > + num-ib-windows = <16>; > + num-ob-windows = <16>; > + num-viewport = <8>; These are marked as deprecated in the bindings and unused by the driver anyway. The DW PCIe core driver auto-detects a number of available iATU memory windows. So you can freely drop these properties. > + max-link-speed = <3>; > + msi-map = <0x0000 &its1 0x0000 0x1000>; > + num-lanes = <4>; > + phys = <&pcie30phy>; > + phy-names = "pcie-phy"; > + power-domains = <&power RK3588_PD_PCIE>; > + ranges = <0x01000000 0x0 0xf0100000 0x0 0xf0100000 0x0 0x00100000>, > + <0x02000000 0x0 0xf0200000 0x0 0xf0200000 0x0 0x00e00000>, > + <0x03000000 0x0 0x40000000 0x9 0x00000000 0x0 0x40000000>; > + reg = <0xa 0x40000000 0x0 0x00400000>, > + <0x0 0xfe150000 0x0 0x00010000>, > + <0x0 0xf0000000 0x0 0x00100000>; > + reg-names = "dbi", "apb", "config"; > + resets = <&cru SRST_PCIE0_POWER_UP>, <&cru SRST_P_PCIE0>; > + reset-names = "pwr", "pipe"; > + rockchip,pipe-grf = <&php_grf>; > + status = "disabled"; > + > + pcie3x4_intc: legacy-interrupt-controller { > + interrupt-controller; > + #address-cells = <0>; > + #interrupt-cells = <1>; > + interrupt-parent = <&gic>; > + interrupts = <GIC_SPI 260 IRQ_TYPE_EDGE_RISING 0>; > + }; > + }; > + > + pcie3x2: pcie@fe160000 { > + compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie"; > + #address-cells = <3>; > + #size-cells = <2>; > + bus-range = <0x10 0x1f>; > + clocks = <&cru ACLK_PCIE_2L_MSTR>, <&cru ACLK_PCIE_2L_SLV>, > + <&cru ACLK_PCIE_2L_DBI>, <&cru PCLK_PCIE_2L>, > + <&cru CLK_PCIE_AUX1>, <&cru CLK_PCIE2L_PIPE>; > + clock-names = "aclk_mst", "aclk_slv", > + "aclk_dbi", "pclk", > + "aux", "pipe"; > + device_type = "pci"; > + interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH 0>, > + <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH 0>, > + <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH 0>, > + <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH 0>, > + <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH 0>; > + interrupt-names = "sys", "pmc", "msg", "legacy", "err"; > + #interrupt-cells = <1>; > + interrupt-map-mask = <0 0 0 7>; > + interrupt-map = <0 0 0 1 &pcie3x2_intc 0>, > + <0 0 0 2 &pcie3x2_intc 1>, > + <0 0 0 3 &pcie3x2_intc 2>, > + <0 0 0 4 &pcie3x2_intc 3>; > + linux,pci-domain = <1>; > + num-ib-windows = <16>; > + num-ob-windows = <16>; > + num-viewport = <8>; ditto -Serge(y) > + max-link-speed = <3>; > + msi-map = <0x1000 &its1 0x1000 0x1000>; > + num-lanes = <2>; > + phys = <&pcie30phy>; > + phy-names = "pcie-phy"; > + power-domains = <&power RK3588_PD_PCIE>; > + ranges = <0x01000000 0x0 0xf1100000 0x0 0xf1100000 0x0 0x00100000>, > + <0x02000000 0x0 0xf1200000 0x0 0xf1200000 0x0 0x00e00000>, > + <0x03000000 0x0 0x40000000 0x9 0x40000000 0x0 0x40000000>; > + reg = <0xa 0x40400000 0x0 0x00400000>, > + <0x0 0xfe160000 0x0 0x00010000>, > + <0x0 0xf1000000 0x0 0x00100000>; > + reg-names = "dbi", "apb", "config"; > + resets = <&cru SRST_PCIE1_POWER_UP>, <&cru SRST_P_PCIE1>; > + reset-names = "pwr", "pipe"; > + rockchip,pipe-grf = <&php_grf>; > + status = "disabled"; > + > + pcie3x2_intc: legacy-interrupt-controller { > + interrupt-controller; > + #address-cells = <0>; > + #interrupt-cells = <1>; > + interrupt-parent = <&gic>; > + interrupts = <GIC_SPI 255 IRQ_TYPE_EDGE_RISING 0>; > + }; > + }; > + > pcie2x1l0: pcie@fe170000 { > compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie"; > #address-cells = <3>; > @@ -221,4 +336,17 @@ combphy1_ps: phy@fee10000 { > rockchip,pipe-phy-grf = <&pipe_phy1_grf>; > status = "disabled"; > }; > + > + pcie30phy: phy@fee80000 { > + compatible = "rockchip,rk3588-pcie3-phy"; > + reg = <0x0 0xfee80000 0x0 0x20000>; > + #phy-cells = <0>; > + clocks = <&cru PCLK_PCIE_COMBO_PIPE_PHY>; > + clock-names = "pclk"; > + resets = <&cru SRST_PCIE30_PHY>; > + reset-names = "phy"; > + rockchip,pipe-grf = <&php_grf>; > + rockchip,phy-grf = <&pcie30_phy_grf>; > + status = "disabled"; > + }; > }; > -- > 2.40.1 > ^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2023-07-15 16:45 UTC | newest] Thread overview: 5+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2023-07-14 17:53 [PATCH v1 0/2] RK3588 PCIe3 support Sebastian Reichel 2023-07-14 17:53 ` [PATCH v1 1/2] dt-bindings: phy: rockchip: add RK3588 PCIe v3 phy Sebastian Reichel 2023-07-15 10:29 ` Conor Dooley 2023-07-14 17:53 ` [PATCH v1 2/2] arm64: dts: rockchip: rk3588: add PCIe3 support Sebastian Reichel 2023-07-15 16:45 ` Serge Semin
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