From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id EEC72C001DC for ; Tue, 18 Jul 2023 15:50:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232016AbjGRPuc (ORCPT ); Tue, 18 Jul 2023 11:50:32 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46116 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230118AbjGRPub (ORCPT ); Tue, 18 Jul 2023 11:50:31 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [IPv6:2604:1380:4641:c500::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E51909E; Tue, 18 Jul 2023 08:50:30 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 7BB0C61636; Tue, 18 Jul 2023 15:50:30 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 70CAFC433C7; Tue, 18 Jul 2023 15:50:26 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1689695429; bh=KpsXoGNT24bqVK2j4V39yYPHPZAehW1pBCGywyhhsZg=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=SCl6VUf09aCm8F9Rfutn6Uxx1jy2IXKPwVbDgKNy1lsByW8D863kBj34wgk2UM72g w1xJ/miCw6e0jHG1v+nv0PesQByoe+ygDO+uaGUl+kT4/oEjpu6XOk+GxaC62yj2w2 qs7NCOmvby5/koQcOlOhHApH2sSLLpn00WWDYn/nDZtrbaBjuLcGQhZmI4lDlx9K53 X4Fcw0U+zDJziRGp16VQoMWxMlfRhX58qqZOJHenzUSABwl9YUTj8/hKREuQhVvQE+ rX5T4SeYeY9ajqhE3J91401ueoMDUuNLRkXoDiN9RNmE8cXFbRcdg7MC5DZvuuxLLI VoIHsZ564kXNg== Date: Tue, 18 Jul 2023 16:50:24 +0100 From: Conor Dooley To: Sai Krishna Potthuri Cc: Linus Walleij , Michal Simek , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Mathieu Poirier , Tanmay Shah , Ben Levinsky , Marek Vasut , Roman Gushchin , Arnd Bergmann , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, saikrishna12468@gmail.com, git@amd.com Subject: Re: [PATCH 3/4] dt-bindings: pinctrl-zynqmp: Add output-enable configuration Message-ID: <20230718-jitters-excretion-fe18c820c102@spud> References: <20230717093347.3869167-1-sai.krishna.potthuri@amd.com> <20230717093347.3869167-4-sai.krishna.potthuri@amd.com> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="hrxtH0ql+XfVls6Z" Content-Disposition: inline In-Reply-To: <20230717093347.3869167-4-sai.krishna.potthuri@amd.com> Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org --hrxtH0ql+XfVls6Z Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Mon, Jul 17, 2023 at 03:03:46PM +0530, Sai Krishna Potthuri wrote: > Add 'output-enable' configuration parameter to the properties list. >=20 > Using these pinctrl properties observed hang issues with older Xilinx > ZynqMP Platform Management Firmware, hence reverted the patch previously. > Commit ff8356060e3a5e126abb ("Revert "dt-bindings: pinctrl-zynqmp: Add > output-enable configuration""). And what has changed since then that makes it okay to add? Is the old firmware not still in the wild? Thanks, Conor. >=20 > Signed-off-by: Sai Krishna Potthuri > --- > .../devicetree/bindings/pinctrl/xlnx,zynqmp-pinctrl.yaml | 4 ++++ > 1 file changed, 4 insertions(+) >=20 > diff --git a/Documentation/devicetree/bindings/pinctrl/xlnx,zynqmp-pinctr= l.yaml b/Documentation/devicetree/bindings/pinctrl/xlnx,zynqmp-pinctrl.yaml > index 2722dc7bb03d..1e2b9b627b12 100644 > --- a/Documentation/devicetree/bindings/pinctrl/xlnx,zynqmp-pinctrl.yaml > +++ b/Documentation/devicetree/bindings/pinctrl/xlnx,zynqmp-pinctrl.yaml > @@ -274,6 +274,10 @@ patternProperties: > slew-rate: > enum: [0, 1] > =20 > + output-enable: > + description: > + This will internally disable the tri-state for MIO pins. > + > drive-strength: > description: > Selects the drive strength for MIO pins, in mA. > --=20 > 2.25.1 >=20 --hrxtH0ql+XfVls6Z Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iHUEABYIAB0WIQRh246EGq/8RLhDjO14tDGHoIJi0gUCZLa0wAAKCRB4tDGHoIJi 0oQHAPwLbzoQrcII+jPHwQtJ8XLVTtNNrYqRLQBk6RwGQUphugD/Q638arUQoo1g cyV6Ef/POblzZqSX0Xj0V4XLt9Klswc= =ANB1 -----END PGP SIGNATURE----- --hrxtH0ql+XfVls6Z--