From: Meng Li <Meng.Li@windriver.com>
To: dinguyen@kernel.org, robh+dt@kernel.org,
krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org,
devicetree@vger.kernel.org
Cc: linux-kernel@vger.kernel.org, meng.li@windriver.com
Subject: [PATCH] usb: dwc2: add new compatible for Intel SoCFPGA Stratix10 platform
Date: Tue, 18 Jul 2023 11:08:51 +0800 [thread overview]
Message-ID: <20230718030851.2014306-1-Meng.Li@windriver.com> (raw)
Intel Stratix10 is very the same with Agilex platform, the DWC2 IP on
the Stratix platform also does not support clock-gating. The commit
3d8d3504d233("usb: dwc2: Add platform specific data for Intel's Agilex")
had fixed this issue. So, add the essential compatible to also use the
specific data on Stratix10 platform.
Signed-off-by: Meng Li <Meng.Li@windriver.com>
---
arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
index ea788a920eab..b8dd5509c214 100644
--- a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
+++ b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
@@ -490,7 +490,7 @@ usbphy0: usbphy@0 {
};
usb0: usb@ffb00000 {
- compatible = "snps,dwc2";
+ compatible = "intel,socfpga-agilex-hsotg", "snps,dwc2";
reg = <0xffb00000 0x40000>;
interrupts = <0 93 4>;
phys = <&usbphy0>;
@@ -504,7 +504,7 @@ usb0: usb@ffb00000 {
};
usb1: usb@ffb40000 {
- compatible = "snps,dwc2";
+ compatible = "intel,socfpga-agilex-hsotg", "snps,dwc2";
reg = <0xffb40000 0x40000>;
interrupts = <0 94 4>;
phys = <&usbphy0>;
--
2.34.1
next reply other threads:[~2023-07-18 3:09 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-07-18 3:08 Meng Li [this message]
2023-07-18 6:11 ` [PATCH] usb: dwc2: add new compatible for Intel SoCFPGA Stratix10 platform Krzysztof Kozlowski
2023-07-18 7:43 ` Li, Meng
2023-07-18 7:56 ` Krzysztof Kozlowski
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