* [PATCH 01/10] arm64: dts: imx8ulp: add cm33 node
2023-06-25 12:42 [PATCH 00/10] arm64: dts: imx8ulp: add more nodes Peng Fan (OSS)
@ 2023-06-25 12:42 ` Peng Fan (OSS)
2023-06-25 12:42 ` [PATCH 02/10] arm64: dts: imx8ulp: set default clock for SDHC Peng Fan (OSS)
` (8 subsequent siblings)
9 siblings, 0 replies; 16+ messages in thread
From: Peng Fan (OSS) @ 2023-06-25 12:42 UTC (permalink / raw)
To: robh+dt, krzysztof.kozlowski+dt, shawnguo, s.hauer
Cc: kernel, festevam, linux-imx, devicetree, linux-arm-kernel,
linux-kernel, Peng Fan
From: Peng Fan <peng.fan@nxp.com>
Add i.MX8ULP CM33 node.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
arch/arm64/boot/dts/freescale/imx8ulp.dtsi | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8ulp.dtsi b/arch/arm64/boot/dts/freescale/imx8ulp.dtsi
index 57627bdaa851..8116d6eeb738 100644
--- a/arch/arm64/boot/dts/freescale/imx8ulp.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8ulp.dtsi
@@ -148,6 +148,11 @@ scmi_sensor: protocol@15 {
};
};
+ cm33: remoteproc-cm33 {
+ compatible = "fsl,imx8ulp-cm33";
+ status = "disabled";
+ };
+
soc: soc@0 {
compatible = "simple-bus";
#address-cells = <1>;
--
2.37.1
^ permalink raw reply related [flat|nested] 16+ messages in thread* [PATCH 02/10] arm64: dts: imx8ulp: set default clock for SDHC
2023-06-25 12:42 [PATCH 00/10] arm64: dts: imx8ulp: add more nodes Peng Fan (OSS)
2023-06-25 12:42 ` [PATCH 01/10] arm64: dts: imx8ulp: add cm33 node Peng Fan (OSS)
@ 2023-06-25 12:42 ` Peng Fan (OSS)
2023-06-25 12:42 ` [PATCH 03/10] arm64: dts: imx8ulp: add thermal node Peng Fan (OSS)
` (7 subsequent siblings)
9 siblings, 0 replies; 16+ messages in thread
From: Peng Fan (OSS) @ 2023-06-25 12:42 UTC (permalink / raw)
To: robh+dt, krzysztof.kozlowski+dt, shawnguo, s.hauer
Cc: kernel, festevam, linux-imx, devicetree, linux-arm-kernel,
linux-kernel, Peng Fan, Haibo Chen, Ye Li
From: Peng Fan <peng.fan@nxp.com>
Set default clock rate and parents for SDHC[0,1,2].
The PLL3 PFD2 maximum frequency is 332Mhz, we can't set it to 389Mhz
as USDHC clock parent. Because PLL3 PFD0 is used for NIC, PFD1 is used
for audio, the only choice is PFD3 which can reach to 400Mhz.
USDHC1 and USDHC2 maximum PCC clock rate is 200Mhz in Over Drive mode,
and 100Mhz in Nominal/Low Drive mode, when PTE or PTF is used.
The patch adjusts clock parent to PLL3 PFD3 DIV1 for USDHC0, PLL3
PFD3 DIV2 for USDHC1 and USDHC2. And set the max rate to meet
restrictions.
Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
arch/arm64/boot/dts/freescale/imx8ulp.dtsi | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8ulp.dtsi b/arch/arm64/boot/dts/freescale/imx8ulp.dtsi
index 8116d6eeb738..ba0edb9a009b 100644
--- a/arch/arm64/boot/dts/freescale/imx8ulp.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8ulp.dtsi
@@ -370,6 +370,10 @@ usdhc0: mmc@298d0000 {
<&pcc4 IMX8ULP_CLK_USDHC0>;
clock-names = "ipg", "ahb", "per";
power-domains = <&scmi_devpd IMX8ULP_PD_USDHC0>;
+ assigned-clocks = <&cgc1 IMX8ULP_CLK_SPLL3_PFD3_DIV1>,
+ <&pcc4 IMX8ULP_CLK_USDHC0>;
+ assigned-clock-parents = <0>, <&cgc1 IMX8ULP_CLK_SPLL3_PFD3_DIV1>;
+ assigned-clock-rates = <389283840>, <389283840>;
fsl,tuning-start-tap = <20>;
fsl,tuning-step = <2>;
bus-width = <4>;
@@ -385,6 +389,10 @@ usdhc1: mmc@298e0000 {
<&pcc4 IMX8ULP_CLK_USDHC1>;
clock-names = "ipg", "ahb", "per";
power-domains = <&scmi_devpd IMX8ULP_PD_USDHC1>;
+ assigned-clocks = <&cgc1 IMX8ULP_CLK_SPLL3_PFD3_DIV2>,
+ <&pcc4 IMX8ULP_CLK_USDHC1>;
+ assigned-clock-parents = <0>, <&cgc1 IMX8ULP_CLK_SPLL3_PFD3_DIV2>;
+ assigned-clock-rates = <194641920>, <194641920>;
fsl,tuning-start-tap = <20>;
fsl,tuning-step = <2>;
bus-width = <4>;
@@ -400,6 +408,10 @@ usdhc2: mmc@298f0000 {
<&pcc4 IMX8ULP_CLK_USDHC2>;
clock-names = "ipg", "ahb", "per";
power-domains = <&scmi_devpd IMX8ULP_PD_USDHC2_USB1>;
+ assigned-clocks = <&cgc1 IMX8ULP_CLK_SPLL3_PFD3_DIV2>,
+ <&pcc4 IMX8ULP_CLK_USDHC2>;
+ assigned-clock-parents = <0>, <&cgc1 IMX8ULP_CLK_SPLL3_PFD3_DIV2>;
+ assigned-clock-rates = <194641920>, <194641920>;
fsl,tuning-start-tap = <20>;
fsl,tuning-step = <2>;
bus-width = <4>;
--
2.37.1
^ permalink raw reply related [flat|nested] 16+ messages in thread* [PATCH 03/10] arm64: dts: imx8ulp: add thermal node
2023-06-25 12:42 [PATCH 00/10] arm64: dts: imx8ulp: add more nodes Peng Fan (OSS)
2023-06-25 12:42 ` [PATCH 01/10] arm64: dts: imx8ulp: add cm33 node Peng Fan (OSS)
2023-06-25 12:42 ` [PATCH 02/10] arm64: dts: imx8ulp: set default clock for SDHC Peng Fan (OSS)
@ 2023-06-25 12:42 ` Peng Fan (OSS)
2023-07-18 3:30 ` Shawn Guo
2023-06-25 12:42 ` [PATCH 04/10] arm64: dts: imx8ulp: add cpuidle node Peng Fan (OSS)
` (6 subsequent siblings)
9 siblings, 1 reply; 16+ messages in thread
From: Peng Fan (OSS) @ 2023-06-25 12:42 UTC (permalink / raw)
To: robh+dt, krzysztof.kozlowski+dt, shawnguo, s.hauer
Cc: kernel, festevam, linux-imx, devicetree, linux-arm-kernel,
linux-kernel, Peng Fan, Jacky Bai
From: Peng Fan <peng.fan@nxp.com>
Add thermal node. Cooling map is not added, because frequency runtime
changing not supported for now.
Reviewed-by: Jacky Bai <ping.bai@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
arch/arm64/boot/dts/freescale/imx8ulp.dtsi | 22 ++++++++++++++++++++++
1 file changed, 22 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8ulp.dtsi b/arch/arm64/boot/dts/freescale/imx8ulp.dtsi
index ba0edb9a009b..fd30475a561d 100644
--- a/arch/arm64/boot/dts/freescale/imx8ulp.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8ulp.dtsi
@@ -7,6 +7,7 @@
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/power/imx8ulp-power.h>
+#include <dt-bindings/thermal/thermal.h>
#include "imx8ulp-pinfunc.h"
@@ -78,6 +79,27 @@ psci {
method = "smc";
};
+ thermal-zones {
+ cpu-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <2000>;
+ thermal-sensors = <&scmi_sensor 0>;
+ trips {
+ cpu_alert0: trip0 {
+ temperature = <85000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu_crit0: trip1 {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+ };
+ };
+
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* Physical Secure */
--
2.37.1
^ permalink raw reply related [flat|nested] 16+ messages in thread* Re: [PATCH 03/10] arm64: dts: imx8ulp: add thermal node
2023-06-25 12:42 ` [PATCH 03/10] arm64: dts: imx8ulp: add thermal node Peng Fan (OSS)
@ 2023-07-18 3:30 ` Shawn Guo
0 siblings, 0 replies; 16+ messages in thread
From: Shawn Guo @ 2023-07-18 3:30 UTC (permalink / raw)
To: Peng Fan (OSS)
Cc: robh+dt, krzysztof.kozlowski+dt, s.hauer, kernel, festevam,
linux-imx, devicetree, linux-arm-kernel, linux-kernel, Peng Fan,
Jacky Bai
On Sun, Jun 25, 2023 at 08:42:31PM +0800, Peng Fan (OSS) wrote:
> From: Peng Fan <peng.fan@nxp.com>
>
> Add thermal node. Cooling map is not added, because frequency runtime
> changing not supported for now.
>
> Reviewed-by: Jacky Bai <ping.bai@nxp.com>
> Signed-off-by: Peng Fan <peng.fan@nxp.com>
> ---
> arch/arm64/boot/dts/freescale/imx8ulp.dtsi | 22 ++++++++++++++++++++++
> 1 file changed, 22 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/freescale/imx8ulp.dtsi b/arch/arm64/boot/dts/freescale/imx8ulp.dtsi
> index ba0edb9a009b..fd30475a561d 100644
> --- a/arch/arm64/boot/dts/freescale/imx8ulp.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8ulp.dtsi
> @@ -7,6 +7,7 @@
> #include <dt-bindings/gpio/gpio.h>
> #include <dt-bindings/interrupt-controller/arm-gic.h>
> #include <dt-bindings/power/imx8ulp-power.h>
> +#include <dt-bindings/thermal/thermal.h>
>
> #include "imx8ulp-pinfunc.h"
>
> @@ -78,6 +79,27 @@ psci {
> method = "smc";
> };
>
> + thermal-zones {
> + cpu-thermal {
> + polling-delay-passive = <250>;
> + polling-delay = <2000>;
> + thermal-sensors = <&scmi_sensor 0>;
Have a newline between property list and child node.
Shawn
> + trips {
> + cpu_alert0: trip0 {
> + temperature = <85000>;
> + hysteresis = <2000>;
> + type = "passive";
> + };
> +
> + cpu_crit0: trip1 {
> + temperature = <95000>;
> + hysteresis = <2000>;
> + type = "critical";
> + };
> + };
> + };
> + };
> +
> timer {
> compatible = "arm,armv8-timer";
> interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* Physical Secure */
> --
> 2.37.1
>
^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH 04/10] arm64: dts: imx8ulp: add cpuidle node
2023-06-25 12:42 [PATCH 00/10] arm64: dts: imx8ulp: add more nodes Peng Fan (OSS)
` (2 preceding siblings ...)
2023-06-25 12:42 ` [PATCH 03/10] arm64: dts: imx8ulp: add thermal node Peng Fan (OSS)
@ 2023-06-25 12:42 ` Peng Fan (OSS)
2023-06-25 12:42 ` [PATCH 05/10] arm64: dts: imx8ulp: add flexspi node Peng Fan (OSS)
` (5 subsequent siblings)
9 siblings, 0 replies; 16+ messages in thread
From: Peng Fan (OSS) @ 2023-06-25 12:42 UTC (permalink / raw)
To: robh+dt, krzysztof.kozlowski+dt, shawnguo, s.hauer
Cc: kernel, festevam, linux-imx, devicetree, linux-arm-kernel,
linux-kernel, Peng Fan, Jacky Bai
From: Peng Fan <peng.fan@nxp.com>
Add cpuidle node and enable cpuidle for dual cores. The HW mode in
Arm Trusted Firmware is SoC Application Power Domain Sleep mode.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
arch/arm64/boot/dts/freescale/imx8ulp.dtsi | 15 +++++++++++++++
1 file changed, 15 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8ulp.dtsi b/arch/arm64/boot/dts/freescale/imx8ulp.dtsi
index fd30475a561d..16906c20bce9 100644
--- a/arch/arm64/boot/dts/freescale/imx8ulp.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8ulp.dtsi
@@ -40,6 +40,7 @@ A35_0: cpu@0 {
reg = <0x0 0x0>;
enable-method = "psci";
next-level-cache = <&A35_L2>;
+ cpu-idle-states = <&cpu_sleep>;
};
A35_1: cpu@1 {
@@ -48,6 +49,7 @@ A35_1: cpu@1 {
reg = <0x0 0x1>;
enable-method = "psci";
next-level-cache = <&A35_L2>;
+ cpu-idle-states = <&cpu_sleep>;
};
A35_L2: l2-cache0 {
@@ -55,6 +57,19 @@ A35_L2: l2-cache0 {
cache-level = <2>;
cache-unified;
};
+
+ idle-states {
+ entry-method = "psci";
+
+ cpu_sleep: cpu-sleep {
+ compatible = "arm,idle-state";
+ arm,psci-suspend-param = <0x0>;
+ local-timer-stop;
+ entry-latency-us = <1000>;
+ exit-latency-us = <700>;
+ min-residency-us = <2700>;
+ };
+ };
};
gic: interrupt-controller@2d400000 {
--
2.37.1
^ permalink raw reply related [flat|nested] 16+ messages in thread* [PATCH 05/10] arm64: dts: imx8ulp: add flexspi node
2023-06-25 12:42 [PATCH 00/10] arm64: dts: imx8ulp: add more nodes Peng Fan (OSS)
` (3 preceding siblings ...)
2023-06-25 12:42 ` [PATCH 04/10] arm64: dts: imx8ulp: add cpuidle node Peng Fan (OSS)
@ 2023-06-25 12:42 ` Peng Fan (OSS)
2023-06-25 12:42 ` [PATCH 06/10] arm64: dts: imx8ulp-evk: add reserved memory for cma Peng Fan (OSS)
` (4 subsequent siblings)
9 siblings, 0 replies; 16+ messages in thread
From: Peng Fan (OSS) @ 2023-06-25 12:42 UTC (permalink / raw)
To: robh+dt, krzysztof.kozlowski+dt, shawnguo, s.hauer
Cc: kernel, festevam, linux-imx, devicetree, linux-arm-kernel,
linux-kernel, Haibo Chen, Peng Fan
From: Haibo Chen <haibo.chen@nxp.com>
Add flexspi node, flexspi has a special memory region mapped to
0x60000000~0x6fffffff. This region is for AHB usage. So add this region
to SoC ranges.
Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
arch/arm64/boot/dts/freescale/imx8ulp.dtsi | 18 +++++++++++++++++-
1 file changed, 17 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/freescale/imx8ulp.dtsi b/arch/arm64/boot/dts/freescale/imx8ulp.dtsi
index 16906c20bce9..4d317029490c 100644
--- a/arch/arm64/boot/dts/freescale/imx8ulp.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8ulp.dtsi
@@ -194,7 +194,8 @@ soc: soc@0 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
- ranges = <0x0 0x0 0x0 0x40000000>;
+ ranges = <0x0 0x0 0x0 0x40000000>,
+ <0x60000000 0x0 0x60000000 0x1000000>;
s4muap: mailbox@27020000 {
compatible = "fsl,imx8ulp-mu-s4";
@@ -349,6 +350,21 @@ pcc4: clock-controller@29800000 {
#reset-cells = <1>;
};
+ flexspi2: spi@29810000 {
+ compatible = "nxp,imx8mm-fspi";
+ reg = <0x29810000 0x10000>, <0x60000000 0x10000000>;
+ reg-names = "fspi_base", "fspi_mmap";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&pcc4 IMX8ULP_CLK_FLEXSPI2>,
+ <&pcc4 IMX8ULP_CLK_FLEXSPI2>;
+ clock-names = "fspi", "fspi_en";
+ assigned-clocks = <&pcc4 IMX8ULP_CLK_FLEXSPI2>;
+ assigned-clock-parents = <&cgc1 IMX8ULP_CLK_SPLL3_PFD3_DIV2>;
+ status = "disabled";
+ };
+
lpi2c6: i2c@29840000 {
compatible = "fsl,imx8ulp-lpi2c", "fsl,imx7ulp-lpi2c";
reg = <0x29840000 0x10000>;
--
2.37.1
^ permalink raw reply related [flat|nested] 16+ messages in thread* [PATCH 06/10] arm64: dts: imx8ulp-evk: add reserved memory for cma
2023-06-25 12:42 [PATCH 00/10] arm64: dts: imx8ulp: add more nodes Peng Fan (OSS)
` (4 preceding siblings ...)
2023-06-25 12:42 ` [PATCH 05/10] arm64: dts: imx8ulp: add flexspi node Peng Fan (OSS)
@ 2023-06-25 12:42 ` Peng Fan (OSS)
2023-06-25 12:42 ` [PATCH 07/10] arm64: dts: imx8ulp-evk: enable CM33 node Peng Fan (OSS)
` (3 subsequent siblings)
9 siblings, 0 replies; 16+ messages in thread
From: Peng Fan (OSS) @ 2023-06-25 12:42 UTC (permalink / raw)
To: robh+dt, krzysztof.kozlowski+dt, shawnguo, s.hauer
Cc: kernel, festevam, linux-imx, devicetree, linux-arm-kernel,
linux-kernel, Peng Fan
From: Peng Fan <peng.fan@nxp.com>
Add reserved memory node for CMA usage.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
arch/arm64/boot/dts/freescale/imx8ulp-evk.dts | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts b/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts
index f1c6d933a17c..e171390a1888 100644
--- a/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts
+++ b/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts
@@ -20,6 +20,19 @@ memory@80000000 {
reg = <0x0 0x80000000 0 0x80000000>;
};
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ linux,cma {
+ compatible = "shared-dma-pool";
+ reusable;
+ size = <0 0x28000000>;
+ linux,cma-default;
+ };
+ };
+
clock_ext_rmii: clock-ext-rmii {
compatible = "fixed-clock";
clock-frequency = <50000000>;
--
2.37.1
^ permalink raw reply related [flat|nested] 16+ messages in thread* [PATCH 07/10] arm64: dts: imx8ulp-evk: enable CM33 node
2023-06-25 12:42 [PATCH 00/10] arm64: dts: imx8ulp: add more nodes Peng Fan (OSS)
` (5 preceding siblings ...)
2023-06-25 12:42 ` [PATCH 06/10] arm64: dts: imx8ulp-evk: add reserved memory for cma Peng Fan (OSS)
@ 2023-06-25 12:42 ` Peng Fan (OSS)
2023-06-25 12:42 ` [PATCH 08/10] arm64: dts: imx8ulp-evk: add spi-nor device support Peng Fan (OSS)
` (2 subsequent siblings)
9 siblings, 0 replies; 16+ messages in thread
From: Peng Fan (OSS) @ 2023-06-25 12:42 UTC (permalink / raw)
To: robh+dt, krzysztof.kozlowski+dt, shawnguo, s.hauer
Cc: kernel, festevam, linux-imx, devicetree, linux-arm-kernel,
linux-kernel, Peng Fan
From: Peng Fan <peng.fan@nxp.com>
Enable CM33 node to support rpmsg feature. To use rpmsg, also need
to enable mu node for mailbox doorbell and reserved memory node
for vring, and data buffer. And reserved a piece DRAM memory for case
that m33 images loaded in DRAM.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
arch/arm64/boot/dts/freescale/imx8ulp-evk.dts | 50 +++++++++++++++++++
1 file changed, 50 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts b/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts
index e171390a1888..d66e31cf83fe 100644
--- a/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts
+++ b/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts
@@ -31,6 +31,42 @@ linux,cma {
size = <0 0x28000000>;
linux,cma-default;
};
+
+ m33_reserved: noncacheable-section@a8600000 {
+ reg = <0 0xa8600000 0 0x1000000>;
+ no-map;
+ };
+
+ rsc_table: rsc-table@1fff8000{
+ reg = <0 0x1fff8000 0 0x1000>;
+ no-map;
+ };
+
+ vdev0vring0: vdev0vring0@aff00000 {
+ reg = <0 0xaff00000 0 0x8000>;
+ no-map;
+ };
+
+ vdev0vring1: vdev0vring1@aff08000 {
+ reg = <0 0xaff08000 0 0x8000>;
+ no-map;
+ };
+
+ vdev1vring0: vdev1vring0@aff10000 {
+ reg = <0 0xaff10000 0 0x8000>;
+ no-map;
+ };
+
+ vdev1vring1: vdev1vring1@aff18000 {
+ reg = <0 0xaff18000 0 0x8000>;
+ no-map;
+ };
+
+ vdevbuffer: vdevbuffer@a8400000 {
+ compatible = "shared-dma-pool";
+ reg = <0 0xa8400000 0 0x100000>;
+ no-map;
+ };
};
clock_ext_rmii: clock-ext-rmii {
@@ -49,6 +85,16 @@ clock_ext_ts: clock-ext-ts {
};
};
+&cm33 {
+ mbox-names = "tx", "rx", "rxdb";
+ mboxes = <&mu 0 1>,
+ <&mu 1 1>,
+ <&mu 3 1>;
+ memory-region = <&vdevbuffer>, <&vdev0vring0>, <&vdev0vring1>,
+ <&vdev1vring0>, <&vdev1vring1>, <&rsc_table>;
+ status = "okay";
+};
+
&lpuart5 {
/* console */
pinctrl-names = "default", "sleep";
@@ -92,6 +138,10 @@ ethphy: ethernet-phy@1 {
};
};
+&mu {
+ status = "okay";
+};
+
&iomuxc1 {
pinctrl_enet: enetgrp {
fsl,pins = <
--
2.37.1
^ permalink raw reply related [flat|nested] 16+ messages in thread* [PATCH 08/10] arm64: dts: imx8ulp-evk: add spi-nor device support
2023-06-25 12:42 [PATCH 00/10] arm64: dts: imx8ulp: add more nodes Peng Fan (OSS)
` (6 preceding siblings ...)
2023-06-25 12:42 ` [PATCH 07/10] arm64: dts: imx8ulp-evk: enable CM33 node Peng Fan (OSS)
@ 2023-06-25 12:42 ` Peng Fan (OSS)
2023-07-18 3:29 ` Shawn Guo
2023-06-25 12:42 ` [PATCH 09/10] arm64: dts: imx8ulp-evk: add 100MHz/200MHz pinctrl setting for eMMC Peng Fan (OSS)
2023-06-25 12:42 ` [PATCH 10/10] arm64: dts: imx8ulp-evk: enable lpi2c7 bus Peng Fan (OSS)
9 siblings, 1 reply; 16+ messages in thread
From: Peng Fan (OSS) @ 2023-06-25 12:42 UTC (permalink / raw)
To: robh+dt, krzysztof.kozlowski+dt, shawnguo, s.hauer
Cc: kernel, festevam, linux-imx, devicetree, linux-arm-kernel,
linux-kernel, Han Xu, Haibo Chen, Peng Fan
From: Han Xu <han.xu@nxp.com>
Add spi-nor support.
- 8 bit mode for RX/TX.
- Set the clock rate to 200MHz.
- add default/sleep pinctrl.
Co-developed-by: Haibo Chen <haibo.chen@nxp.com>
Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
Signed-off-by: Han Xu <han.xu@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
arch/arm64/boot/dts/freescale/imx8ulp-evk.dts | 34 +++++++++++++++++++
1 file changed, 34 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts b/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts
index d66e31cf83fe..e459dc35e469 100644
--- a/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts
+++ b/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts
@@ -95,6 +95,23 @@ &cm33 {
status = "okay";
};
+&flexspi2 {
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&pinctrl_flexspi2_ptd>;
+ pinctrl-1 = <&pinctrl_flexspi2_ptd>;
+ status = "okay";
+
+ mx25uw51345gxdi00: flash@0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "jedec,spi-nor";
+ spi-max-frequency = <200000000>;
+ spi-tx-bus-width = <8>;
+ spi-rx-bus-width = <8>;
+ };
+};
+
&lpuart5 {
/* console */
pinctrl-names = "default", "sleep";
@@ -159,6 +176,23 @@ MX8ULP_PAD_PTF10__ENET0_1588_CLKIN 0x43
>;
};
+ pinctrl_flexspi2_ptd: flexspi2ptdgrp {
+ fsl,pins = <
+
+ MX8ULP_PAD_PTD12__FLEXSPI2_A_SS0_B 0x42
+ MX8ULP_PAD_PTD13__FLEXSPI2_A_SCLK 0x42
+ MX8ULP_PAD_PTD14__FLEXSPI2_A_DATA3 0x42
+ MX8ULP_PAD_PTD15__FLEXSPI2_A_DATA2 0x42
+ MX8ULP_PAD_PTD16__FLEXSPI2_A_DATA1 0x42
+ MX8ULP_PAD_PTD17__FLEXSPI2_A_DATA0 0x42
+ MX8ULP_PAD_PTD18__FLEXSPI2_A_DQS 0x42
+ MX8ULP_PAD_PTD19__FLEXSPI2_A_DATA7 0x42
+ MX8ULP_PAD_PTD20__FLEXSPI2_A_DATA6 0x42
+ MX8ULP_PAD_PTD21__FLEXSPI2_A_DATA5 0x42
+ MX8ULP_PAD_PTD22__FLEXSPI2_A_DATA4 0x42
+ >;
+ };
+
pinctrl_lpuart5: lpuart5grp {
fsl,pins = <
MX8ULP_PAD_PTF14__LPUART5_TX 0x3
--
2.37.1
^ permalink raw reply related [flat|nested] 16+ messages in thread* Re: [PATCH 08/10] arm64: dts: imx8ulp-evk: add spi-nor device support
2023-06-25 12:42 ` [PATCH 08/10] arm64: dts: imx8ulp-evk: add spi-nor device support Peng Fan (OSS)
@ 2023-07-18 3:29 ` Shawn Guo
0 siblings, 0 replies; 16+ messages in thread
From: Shawn Guo @ 2023-07-18 3:29 UTC (permalink / raw)
To: Peng Fan (OSS)
Cc: robh+dt, krzysztof.kozlowski+dt, s.hauer, kernel, festevam,
linux-imx, devicetree, linux-arm-kernel, linux-kernel, Han Xu,
Haibo Chen, Peng Fan
On Sun, Jun 25, 2023 at 08:42:36PM +0800, Peng Fan (OSS) wrote:
> From: Han Xu <han.xu@nxp.com>
>
> Add spi-nor support.
> - 8 bit mode for RX/TX.
> - Set the clock rate to 200MHz.
> - add default/sleep pinctrl.
>
> Co-developed-by: Haibo Chen <haibo.chen@nxp.com>
> Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
> Signed-off-by: Han Xu <han.xu@nxp.com>
> Signed-off-by: Peng Fan <peng.fan@nxp.com>
> ---
> arch/arm64/boot/dts/freescale/imx8ulp-evk.dts | 34 +++++++++++++++++++
> 1 file changed, 34 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts b/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts
> index d66e31cf83fe..e459dc35e469 100644
> --- a/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts
> +++ b/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts
> @@ -95,6 +95,23 @@ &cm33 {
> status = "okay";
> };
>
> +&flexspi2 {
> + pinctrl-names = "default", "sleep";
> + pinctrl-0 = <&pinctrl_flexspi2_ptd>;
> + pinctrl-1 = <&pinctrl_flexspi2_ptd>;
> + status = "okay";
> +
> + mx25uw51345gxdi00: flash@0 {
> + reg = <0>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> + compatible = "jedec,spi-nor";
We usually start the property list with 'compatible'.
Shawn
> + spi-max-frequency = <200000000>;
> + spi-tx-bus-width = <8>;
> + spi-rx-bus-width = <8>;
> + };
> +};
> +
> &lpuart5 {
> /* console */
> pinctrl-names = "default", "sleep";
> @@ -159,6 +176,23 @@ MX8ULP_PAD_PTF10__ENET0_1588_CLKIN 0x43
> >;
> };
>
> + pinctrl_flexspi2_ptd: flexspi2ptdgrp {
> + fsl,pins = <
> +
> + MX8ULP_PAD_PTD12__FLEXSPI2_A_SS0_B 0x42
> + MX8ULP_PAD_PTD13__FLEXSPI2_A_SCLK 0x42
> + MX8ULP_PAD_PTD14__FLEXSPI2_A_DATA3 0x42
> + MX8ULP_PAD_PTD15__FLEXSPI2_A_DATA2 0x42
> + MX8ULP_PAD_PTD16__FLEXSPI2_A_DATA1 0x42
> + MX8ULP_PAD_PTD17__FLEXSPI2_A_DATA0 0x42
> + MX8ULP_PAD_PTD18__FLEXSPI2_A_DQS 0x42
> + MX8ULP_PAD_PTD19__FLEXSPI2_A_DATA7 0x42
> + MX8ULP_PAD_PTD20__FLEXSPI2_A_DATA6 0x42
> + MX8ULP_PAD_PTD21__FLEXSPI2_A_DATA5 0x42
> + MX8ULP_PAD_PTD22__FLEXSPI2_A_DATA4 0x42
> + >;
> + };
> +
> pinctrl_lpuart5: lpuart5grp {
> fsl,pins = <
> MX8ULP_PAD_PTF14__LPUART5_TX 0x3
> --
> 2.37.1
>
^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH 09/10] arm64: dts: imx8ulp-evk: add 100MHz/200MHz pinctrl setting for eMMC
2023-06-25 12:42 [PATCH 00/10] arm64: dts: imx8ulp: add more nodes Peng Fan (OSS)
` (7 preceding siblings ...)
2023-06-25 12:42 ` [PATCH 08/10] arm64: dts: imx8ulp-evk: add spi-nor device support Peng Fan (OSS)
@ 2023-06-25 12:42 ` Peng Fan (OSS)
2023-07-18 3:32 ` Shawn Guo
2023-06-25 12:42 ` [PATCH 10/10] arm64: dts: imx8ulp-evk: enable lpi2c7 bus Peng Fan (OSS)
9 siblings, 1 reply; 16+ messages in thread
From: Peng Fan (OSS) @ 2023-06-25 12:42 UTC (permalink / raw)
To: robh+dt, krzysztof.kozlowski+dt, shawnguo, s.hauer
Cc: kernel, festevam, linux-imx, devicetree, linux-arm-kernel,
linux-kernel, Haibo Chen, Sherry Sun, Peng Fan
From: Haibo Chen <haibo.chen@nxp.com>
Add 100MHz and 200MHz pinctrl setting for eMMC, and enable 8 bit bus mode
to config the eMMC work at HS400ES mode.
Also update to use Standard Drive Strength for USDHC pad to get a better
signal quality per Hardware team suggests.
Reviewed-by: Sherry Sun <sherry.sun@nxp.com>
Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
arch/arm64/boot/dts/freescale/imx8ulp-evk.dts | 26 ++++++++++---------
1 file changed, 14 insertions(+), 12 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts b/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts
index e459dc35e469..ab7af705bbca 100644
--- a/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts
+++ b/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts
@@ -121,9 +121,11 @@ &lpuart5 {
};
&usdhc0 {
- pinctrl-names = "default", "sleep";
+ pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
pinctrl-0 = <&pinctrl_usdhc0>;
pinctrl-1 = <&pinctrl_usdhc0>;
+ pinctrl-2 = <&pinctrl_usdhc0>;
+ pinctrl-3 = <&pinctrl_usdhc0>;
non-removable;
bus-width = <8>;
status = "okay";
@@ -202,17 +204,17 @@ MX8ULP_PAD_PTF15__LPUART5_RX 0x3
pinctrl_usdhc0: usdhc0grp {
fsl,pins = <
- MX8ULP_PAD_PTD1__SDHC0_CMD 0x43
- MX8ULP_PAD_PTD2__SDHC0_CLK 0x10042
- MX8ULP_PAD_PTD10__SDHC0_D0 0x43
- MX8ULP_PAD_PTD9__SDHC0_D1 0x43
- MX8ULP_PAD_PTD8__SDHC0_D2 0x43
- MX8ULP_PAD_PTD7__SDHC0_D3 0x43
- MX8ULP_PAD_PTD6__SDHC0_D4 0x43
- MX8ULP_PAD_PTD5__SDHC0_D5 0x43
- MX8ULP_PAD_PTD4__SDHC0_D6 0x43
- MX8ULP_PAD_PTD3__SDHC0_D7 0x43
- MX8ULP_PAD_PTD11__SDHC0_DQS 0x10042
+ MX8ULP_PAD_PTD1__SDHC0_CMD 0x3
+ MX8ULP_PAD_PTD2__SDHC0_CLK 0x10002
+ MX8ULP_PAD_PTD10__SDHC0_D0 0x3
+ MX8ULP_PAD_PTD9__SDHC0_D1 0x3
+ MX8ULP_PAD_PTD8__SDHC0_D2 0x3
+ MX8ULP_PAD_PTD7__SDHC0_D3 0x3
+ MX8ULP_PAD_PTD6__SDHC0_D4 0x3
+ MX8ULP_PAD_PTD5__SDHC0_D5 0x3
+ MX8ULP_PAD_PTD4__SDHC0_D6 0x3
+ MX8ULP_PAD_PTD3__SDHC0_D7 0x3
+ MX8ULP_PAD_PTD11__SDHC0_DQS 0x10002
>;
};
};
--
2.37.1
^ permalink raw reply related [flat|nested] 16+ messages in thread* Re: [PATCH 09/10] arm64: dts: imx8ulp-evk: add 100MHz/200MHz pinctrl setting for eMMC
2023-06-25 12:42 ` [PATCH 09/10] arm64: dts: imx8ulp-evk: add 100MHz/200MHz pinctrl setting for eMMC Peng Fan (OSS)
@ 2023-07-18 3:32 ` Shawn Guo
2023-07-24 6:51 ` Bough Chen
0 siblings, 1 reply; 16+ messages in thread
From: Shawn Guo @ 2023-07-18 3:32 UTC (permalink / raw)
To: Peng Fan (OSS)
Cc: robh+dt, krzysztof.kozlowski+dt, s.hauer, kernel, festevam,
linux-imx, devicetree, linux-arm-kernel, linux-kernel, Haibo Chen,
Sherry Sun, Peng Fan
On Sun, Jun 25, 2023 at 08:42:37PM +0800, Peng Fan (OSS) wrote:
> From: Haibo Chen <haibo.chen@nxp.com>
>
> Add 100MHz and 200MHz pinctrl setting for eMMC, and enable 8 bit bus mode
> to config the eMMC work at HS400ES mode.
>
> Also update to use Standard Drive Strength for USDHC pad to get a better
> signal quality per Hardware team suggests.
>
> Reviewed-by: Sherry Sun <sherry.sun@nxp.com>
> Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
> Signed-off-by: Peng Fan <peng.fan@nxp.com>
> ---
> arch/arm64/boot/dts/freescale/imx8ulp-evk.dts | 26 ++++++++++---------
> 1 file changed, 14 insertions(+), 12 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts b/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts
> index e459dc35e469..ab7af705bbca 100644
> --- a/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts
> +++ b/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts
> @@ -121,9 +121,11 @@ &lpuart5 {
> };
>
> &usdhc0 {
> - pinctrl-names = "default", "sleep";
> + pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
> pinctrl-0 = <&pinctrl_usdhc0>;
> pinctrl-1 = <&pinctrl_usdhc0>;
> + pinctrl-2 = <&pinctrl_usdhc0>;
> + pinctrl-3 = <&pinctrl_usdhc0>;
All three speed modes use the same pinctrl?
Shawn
> non-removable;
> bus-width = <8>;
> status = "okay";
> @@ -202,17 +204,17 @@ MX8ULP_PAD_PTF15__LPUART5_RX 0x3
>
> pinctrl_usdhc0: usdhc0grp {
> fsl,pins = <
> - MX8ULP_PAD_PTD1__SDHC0_CMD 0x43
> - MX8ULP_PAD_PTD2__SDHC0_CLK 0x10042
> - MX8ULP_PAD_PTD10__SDHC0_D0 0x43
> - MX8ULP_PAD_PTD9__SDHC0_D1 0x43
> - MX8ULP_PAD_PTD8__SDHC0_D2 0x43
> - MX8ULP_PAD_PTD7__SDHC0_D3 0x43
> - MX8ULP_PAD_PTD6__SDHC0_D4 0x43
> - MX8ULP_PAD_PTD5__SDHC0_D5 0x43
> - MX8ULP_PAD_PTD4__SDHC0_D6 0x43
> - MX8ULP_PAD_PTD3__SDHC0_D7 0x43
> - MX8ULP_PAD_PTD11__SDHC0_DQS 0x10042
> + MX8ULP_PAD_PTD1__SDHC0_CMD 0x3
> + MX8ULP_PAD_PTD2__SDHC0_CLK 0x10002
> + MX8ULP_PAD_PTD10__SDHC0_D0 0x3
> + MX8ULP_PAD_PTD9__SDHC0_D1 0x3
> + MX8ULP_PAD_PTD8__SDHC0_D2 0x3
> + MX8ULP_PAD_PTD7__SDHC0_D3 0x3
> + MX8ULP_PAD_PTD6__SDHC0_D4 0x3
> + MX8ULP_PAD_PTD5__SDHC0_D5 0x3
> + MX8ULP_PAD_PTD4__SDHC0_D6 0x3
> + MX8ULP_PAD_PTD3__SDHC0_D7 0x3
> + MX8ULP_PAD_PTD11__SDHC0_DQS 0x10002
> >;
> };
> };
> --
> 2.37.1
>
^ permalink raw reply [flat|nested] 16+ messages in thread* RE: [PATCH 09/10] arm64: dts: imx8ulp-evk: add 100MHz/200MHz pinctrl setting for eMMC
2023-07-18 3:32 ` Shawn Guo
@ 2023-07-24 6:51 ` Bough Chen
2023-07-30 3:04 ` Shawn Guo
0 siblings, 1 reply; 16+ messages in thread
From: Bough Chen @ 2023-07-24 6:51 UTC (permalink / raw)
To: Shawn Guo, Peng Fan (OSS)
Cc: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org,
s.hauer@pengutronix.de, kernel@pengutronix.de, festevam@gmail.com,
dl-linux-imx, devicetree@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, Sherry Sun, Peng Fan
> -----Original Message-----
> From: Shawn Guo <shawnguo@kernel.org>
> Sent: 2023年7月18日 11:32
> To: Peng Fan (OSS) <peng.fan@oss.nxp.com>
> Cc: robh+dt@kernel.org; krzysztof.kozlowski+dt@linaro.org;
> s.hauer@pengutronix.de; kernel@pengutronix.de; festevam@gmail.com;
> dl-linux-imx <linux-imx@nxp.com>; devicetree@vger.kernel.org;
> linux-arm-kernel@lists.infradead.org; linux-kernel@vger.kernel.org; Bough
> Chen <haibo.chen@nxp.com>; Sherry Sun <sherry.sun@nxp.com>; Peng Fan
> <peng.fan@nxp.com>
> Subject: Re: [PATCH 09/10] arm64: dts: imx8ulp-evk: add 100MHz/200MHz
> pinctrl setting for eMMC
>
> On Sun, Jun 25, 2023 at 08:42:37PM +0800, Peng Fan (OSS) wrote:
> > From: Haibo Chen <haibo.chen@nxp.com>
> >
> > Add 100MHz and 200MHz pinctrl setting for eMMC, and enable 8 bit bus
> > mode to config the eMMC work at HS400ES mode.
> >
> > Also update to use Standard Drive Strength for USDHC pad to get a
> > better signal quality per Hardware team suggests.
> >
> > Reviewed-by: Sherry Sun <sherry.sun@nxp.com>
> > Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
> > Signed-off-by: Peng Fan <peng.fan@nxp.com>
> > ---
> > arch/arm64/boot/dts/freescale/imx8ulp-evk.dts | 26
> > ++++++++++---------
> > 1 file changed, 14 insertions(+), 12 deletions(-)
> >
> > diff --git a/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts
> > b/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts
> > index e459dc35e469..ab7af705bbca 100644
> > --- a/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts
> > +++ b/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts
> > @@ -121,9 +121,11 @@ &lpuart5 {
> > };
> >
> > &usdhc0 {
> > - pinctrl-names = "default", "sleep";
> > + pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
> > pinctrl-0 = <&pinctrl_usdhc0>;
> > pinctrl-1 = <&pinctrl_usdhc0>;
> > + pinctrl-2 = <&pinctrl_usdhc0>;
> > + pinctrl-3 = <&pinctrl_usdhc0>;
>
> All three speed modes use the same pinctrl?
Yes, the IOMUX on imx8ulp do not support config different drive strength. So here use the same pinctrl.
Best Regards
Haibo Chen
>
> Shawn
>
> > non-removable;
> > bus-width = <8>;
> > status = "okay";
> > @@ -202,17 +204,17 @@ MX8ULP_PAD_PTF15__LPUART5_RX 0x3
> >
> > pinctrl_usdhc0: usdhc0grp {
> > fsl,pins = <
> > - MX8ULP_PAD_PTD1__SDHC0_CMD 0x43
> > - MX8ULP_PAD_PTD2__SDHC0_CLK 0x10042
> > - MX8ULP_PAD_PTD10__SDHC0_D0 0x43
> > - MX8ULP_PAD_PTD9__SDHC0_D1 0x43
> > - MX8ULP_PAD_PTD8__SDHC0_D2 0x43
> > - MX8ULP_PAD_PTD7__SDHC0_D3 0x43
> > - MX8ULP_PAD_PTD6__SDHC0_D4 0x43
> > - MX8ULP_PAD_PTD5__SDHC0_D5 0x43
> > - MX8ULP_PAD_PTD4__SDHC0_D6 0x43
> > - MX8ULP_PAD_PTD3__SDHC0_D7 0x43
> > - MX8ULP_PAD_PTD11__SDHC0_DQS 0x10042
> > + MX8ULP_PAD_PTD1__SDHC0_CMD 0x3
> > + MX8ULP_PAD_PTD2__SDHC0_CLK 0x10002
> > + MX8ULP_PAD_PTD10__SDHC0_D0 0x3
> > + MX8ULP_PAD_PTD9__SDHC0_D1 0x3
> > + MX8ULP_PAD_PTD8__SDHC0_D2 0x3
> > + MX8ULP_PAD_PTD7__SDHC0_D3 0x3
> > + MX8ULP_PAD_PTD6__SDHC0_D4 0x3
> > + MX8ULP_PAD_PTD5__SDHC0_D5 0x3
> > + MX8ULP_PAD_PTD4__SDHC0_D6 0x3
> > + MX8ULP_PAD_PTD3__SDHC0_D7 0x3
> > + MX8ULP_PAD_PTD11__SDHC0_DQS 0x10002
> > >;
> > };
> > };
> > --
> > 2.37.1
> >
^ permalink raw reply [flat|nested] 16+ messages in thread* Re: [PATCH 09/10] arm64: dts: imx8ulp-evk: add 100MHz/200MHz pinctrl setting for eMMC
2023-07-24 6:51 ` Bough Chen
@ 2023-07-30 3:04 ` Shawn Guo
0 siblings, 0 replies; 16+ messages in thread
From: Shawn Guo @ 2023-07-30 3:04 UTC (permalink / raw)
To: Bough Chen
Cc: Peng Fan (OSS), robh+dt@kernel.org,
krzysztof.kozlowski+dt@linaro.org, s.hauer@pengutronix.de,
kernel@pengutronix.de, festevam@gmail.com, dl-linux-imx,
devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, Sherry Sun, Peng Fan
On Mon, Jul 24, 2023 at 06:51:17AM +0000, Bough Chen wrote:
> > -----Original Message-----
> > From: Shawn Guo <shawnguo@kernel.org>
> > Sent: 2023年7月18日 11:32
> > To: Peng Fan (OSS) <peng.fan@oss.nxp.com>
> > Cc: robh+dt@kernel.org; krzysztof.kozlowski+dt@linaro.org;
> > s.hauer@pengutronix.de; kernel@pengutronix.de; festevam@gmail.com;
> > dl-linux-imx <linux-imx@nxp.com>; devicetree@vger.kernel.org;
> > linux-arm-kernel@lists.infradead.org; linux-kernel@vger.kernel.org; Bough
> > Chen <haibo.chen@nxp.com>; Sherry Sun <sherry.sun@nxp.com>; Peng Fan
> > <peng.fan@nxp.com>
> > Subject: Re: [PATCH 09/10] arm64: dts: imx8ulp-evk: add 100MHz/200MHz
> > pinctrl setting for eMMC
> >
> > On Sun, Jun 25, 2023 at 08:42:37PM +0800, Peng Fan (OSS) wrote:
> > > From: Haibo Chen <haibo.chen@nxp.com>
> > >
> > > Add 100MHz and 200MHz pinctrl setting for eMMC, and enable 8 bit bus
> > > mode to config the eMMC work at HS400ES mode.
> > >
> > > Also update to use Standard Drive Strength for USDHC pad to get a
> > > better signal quality per Hardware team suggests.
> > >
> > > Reviewed-by: Sherry Sun <sherry.sun@nxp.com>
> > > Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
> > > Signed-off-by: Peng Fan <peng.fan@nxp.com>
> > > ---
> > > arch/arm64/boot/dts/freescale/imx8ulp-evk.dts | 26
> > > ++++++++++---------
> > > 1 file changed, 14 insertions(+), 12 deletions(-)
> > >
> > > diff --git a/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts
> > > b/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts
> > > index e459dc35e469..ab7af705bbca 100644
> > > --- a/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts
> > > +++ b/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts
> > > @@ -121,9 +121,11 @@ &lpuart5 {
> > > };
> > >
> > > &usdhc0 {
> > > - pinctrl-names = "default", "sleep";
> > > + pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
> > > pinctrl-0 = <&pinctrl_usdhc0>;
> > > pinctrl-1 = <&pinctrl_usdhc0>;
> > > + pinctrl-2 = <&pinctrl_usdhc0>;
> > > + pinctrl-3 = <&pinctrl_usdhc0>;
> >
> > All three speed modes use the same pinctrl?
>
> Yes, the IOMUX on imx8ulp do not support config different drive strength. So here use the same pinctrl.
Mention that in the commit log or with a comment would be helpful.
Shawn
^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH 10/10] arm64: dts: imx8ulp-evk: enable lpi2c7 bus
2023-06-25 12:42 [PATCH 00/10] arm64: dts: imx8ulp: add more nodes Peng Fan (OSS)
` (8 preceding siblings ...)
2023-06-25 12:42 ` [PATCH 09/10] arm64: dts: imx8ulp-evk: add 100MHz/200MHz pinctrl setting for eMMC Peng Fan (OSS)
@ 2023-06-25 12:42 ` Peng Fan (OSS)
9 siblings, 0 replies; 16+ messages in thread
From: Peng Fan (OSS) @ 2023-06-25 12:42 UTC (permalink / raw)
To: robh+dt, krzysztof.kozlowski+dt, shawnguo, s.hauer
Cc: kernel, festevam, linux-imx, devicetree, linux-arm-kernel,
linux-kernel, Haibo Chen, Clark Wang, Peng Fan
From: Haibo Chen <haibo.chen@nxp.com>
Enable lpi2c7 bus, and enable i2c IO expander.
Reviewed-by: Clark Wang <xiaoning.wang@nxp.com>
Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
arch/arm64/boot/dts/freescale/imx8ulp-evk.dts | 24 +++++++++++++++++++
1 file changed, 24 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts b/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts
index ab7af705bbca..785108c37210 100644
--- a/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts
+++ b/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts
@@ -120,6 +120,23 @@ &lpuart5 {
status = "okay";
};
+&lpi2c7 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clock-frequency = <400000>;
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&pinctrl_lpi2c7>;
+ pinctrl-1 = <&pinctrl_lpi2c7>;
+ status = "okay";
+
+ pcal6408: gpio@21 {
+ compatible = "nxp,pcal9554b";
+ reg = <0x21>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+};
+
&usdhc0 {
pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
pinctrl-0 = <&pinctrl_usdhc0>;
@@ -202,6 +219,13 @@ MX8ULP_PAD_PTF15__LPUART5_RX 0x3
>;
};
+ pinctrl_lpi2c7: lpi2c7grp {
+ fsl,pins = <
+ MX8ULP_PAD_PTE12__LPI2C7_SCL 0x20
+ MX8ULP_PAD_PTE13__LPI2C7_SDA 0x20
+ >;
+ };
+
pinctrl_usdhc0: usdhc0grp {
fsl,pins = <
MX8ULP_PAD_PTD1__SDHC0_CMD 0x3
--
2.37.1
^ permalink raw reply related [flat|nested] 16+ messages in thread