* [PATCH v2 0/2] RK3588 PCIe3 support
@ 2023-07-17 17:35 Sebastian Reichel
2023-07-17 17:35 ` [PATCH v2 1/2] dt-bindings: phy: rockchip: add RK3588 PCIe v3 phy Sebastian Reichel
` (3 more replies)
0 siblings, 4 replies; 12+ messages in thread
From: Sebastian Reichel @ 2023-07-17 17:35 UTC (permalink / raw)
To: linux-phy, linux-rockchip
Cc: Jingoo Han, Gustavo Pimentel, Bjorn Helgaas, Lorenzo Pieralisi,
Vinod Koul, Kishon Vijay Abraham I, Krzysztof Wilczyński,
Rob Herring, Serge Semin, Krzysztof Kozlowski, Conor Dooley,
Heiko Stuebner, Shawn Lin, Simon Xue, John Clark, Qu Wenruo,
devicetree, linux-pci, linux-kernel, linux-arm-kernel,
Sebastian Reichel, kernel
Hi,
This adds PCIe v3 support for RK3588. The series depends on the PCIe
v2 series [0], since the the same binding is used. It has been tested
on Rockchip EVB1 and Radxa Rock 5B.
Note, that the PCIe3 PHY driver is currently missing bifurcation
support for RK3588. Thus after this series only PCIe3x4 is usable
(in aggregated x4 mode) without adding support for the PHY's
"rockchip,pcie30-phymode" DT property, which allows configuring
how the lanes are distributed. Aggregated 3x4 mode seems to be the
most common configuration. Both EVB1 and Rock 5B use it, so I
cannot test anything else anyways.
[0] https://lore.kernel.org/all/20230717172651.64324-1-sebastian.reichel@collabora.com/
Changes since v1:
* https://lore.kernel.org/all/20230714175331.112923-1-sebastian.reichel@collabora.com/
* Collected Acked-by from Conor Dooley
* Dropped deprecated and useless num-ib-windows/num-ob-windows/num-viewport
properties from DT (Serge Semin)
-- Sebastian
Sebastian Reichel (2):
dt-bindings: phy: rockchip: add RK3588 PCIe v3 phy
arm64: dts: rockchip: rk3588: add PCIe3 support
.../bindings/phy/rockchip,pcie3-phy.yaml | 33 ++++-
arch/arm64/boot/dts/rockchip/rk3588.dtsi | 120 ++++++++++++++++++
2 files changed, 148 insertions(+), 5 deletions(-)
--
2.40.1
^ permalink raw reply [flat|nested] 12+ messages in thread* [PATCH v2 1/2] dt-bindings: phy: rockchip: add RK3588 PCIe v3 phy 2023-07-17 17:35 [PATCH v2 0/2] RK3588 PCIe3 support Sebastian Reichel @ 2023-07-17 17:35 ` Sebastian Reichel 2023-07-17 17:35 ` [PATCH v2 2/2] arm64: dts: rockchip: rk3588: add PCIe3 support Sebastian Reichel ` (2 subsequent siblings) 3 siblings, 0 replies; 12+ messages in thread From: Sebastian Reichel @ 2023-07-17 17:35 UTC (permalink / raw) To: linux-phy, linux-rockchip Cc: Jingoo Han, Gustavo Pimentel, Bjorn Helgaas, Lorenzo Pieralisi, Vinod Koul, Kishon Vijay Abraham I, Krzysztof Wilczyński, Rob Herring, Serge Semin, Krzysztof Kozlowski, Conor Dooley, Heiko Stuebner, Shawn Lin, Simon Xue, John Clark, Qu Wenruo, devicetree, linux-pci, linux-kernel, linux-arm-kernel, Sebastian Reichel, kernel, Conor Dooley When the RK3568 PCIe v3 PHY supported has been upstreamed, RK3588 support was included, but the DT binding does not reflect this. This adds the missing bits. Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com> --- .../bindings/phy/rockchip,pcie3-phy.yaml | 33 ++++++++++++++++--- 1 file changed, 28 insertions(+), 5 deletions(-) diff --git a/Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.yaml b/Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.yaml index 9f2d8d2cc7a5..c4fbffcde6e4 100644 --- a/Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.yaml +++ b/Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.yaml @@ -13,19 +13,18 @@ properties: compatible: enum: - rockchip,rk3568-pcie3-phy + - rockchip,rk3588-pcie3-phy reg: maxItems: 1 clocks: - minItems: 3 + minItems: 1 maxItems: 3 clock-names: - items: - - const: refclk_m - - const: refclk_n - - const: pclk + minItems: 1 + maxItems: 3 data-lanes: description: which lanes (by position) should be mapped to which @@ -61,6 +60,30 @@ required: - rockchip,phy-grf - "#phy-cells" +allOf: + - if: + properties: + compatible: + enum: + - rockchip,rk3588-pcie3-phy + then: + properties: + clocks: + maxItems: 1 + clock-names: + items: + - const: pclk + else: + properties: + clocks: + minItems: 3 + + clock-names: + items: + - const: refclk_m + - const: refclk_n + - const: pclk + additionalProperties: false examples: -- 2.40.1 ^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH v2 2/2] arm64: dts: rockchip: rk3588: add PCIe3 support 2023-07-17 17:35 [PATCH v2 0/2] RK3588 PCIe3 support Sebastian Reichel 2023-07-17 17:35 ` [PATCH v2 1/2] dt-bindings: phy: rockchip: add RK3588 PCIe v3 phy Sebastian Reichel @ 2023-07-17 17:35 ` Sebastian Reichel 2023-07-18 15:09 ` Liviu Dudau 2023-07-18 6:15 ` (subset) [PATCH v2 0/2] RK3588 " Vinod Koul 2023-07-24 19:12 ` Heiko Stuebner 3 siblings, 1 reply; 12+ messages in thread From: Sebastian Reichel @ 2023-07-17 17:35 UTC (permalink / raw) To: linux-phy, linux-rockchip Cc: Jingoo Han, Gustavo Pimentel, Bjorn Helgaas, Lorenzo Pieralisi, Vinod Koul, Kishon Vijay Abraham I, Krzysztof Wilczyński, Rob Herring, Serge Semin, Krzysztof Kozlowski, Conor Dooley, Heiko Stuebner, Shawn Lin, Simon Xue, John Clark, Qu Wenruo, devicetree, linux-pci, linux-kernel, linux-arm-kernel, Sebastian Reichel, kernel Add both PCIe3 controllers together with the shared PHY. Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com> --- arch/arm64/boot/dts/rockchip/rk3588.dtsi | 120 +++++++++++++++++++++++ 1 file changed, 120 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588.dtsi b/arch/arm64/boot/dts/rockchip/rk3588.dtsi index 88d702575db2..8f210f002fac 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588.dtsi @@ -7,6 +7,11 @@ #include "rk3588-pinctrl.dtsi" / { + pcie30_phy_grf: syscon@fd5b8000 { + compatible = "rockchip,rk3588-pcie3-phy-grf", "syscon"; + reg = <0x0 0xfd5b8000 0x0 0x10000>; + }; + pipe_phy1_grf: syscon@fd5c0000 { compatible = "rockchip,rk3588-pipe-phy-grf", "syscon"; reg = <0x0 0xfd5c0000 0x0 0x100>; @@ -80,6 +85,108 @@ i2s10_8ch: i2s@fde00000 { status = "disabled"; }; + pcie3x4: pcie@fe150000 { + compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie"; + #address-cells = <3>; + #size-cells = <2>; + bus-range = <0x00 0x0f>; + clocks = <&cru ACLK_PCIE_4L_MSTR>, <&cru ACLK_PCIE_4L_SLV>, + <&cru ACLK_PCIE_4L_DBI>, <&cru PCLK_PCIE_4L>, + <&cru CLK_PCIE_AUX0>, <&cru CLK_PCIE4L_PIPE>; + clock-names = "aclk_mst", "aclk_slv", + "aclk_dbi", "pclk", + "aux", "pipe"; + device_type = "pci"; + interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH 0>; + interrupt-names = "sys", "pmc", "msg", "legacy", "err"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie3x4_intc 0>, + <0 0 0 2 &pcie3x4_intc 1>, + <0 0 0 3 &pcie3x4_intc 2>, + <0 0 0 4 &pcie3x4_intc 3>; + linux,pci-domain = <0>; + max-link-speed = <3>; + msi-map = <0x0000 &its1 0x0000 0x1000>; + num-lanes = <4>; + phys = <&pcie30phy>; + phy-names = "pcie-phy"; + power-domains = <&power RK3588_PD_PCIE>; + ranges = <0x01000000 0x0 0xf0100000 0x0 0xf0100000 0x0 0x00100000>, + <0x02000000 0x0 0xf0200000 0x0 0xf0200000 0x0 0x00e00000>, + <0x03000000 0x0 0x40000000 0x9 0x00000000 0x0 0x40000000>; + reg = <0xa 0x40000000 0x0 0x00400000>, + <0x0 0xfe150000 0x0 0x00010000>, + <0x0 0xf0000000 0x0 0x00100000>; + reg-names = "dbi", "apb", "config"; + resets = <&cru SRST_PCIE0_POWER_UP>, <&cru SRST_P_PCIE0>; + reset-names = "pwr", "pipe"; + status = "disabled"; + + pcie3x4_intc: legacy-interrupt-controller { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-parent = <&gic>; + interrupts = <GIC_SPI 260 IRQ_TYPE_EDGE_RISING 0>; + }; + }; + + pcie3x2: pcie@fe160000 { + compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie"; + #address-cells = <3>; + #size-cells = <2>; + bus-range = <0x10 0x1f>; + clocks = <&cru ACLK_PCIE_2L_MSTR>, <&cru ACLK_PCIE_2L_SLV>, + <&cru ACLK_PCIE_2L_DBI>, <&cru PCLK_PCIE_2L>, + <&cru CLK_PCIE_AUX1>, <&cru CLK_PCIE2L_PIPE>; + clock-names = "aclk_mst", "aclk_slv", + "aclk_dbi", "pclk", + "aux", "pipe"; + device_type = "pci"; + interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH 0>; + interrupt-names = "sys", "pmc", "msg", "legacy", "err"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie3x2_intc 0>, + <0 0 0 2 &pcie3x2_intc 1>, + <0 0 0 3 &pcie3x2_intc 2>, + <0 0 0 4 &pcie3x2_intc 3>; + linux,pci-domain = <1>; + max-link-speed = <3>; + msi-map = <0x1000 &its1 0x1000 0x1000>; + num-lanes = <2>; + phys = <&pcie30phy>; + phy-names = "pcie-phy"; + power-domains = <&power RK3588_PD_PCIE>; + ranges = <0x01000000 0x0 0xf1100000 0x0 0xf1100000 0x0 0x00100000>, + <0x02000000 0x0 0xf1200000 0x0 0xf1200000 0x0 0x00e00000>, + <0x03000000 0x0 0x40000000 0x9 0x40000000 0x0 0x40000000>; + reg = <0xa 0x40400000 0x0 0x00400000>, + <0x0 0xfe160000 0x0 0x00010000>, + <0x0 0xf1000000 0x0 0x00100000>; + reg-names = "dbi", "apb", "config"; + resets = <&cru SRST_PCIE1_POWER_UP>, <&cru SRST_P_PCIE1>; + reset-names = "pwr", "pipe"; + status = "disabled"; + + pcie3x2_intc: legacy-interrupt-controller { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-parent = <&gic>; + interrupts = <GIC_SPI 255 IRQ_TYPE_EDGE_RISING 0>; + }; + }; + pcie2x1l0: pcie@fe170000 { compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie"; #address-cells = <3>; @@ -218,4 +325,17 @@ combphy1_ps: phy@fee10000 { rockchip,pipe-phy-grf = <&pipe_phy1_grf>; status = "disabled"; }; + + pcie30phy: phy@fee80000 { + compatible = "rockchip,rk3588-pcie3-phy"; + reg = <0x0 0xfee80000 0x0 0x20000>; + #phy-cells = <0>; + clocks = <&cru PCLK_PCIE_COMBO_PIPE_PHY>; + clock-names = "pclk"; + resets = <&cru SRST_PCIE30_PHY>; + reset-names = "phy"; + rockchip,pipe-grf = <&php_grf>; + rockchip,phy-grf = <&pcie30_phy_grf>; + status = "disabled"; + }; }; -- 2.40.1 ^ permalink raw reply related [flat|nested] 12+ messages in thread
* Re: [PATCH v2 2/2] arm64: dts: rockchip: rk3588: add PCIe3 support 2023-07-17 17:35 ` [PATCH v2 2/2] arm64: dts: rockchip: rk3588: add PCIe3 support Sebastian Reichel @ 2023-07-18 15:09 ` Liviu Dudau 2023-07-18 16:01 ` Sebastian Reichel 0 siblings, 1 reply; 12+ messages in thread From: Liviu Dudau @ 2023-07-18 15:09 UTC (permalink / raw) To: Sebastian Reichel Cc: linux-phy, linux-rockchip, Jingoo Han, Gustavo Pimentel, Bjorn Helgaas, Lorenzo Pieralisi, Vinod Koul, Kishon Vijay Abraham I, Krzysztof Wilczyński, Rob Herring, Serge Semin, Krzysztof Kozlowski, Conor Dooley, Heiko Stuebner, Shawn Lin, Simon Xue, John Clark, Qu Wenruo, devicetree, linux-pci, linux-kernel, linux-arm-kernel, kernel On Mon, Jul 17, 2023 at 07:35:12PM +0200, Sebastian Reichel wrote: > Add both PCIe3 controllers together with the shared PHY. > > Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com> > --- > arch/arm64/boot/dts/rockchip/rk3588.dtsi | 120 +++++++++++++++++++++++ > 1 file changed, 120 insertions(+) > > diff --git a/arch/arm64/boot/dts/rockchip/rk3588.dtsi b/arch/arm64/boot/dts/rockchip/rk3588.dtsi > index 88d702575db2..8f210f002fac 100644 > --- a/arch/arm64/boot/dts/rockchip/rk3588.dtsi > +++ b/arch/arm64/boot/dts/rockchip/rk3588.dtsi > @@ -7,6 +7,11 @@ > #include "rk3588-pinctrl.dtsi" > > / { > + pcie30_phy_grf: syscon@fd5b8000 { > + compatible = "rockchip,rk3588-pcie3-phy-grf", "syscon"; > + reg = <0x0 0xfd5b8000 0x0 0x10000>; > + }; > + > pipe_phy1_grf: syscon@fd5c0000 { > compatible = "rockchip,rk3588-pipe-phy-grf", "syscon"; > reg = <0x0 0xfd5c0000 0x0 0x100>; Hi Sebastian, What tree is based this on? Even after applying your PCIe2 series I don't have the above node so the patch doesn't apply to mainline. Best regards, Liviu > @@ -80,6 +85,108 @@ i2s10_8ch: i2s@fde00000 { > status = "disabled"; > }; > > + pcie3x4: pcie@fe150000 { > + compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie"; > + #address-cells = <3>; > + #size-cells = <2>; > + bus-range = <0x00 0x0f>; > + clocks = <&cru ACLK_PCIE_4L_MSTR>, <&cru ACLK_PCIE_4L_SLV>, > + <&cru ACLK_PCIE_4L_DBI>, <&cru PCLK_PCIE_4L>, > + <&cru CLK_PCIE_AUX0>, <&cru CLK_PCIE4L_PIPE>; > + clock-names = "aclk_mst", "aclk_slv", > + "aclk_dbi", "pclk", > + "aux", "pipe"; > + device_type = "pci"; > + interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH 0>, > + <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH 0>, > + <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH 0>, > + <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH 0>, > + <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH 0>; > + interrupt-names = "sys", "pmc", "msg", "legacy", "err"; > + #interrupt-cells = <1>; > + interrupt-map-mask = <0 0 0 7>; > + interrupt-map = <0 0 0 1 &pcie3x4_intc 0>, > + <0 0 0 2 &pcie3x4_intc 1>, > + <0 0 0 3 &pcie3x4_intc 2>, > + <0 0 0 4 &pcie3x4_intc 3>; > + linux,pci-domain = <0>; > + max-link-speed = <3>; > + msi-map = <0x0000 &its1 0x0000 0x1000>; > + num-lanes = <4>; > + phys = <&pcie30phy>; > + phy-names = "pcie-phy"; > + power-domains = <&power RK3588_PD_PCIE>; > + ranges = <0x01000000 0x0 0xf0100000 0x0 0xf0100000 0x0 0x00100000>, > + <0x02000000 0x0 0xf0200000 0x0 0xf0200000 0x0 0x00e00000>, > + <0x03000000 0x0 0x40000000 0x9 0x00000000 0x0 0x40000000>; > + reg = <0xa 0x40000000 0x0 0x00400000>, > + <0x0 0xfe150000 0x0 0x00010000>, > + <0x0 0xf0000000 0x0 0x00100000>; > + reg-names = "dbi", "apb", "config"; > + resets = <&cru SRST_PCIE0_POWER_UP>, <&cru SRST_P_PCIE0>; > + reset-names = "pwr", "pipe"; > + status = "disabled"; > + > + pcie3x4_intc: legacy-interrupt-controller { > + interrupt-controller; > + #address-cells = <0>; > + #interrupt-cells = <1>; > + interrupt-parent = <&gic>; > + interrupts = <GIC_SPI 260 IRQ_TYPE_EDGE_RISING 0>; > + }; > + }; > + > + pcie3x2: pcie@fe160000 { > + compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie"; > + #address-cells = <3>; > + #size-cells = <2>; > + bus-range = <0x10 0x1f>; > + clocks = <&cru ACLK_PCIE_2L_MSTR>, <&cru ACLK_PCIE_2L_SLV>, > + <&cru ACLK_PCIE_2L_DBI>, <&cru PCLK_PCIE_2L>, > + <&cru CLK_PCIE_AUX1>, <&cru CLK_PCIE2L_PIPE>; > + clock-names = "aclk_mst", "aclk_slv", > + "aclk_dbi", "pclk", > + "aux", "pipe"; > + device_type = "pci"; > + interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH 0>, > + <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH 0>, > + <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH 0>, > + <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH 0>, > + <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH 0>; > + interrupt-names = "sys", "pmc", "msg", "legacy", "err"; > + #interrupt-cells = <1>; > + interrupt-map-mask = <0 0 0 7>; > + interrupt-map = <0 0 0 1 &pcie3x2_intc 0>, > + <0 0 0 2 &pcie3x2_intc 1>, > + <0 0 0 3 &pcie3x2_intc 2>, > + <0 0 0 4 &pcie3x2_intc 3>; > + linux,pci-domain = <1>; > + max-link-speed = <3>; > + msi-map = <0x1000 &its1 0x1000 0x1000>; > + num-lanes = <2>; > + phys = <&pcie30phy>; > + phy-names = "pcie-phy"; > + power-domains = <&power RK3588_PD_PCIE>; > + ranges = <0x01000000 0x0 0xf1100000 0x0 0xf1100000 0x0 0x00100000>, > + <0x02000000 0x0 0xf1200000 0x0 0xf1200000 0x0 0x00e00000>, > + <0x03000000 0x0 0x40000000 0x9 0x40000000 0x0 0x40000000>; > + reg = <0xa 0x40400000 0x0 0x00400000>, > + <0x0 0xfe160000 0x0 0x00010000>, > + <0x0 0xf1000000 0x0 0x00100000>; > + reg-names = "dbi", "apb", "config"; > + resets = <&cru SRST_PCIE1_POWER_UP>, <&cru SRST_P_PCIE1>; > + reset-names = "pwr", "pipe"; > + status = "disabled"; > + > + pcie3x2_intc: legacy-interrupt-controller { > + interrupt-controller; > + #address-cells = <0>; > + #interrupt-cells = <1>; > + interrupt-parent = <&gic>; > + interrupts = <GIC_SPI 255 IRQ_TYPE_EDGE_RISING 0>; > + }; > + }; > + > pcie2x1l0: pcie@fe170000 { > compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie"; > #address-cells = <3>; > @@ -218,4 +325,17 @@ combphy1_ps: phy@fee10000 { > rockchip,pipe-phy-grf = <&pipe_phy1_grf>; > status = "disabled"; > }; > + > + pcie30phy: phy@fee80000 { > + compatible = "rockchip,rk3588-pcie3-phy"; > + reg = <0x0 0xfee80000 0x0 0x20000>; > + #phy-cells = <0>; > + clocks = <&cru PCLK_PCIE_COMBO_PIPE_PHY>; > + clock-names = "pclk"; > + resets = <&cru SRST_PCIE30_PHY>; > + reset-names = "phy"; > + rockchip,pipe-grf = <&php_grf>; > + rockchip,phy-grf = <&pcie30_phy_grf>; > + status = "disabled"; > + }; > }; > -- > 2.40.1 > > > _______________________________________________ > Linux-rockchip mailing list > Linux-rockchip@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-rockchip -- Everyone who uses computers frequently has had, from time to time, a mad desire to attack the precocious abacus with an axe. -- John D. Clark, Ignition! ^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH v2 2/2] arm64: dts: rockchip: rk3588: add PCIe3 support 2023-07-18 15:09 ` Liviu Dudau @ 2023-07-18 16:01 ` Sebastian Reichel 2023-07-18 19:38 ` Liviu Dudau 0 siblings, 1 reply; 12+ messages in thread From: Sebastian Reichel @ 2023-07-18 16:01 UTC (permalink / raw) To: Liviu Dudau Cc: linux-phy, linux-rockchip, Jingoo Han, Gustavo Pimentel, Bjorn Helgaas, Lorenzo Pieralisi, Vinod Koul, Kishon Vijay Abraham I, Krzysztof Wilczyński, Rob Herring, Serge Semin, Krzysztof Kozlowski, Conor Dooley, Heiko Stuebner, Shawn Lin, Simon Xue, John Clark, Qu Wenruo, devicetree, linux-pci, linux-kernel, linux-arm-kernel, kernel [-- Attachment #1: Type: text/plain, Size: 1406 bytes --] Hi Liviu, On Tue, Jul 18, 2023 at 04:09:53PM +0100, Liviu Dudau wrote: > On Mon, Jul 17, 2023 at 07:35:12PM +0200, Sebastian Reichel wrote: > > Add both PCIe3 controllers together with the shared PHY. > > > > Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com> > > --- > > arch/arm64/boot/dts/rockchip/rk3588.dtsi | 120 +++++++++++++++++++++++ > > 1 file changed, 120 insertions(+) > > > > diff --git a/arch/arm64/boot/dts/rockchip/rk3588.dtsi b/arch/arm64/boot/dts/rockchip/rk3588.dtsi > > index 88d702575db2..8f210f002fac 100644 > > --- a/arch/arm64/boot/dts/rockchip/rk3588.dtsi > > +++ b/arch/arm64/boot/dts/rockchip/rk3588.dtsi > > @@ -7,6 +7,11 @@ > > #include "rk3588-pinctrl.dtsi" > > > > / { > > + pcie30_phy_grf: syscon@fd5b8000 { > > + compatible = "rockchip,rk3588-pcie3-phy-grf", "syscon"; > > + reg = <0x0 0xfd5b8000 0x0 0x10000>; > > + }; > > + > > pipe_phy1_grf: syscon@fd5c0000 { > > compatible = "rockchip,rk3588-pipe-phy-grf", "syscon"; > > reg = <0x0 0xfd5c0000 0x0 0x100>; > > What tree is based this on? Even after applying your PCIe2 series I don't have the above > node so the patch doesn't apply to mainline. You are missing naneng-combphy support: https://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip.git/commit/?h=v6.6-armsoc/dts64&id=6ebd55b3bba383e0523b0c014f17c97f3ce80708 -- Sebastian [-- Attachment #2: signature.asc --] [-- Type: application/pgp-signature, Size: 833 bytes --] ^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH v2 2/2] arm64: dts: rockchip: rk3588: add PCIe3 support 2023-07-18 16:01 ` Sebastian Reichel @ 2023-07-18 19:38 ` Liviu Dudau 2023-07-18 21:06 ` Sebastian Reichel 0 siblings, 1 reply; 12+ messages in thread From: Liviu Dudau @ 2023-07-18 19:38 UTC (permalink / raw) To: Sebastian Reichel Cc: linux-phy, linux-rockchip, Jingoo Han, Gustavo Pimentel, Bjorn Helgaas, Lorenzo Pieralisi, Vinod Koul, Kishon Vijay Abraham I, Krzysztof Wilczyński, Rob Herring, Serge Semin, Krzysztof Kozlowski, Conor Dooley, Heiko Stuebner, Shawn Lin, Simon Xue, John Clark, Qu Wenruo, devicetree, linux-pci, linux-kernel, linux-arm-kernel, kernel On Tue, Jul 18, 2023 at 06:01:37PM +0200, Sebastian Reichel wrote: > Hi Liviu, > > On Tue, Jul 18, 2023 at 04:09:53PM +0100, Liviu Dudau wrote: > > On Mon, Jul 17, 2023 at 07:35:12PM +0200, Sebastian Reichel wrote: > > > Add both PCIe3 controllers together with the shared PHY. > > > > > > Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com> > > > --- > > > arch/arm64/boot/dts/rockchip/rk3588.dtsi | 120 +++++++++++++++++++++++ > > > 1 file changed, 120 insertions(+) > > > > > > diff --git a/arch/arm64/boot/dts/rockchip/rk3588.dtsi b/arch/arm64/boot/dts/rockchip/rk3588.dtsi > > > index 88d702575db2..8f210f002fac 100644 > > > --- a/arch/arm64/boot/dts/rockchip/rk3588.dtsi > > > +++ b/arch/arm64/boot/dts/rockchip/rk3588.dtsi > > > @@ -7,6 +7,11 @@ > > > #include "rk3588-pinctrl.dtsi" > > > > > > / { > > > + pcie30_phy_grf: syscon@fd5b8000 { > > > + compatible = "rockchip,rk3588-pcie3-phy-grf", "syscon"; > > > + reg = <0x0 0xfd5b8000 0x0 0x10000>; > > > + }; > > > + > > > pipe_phy1_grf: syscon@fd5c0000 { > > > compatible = "rockchip,rk3588-pipe-phy-grf", "syscon"; > > > reg = <0x0 0xfd5c0000 0x0 0x100>; > > > > What tree is based this on? Even after applying your PCIe2 series I don't have the above > > node so the patch doesn't apply to mainline. > > You are missing naneng-combphy support: > > https://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip.git/commit/?h=v6.6-armsoc/dts64&id=6ebd55b3bba383e0523b0c014f17c97f3ce80708 Thanks! It looks like the PCIe2 commit that adds support to rk3588(s).dtsi files is also missing an #include <dt-bindings/phy/phy.h> for the PHY_TYPE_PCIE use, otherwise the DTS fail to compile. Best regards, Liviu > > -- Sebastian -- Everyone who uses computers frequently has had, from time to time, a mad desire to attack the precocious abacus with an axe. -- John D. Clark, Ignition! ^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH v2 2/2] arm64: dts: rockchip: rk3588: add PCIe3 support 2023-07-18 19:38 ` Liviu Dudau @ 2023-07-18 21:06 ` Sebastian Reichel 2023-07-19 9:41 ` Liviu Dudau 0 siblings, 1 reply; 12+ messages in thread From: Sebastian Reichel @ 2023-07-18 21:06 UTC (permalink / raw) To: Liviu Dudau Cc: linux-phy, linux-rockchip, Jingoo Han, Gustavo Pimentel, Bjorn Helgaas, Lorenzo Pieralisi, Vinod Koul, Kishon Vijay Abraham I, Krzysztof Wilczyński, Rob Herring, Serge Semin, Krzysztof Kozlowski, Conor Dooley, Heiko Stuebner, Shawn Lin, Simon Xue, John Clark, Qu Wenruo, devicetree, linux-pci, linux-kernel, linux-arm-kernel, kernel [-- Attachment #1: Type: text/plain, Size: 1228 bytes --] Hi, On Tue, Jul 18, 2023 at 08:38:36PM +0100, Liviu Dudau wrote: > On Tue, Jul 18, 2023 at 06:01:37PM +0200, Sebastian Reichel wrote: > > On Tue, Jul 18, 2023 at 04:09:53PM +0100, Liviu Dudau wrote: > > > On Mon, Jul 17, 2023 at 07:35:12PM +0200, Sebastian Reichel wrote: > > > > pipe_phy1_grf: syscon@fd5c0000 { > > > > compatible = "rockchip,rk3588-pipe-phy-grf", "syscon"; > > > > reg = <0x0 0xfd5c0000 0x0 0x100>; > > > > > > What tree is based this on? Even after applying your PCIe2 series I don't have the above > > > node so the patch doesn't apply to mainline. > > > > You are missing naneng-combphy support: > > > > https://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip.git/commit/?h=v6.6-armsoc/dts64&id=6ebd55b3bba383e0523b0c014f17c97f3ce80708 > > Thanks! It looks like the PCIe2 commit that adds support to rk3588(s).dtsi > files is also missing an #include <dt-bindings/phy/phy.h> for the PHY_TYPE_PCIE > use, otherwise the DTS fail to compile. Yes, that's also already in linux-next: https://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip.git/commit/?h=v6.6-armsoc/dts64&id=34d6c15d8e86256ef2456c604b1c8d8242720871 Greetings, -- Sebastian [-- Attachment #2: signature.asc --] [-- Type: application/pgp-signature, Size: 833 bytes --] ^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH v2 2/2] arm64: dts: rockchip: rk3588: add PCIe3 support 2023-07-18 21:06 ` Sebastian Reichel @ 2023-07-19 9:41 ` Liviu Dudau 0 siblings, 0 replies; 12+ messages in thread From: Liviu Dudau @ 2023-07-19 9:41 UTC (permalink / raw) To: Sebastian Reichel Cc: linux-phy, linux-rockchip, Jingoo Han, Gustavo Pimentel, Bjorn Helgaas, Lorenzo Pieralisi, Vinod Koul, Kishon Vijay Abraham I, Krzysztof Wilczyński, Rob Herring, Serge Semin, Krzysztof Kozlowski, Conor Dooley, Heiko Stuebner, Shawn Lin, Simon Xue, John Clark, Qu Wenruo, devicetree, linux-pci, linux-kernel, linux-arm-kernel, kernel Hi Sebastian, On Tue, Jul 18, 2023 at 11:06:01PM +0200, Sebastian Reichel wrote: > Hi, > > On Tue, Jul 18, 2023 at 08:38:36PM +0100, Liviu Dudau wrote: > > On Tue, Jul 18, 2023 at 06:01:37PM +0200, Sebastian Reichel wrote: > > > On Tue, Jul 18, 2023 at 04:09:53PM +0100, Liviu Dudau wrote: > > > > On Mon, Jul 17, 2023 at 07:35:12PM +0200, Sebastian Reichel wrote: > > > > > pipe_phy1_grf: syscon@fd5c0000 { > > > > > compatible = "rockchip,rk3588-pipe-phy-grf", "syscon"; > > > > > reg = <0x0 0xfd5c0000 0x0 0x100>; > > > > > > > > What tree is based this on? Even after applying your PCIe2 series I don't have the above > > > > node so the patch doesn't apply to mainline. > > > > > > You are missing naneng-combphy support: > > > > > > https://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip.git/commit/?h=v6.6-armsoc/dts64&id=6ebd55b3bba383e0523b0c014f17c97f3ce80708 > > > > Thanks! It looks like the PCIe2 commit that adds support to rk3588(s).dtsi > > files is also missing an #include <dt-bindings/phy/phy.h> for the PHY_TYPE_PCIE > > use, otherwise the DTS fail to compile. > > Yes, that's also already in linux-next: > > https://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip.git/commit/?h=v6.6-armsoc/dts64&id=34d6c15d8e86256ef2456c604b1c8d8242720871 I'm reading that as: "relevant patch that this series depends on has already been added to the tree that's going to pull this PCIe2 series so all will be good". Otherwise I think there should be some mention in the cover letter about dependencies, so that people like me don't report issues just because they are not using the linux-rockchip tree by default. Many thanks for the quick answers and the links to fix my tree. Best regards, Liviu > > Greetings, > > -- Sebastian -- Everyone who uses computers frequently has had, from time to time, a mad desire to attack the precocious abacus with an axe. -- John D. Clark, Ignition! ^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: (subset) [PATCH v2 0/2] RK3588 PCIe3 support 2023-07-17 17:35 [PATCH v2 0/2] RK3588 PCIe3 support Sebastian Reichel 2023-07-17 17:35 ` [PATCH v2 1/2] dt-bindings: phy: rockchip: add RK3588 PCIe v3 phy Sebastian Reichel 2023-07-17 17:35 ` [PATCH v2 2/2] arm64: dts: rockchip: rk3588: add PCIe3 support Sebastian Reichel @ 2023-07-18 6:15 ` Vinod Koul 2023-07-24 19:12 ` Heiko Stuebner 3 siblings, 0 replies; 12+ messages in thread From: Vinod Koul @ 2023-07-18 6:15 UTC (permalink / raw) To: linux-phy, linux-rockchip, Sebastian Reichel Cc: Jingoo Han, Gustavo Pimentel, Bjorn Helgaas, Lorenzo Pieralisi, Kishon Vijay Abraham I, Krzysztof Wilczyński, Rob Herring, Serge Semin, Krzysztof Kozlowski, Conor Dooley, Heiko Stuebner, Shawn Lin, Simon Xue, John Clark, Qu Wenruo, devicetree, linux-pci, linux-kernel, linux-arm-kernel, kernel On Mon, 17 Jul 2023 19:35:10 +0200, Sebastian Reichel wrote: > This adds PCIe v3 support for RK3588. The series depends on the PCIe > v2 series [0], since the the same binding is used. It has been tested > on Rockchip EVB1 and Radxa Rock 5B. > > Note, that the PCIe3 PHY driver is currently missing bifurcation > support for RK3588. Thus after this series only PCIe3x4 is usable > (in aggregated x4 mode) without adding support for the PHY's > "rockchip,pcie30-phymode" DT property, which allows configuring > how the lanes are distributed. Aggregated 3x4 mode seems to be the > most common configuration. Both EVB1 and Rock 5B use it, so I > cannot test anything else anyways. > > [...] Applied, thanks! [1/2] dt-bindings: phy: rockchip: add RK3588 PCIe v3 phy commit: f66782cff479807ad7e98f0cf6a0c0babfe0159b Best regards, -- ~Vinod ^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: (subset) [PATCH v2 0/2] RK3588 PCIe3 support 2023-07-17 17:35 [PATCH v2 0/2] RK3588 PCIe3 support Sebastian Reichel ` (2 preceding siblings ...) 2023-07-18 6:15 ` (subset) [PATCH v2 0/2] RK3588 " Vinod Koul @ 2023-07-24 19:12 ` Heiko Stuebner 2023-07-24 19:22 ` Sebastian Reichel 3 siblings, 1 reply; 12+ messages in thread From: Heiko Stuebner @ 2023-07-24 19:12 UTC (permalink / raw) To: Sebastian Reichel, linux-phy, linux-rockchip Cc: Heiko Stuebner, linux-arm-kernel, Qu Wenruo, Rob Herring, Krzysztof Wilczyński, Simon Xue, linux-kernel, Lorenzo Pieralisi, devicetree, Jingoo Han, Gustavo Pimentel, linux-pci, John Clark, Krzysztof Kozlowski, Bjorn Helgaas, Kishon Vijay Abraham I, Serge Semin, kernel, Vinod Koul, Shawn Lin, Conor Dooley On Mon, 17 Jul 2023 19:35:10 +0200, Sebastian Reichel wrote: > This adds PCIe v3 support for RK3588. The series depends on the PCIe > v2 series [0], since the the same binding is used. It has been tested > on Rockchip EVB1 and Radxa Rock 5B. > > Note, that the PCIe3 PHY driver is currently missing bifurcation > support for RK3588. Thus after this series only PCIe3x4 is usable > (in aggregated x4 mode) without adding support for the PHY's > "rockchip,pcie30-phymode" DT property, which allows configuring > how the lanes are distributed. Aggregated 3x4 mode seems to be the > most common configuration. Both EVB1 and Rock 5B use it, so I > cannot test anything else anyways. > > [...] Applied, thanks! [2/2] arm64: dts: rockchip: rk3588: add PCIe3 support commit: 0acf4fa7f187cd7e3dad93f1ee14e9509687621e Best regards, -- Heiko Stuebner <heiko@sntech.de> ^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: (subset) [PATCH v2 0/2] RK3588 PCIe3 support 2023-07-24 19:12 ` Heiko Stuebner @ 2023-07-24 19:22 ` Sebastian Reichel 2023-07-25 18:06 ` Heiko Stuebner 0 siblings, 1 reply; 12+ messages in thread From: Sebastian Reichel @ 2023-07-24 19:22 UTC (permalink / raw) To: Heiko Stuebner Cc: linux-phy, linux-rockchip, linux-arm-kernel, Qu Wenruo, Rob Herring, Krzysztof Wilczyński, Simon Xue, linux-kernel, Lorenzo Pieralisi, devicetree, Jingoo Han, Gustavo Pimentel, linux-pci, John Clark, Krzysztof Kozlowski, Bjorn Helgaas, Kishon Vijay Abraham I, Serge Semin, kernel, Vinod Koul, Shawn Lin, Conor Dooley [-- Attachment #1: Type: text/plain, Size: 1191 bytes --] Hi Heiko, On Mon, Jul 24, 2023 at 09:12:35PM +0200, Heiko Stuebner wrote: > On Mon, 17 Jul 2023 19:35:10 +0200, Sebastian Reichel wrote: > > This adds PCIe v3 support for RK3588. The series depends on the PCIe > > v2 series [0], since the the same binding is used. It has been tested > > on Rockchip EVB1 and Radxa Rock 5B. > > > > Note, that the PCIe3 PHY driver is currently missing bifurcation > > support for RK3588. Thus after this series only PCIe3x4 is usable > > (in aggregated x4 mode) without adding support for the PHY's > > "rockchip,pcie30-phymode" DT property, which allows configuring > > how the lanes are distributed. Aggregated 3x4 mode seems to be the > > most common configuration. Both EVB1 and Rock 5B use it, so I > > cannot test anything else anyways. > > > > [...] > > Applied, thanks! > > [2/2] arm64: dts: rockchip: rk3588: add PCIe3 support > commit: 0acf4fa7f187cd7e3dad93f1ee14e9509687621e Applying this without the PCIe 2 series being applied introduces warnings for the RK3588 dtbs_check, as mentioned in the second setence of the text you quoted :) (FWIW RK356x already has the same warnings, though) -- Sebastian [-- Attachment #2: signature.asc --] [-- Type: application/pgp-signature, Size: 833 bytes --] ^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: (subset) [PATCH v2 0/2] RK3588 PCIe3 support 2023-07-24 19:22 ` Sebastian Reichel @ 2023-07-25 18:06 ` Heiko Stuebner 0 siblings, 0 replies; 12+ messages in thread From: Heiko Stuebner @ 2023-07-25 18:06 UTC (permalink / raw) To: Sebastian Reichel Cc: linux-phy, linux-rockchip, linux-arm-kernel, Qu Wenruo, Rob Herring, Krzysztof Wilczyński, Simon Xue, linux-kernel, Lorenzo Pieralisi, devicetree, Jingoo Han, Gustavo Pimentel, linux-pci, John Clark, Krzysztof Kozlowski, Bjorn Helgaas, Kishon Vijay Abraham I, Serge Semin, kernel, Vinod Koul, Shawn Lin, Conor Dooley Am Montag, 24. Juli 2023, 21:22:23 CEST schrieb Sebastian Reichel: > Hi Heiko, > > On Mon, Jul 24, 2023 at 09:12:35PM +0200, Heiko Stuebner wrote: > > On Mon, 17 Jul 2023 19:35:10 +0200, Sebastian Reichel wrote: > > > This adds PCIe v3 support for RK3588. The series depends on the PCIe > > > v2 series [0], since the the same binding is used. It has been tested > > > on Rockchip EVB1 and Radxa Rock 5B. > > > > > > Note, that the PCIe3 PHY driver is currently missing bifurcation > > > support for RK3588. Thus after this series only PCIe3x4 is usable > > > (in aggregated x4 mode) without adding support for the PHY's > > > "rockchip,pcie30-phymode" DT property, which allows configuring > > > how the lanes are distributed. Aggregated 3x4 mode seems to be the > > > most common configuration. Both EVB1 and Rock 5B use it, so I > > > cannot test anything else anyways. > > > > > > [...] > > > > Applied, thanks! > > > > [2/2] arm64: dts: rockchip: rk3588: add PCIe3 support > > commit: 0acf4fa7f187cd7e3dad93f1ee14e9509687621e > > Applying this without the PCIe 2 series being applied introduces > warnings for the RK3588 dtbs_check, as mentioned in the second > setence of the text you quoted :) > > (FWIW RK356x already has the same warnings, though) darn, I didn't do a full binding check, only a "compiles" check after applying. We're at rc3 now, so I would hope that the pcie2 binding changes get applied soon'ish so I can then also pick up the dts change from there. Heiko ^ permalink raw reply [flat|nested] 12+ messages in thread
end of thread, other threads:[~2023-07-25 18:07 UTC | newest] Thread overview: 12+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2023-07-17 17:35 [PATCH v2 0/2] RK3588 PCIe3 support Sebastian Reichel 2023-07-17 17:35 ` [PATCH v2 1/2] dt-bindings: phy: rockchip: add RK3588 PCIe v3 phy Sebastian Reichel 2023-07-17 17:35 ` [PATCH v2 2/2] arm64: dts: rockchip: rk3588: add PCIe3 support Sebastian Reichel 2023-07-18 15:09 ` Liviu Dudau 2023-07-18 16:01 ` Sebastian Reichel 2023-07-18 19:38 ` Liviu Dudau 2023-07-18 21:06 ` Sebastian Reichel 2023-07-19 9:41 ` Liviu Dudau 2023-07-18 6:15 ` (subset) [PATCH v2 0/2] RK3588 " Vinod Koul 2023-07-24 19:12 ` Heiko Stuebner 2023-07-24 19:22 ` Sebastian Reichel 2023-07-25 18:06 ` Heiko Stuebner
This is a public inbox, see mirroring instructions for how to clone and mirror all data and code used for this inbox; as well as URLs for NNTP newsgroup(s).