[PATCH v9 1/4] dt-bindings: PCI: qcom: ep: Add interconnects path

[PATCH v9 1/4] dt-bindings: PCI: qcom: ep: Add interconnects path

[Krishna chaitanya chundru]

Some platforms may not boot if a device driver doesn't
initialize the interconnect path. Mostly it is handled
by the bootloader but we have starting to see cases
where bootloader simply ignores them.

Add the "pcie-mem" & "cpu-pcie" interconnect path as a required
property to the bindings.

Signed-off-by: Krishna chaitanya chundru <quic_krichai@quicinc.com>
Acked-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
---
 Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml
index 8111122..e553341 100644
--- a/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml
+++ b/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml
@@ -71,6 +71,14 @@ properties:
     description: GPIO used as WAKE# output signal
     maxItems: 1
 
+  interconnects:
+    maxItems: 2
+
+  interconnect-names:
+    items:
+      - const: pcie-mem
+      - const: cpu-pcie
+
   resets:
     maxItems: 1
 
@@ -98,6 +106,8 @@ required:
   - interrupts
   - interrupt-names
   - reset-gpios
+  - interconnects
+  - interconnect-names
   - resets
   - reset-names
   - power-domains
@@ -167,7 +177,9 @@ examples:
   - |
     #include <dt-bindings/clock/qcom,gcc-sdx55.h>
     #include <dt-bindings/gpio/gpio.h>
+    #include <dt-bindings/interconnect/qcom,sdx55.h>
     #include <dt-bindings/interrupt-controller/arm-gic.h>
+
     pcie_ep: pcie-ep@1c00000 {
         compatible = "qcom,sdx55-pcie-ep";
         reg = <0x01c00000 0x3000>,
@@ -194,6 +206,9 @@ examples:
         interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
                      <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
         interrupt-names = "global", "doorbell";
+        interconnects = <&system_noc MASTER_PCIE &mc_virt SLAVE_EBI_CH0>,
+                        <&mem_noc MASTER_AMPSS_M0 &system_noc SLAVE_PCIE_0>;
+        interconnect-names = "pcie-mem", "cpu-pcie";
         reset-gpios = <&tlmm 57 GPIO_ACTIVE_LOW>;
         wake-gpios = <&tlmm 53 GPIO_ACTIVE_LOW>;
         resets = <&gcc GCC_PCIE_BCR>;
-- 
2.7.4

[PATCH v9 2/4] arm: dts: qcom: sdx65: Add PCIe interconnect path

[Krishna chaitanya chundru]

Add pcie-mem & cpu-pcie interconnect path to sdx65 platform.

Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Krishna chaitanya chundru <quic_krichai@quicinc.com>
---
 arch/arm/boot/dts/qcom/qcom-sdx65.dtsi | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/arch/arm/boot/dts/qcom/qcom-sdx65.dtsi b/arch/arm/boot/dts/qcom/qcom-sdx65.dtsi
index 1a35830..69fe7e5 100644
--- a/arch/arm/boot/dts/qcom/qcom-sdx65.dtsi
+++ b/arch/arm/boot/dts/qcom/qcom-sdx65.dtsi
@@ -332,6 +332,10 @@
 				     <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
 			interrupt-names = "global", "doorbell";
 
+			interconnects = <&system_noc MASTER_PCIE_0 &mc_virt SLAVE_EBI1>,
+					<&mem_noc MASTER_APPSS_PROC &system_noc SLAVE_PCIE_0>;
+			interconnect-names = "pcie-mem", "cpu-pcie";
+
 			resets = <&gcc GCC_PCIE_BCR>;
 			reset-names = "core";
 
-- 
2.7.4

[PATCH v9 3/4] arm: dts: qcom: sdx55: Add CPU PCIe interconnect path

[Krishna chaitanya chundru]

Add cpu-pcie interconnect path to sdx65 platform.

Signed-off-by: Krishna chaitanya chundru <quic_krichai@quicinc.com>
---
 arch/arm/boot/dts/qcom/qcom-sdx55.dtsi | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/arch/arm/boot/dts/qcom/qcom-sdx55.dtsi b/arch/arm/boot/dts/qcom/qcom-sdx55.dtsi
index df3cd9c..a7c0c26 100644
--- a/arch/arm/boot/dts/qcom/qcom-sdx55.dtsi
+++ b/arch/arm/boot/dts/qcom/qcom-sdx55.dtsi
@@ -422,8 +422,9 @@
 			interrupt-names = "global",
 					  "doorbell";
 
-			interconnects = <&system_noc MASTER_PCIE &mc_virt SLAVE_EBI_CH0>;
-			interconnect-names = "pcie-mem";
+			interconnects = <&system_noc MASTER_PCIE &mc_virt SLAVE_EBI_CH0>,
+					<&mem_noc MASTER_AMPSS_M0 &system_noc SLAVE_PCIE_0>;
+			interconnect-names = "pcie-mem", "cpu-pcie";
 
 			resets = <&gcc GCC_PCIE_BCR>;
 			reset-names = "core";
-- 
2.7.4

Re: [PATCH v9 3/4] arm: dts: qcom: sdx55: Add CPU PCIe interconnect path

[Manivannan Sadhasivam]

On Tue, Jul 18, 2023 at 08:50:44PM +0530, Krishna chaitanya chundru wrote:
> Add cpu-pcie interconnect path to sdx65 platform.

sdx55 and please mention "PCIe RC". Perhaps you should also add "missing"?

- Mani

> 
> Signed-off-by: Krishna chaitanya chundru <quic_krichai@quicinc.com>
> ---
>  arch/arm/boot/dts/qcom/qcom-sdx55.dtsi | 5 +++--
>  1 file changed, 3 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/arm/boot/dts/qcom/qcom-sdx55.dtsi b/arch/arm/boot/dts/qcom/qcom-sdx55.dtsi
> index df3cd9c..a7c0c26 100644
> --- a/arch/arm/boot/dts/qcom/qcom-sdx55.dtsi
> +++ b/arch/arm/boot/dts/qcom/qcom-sdx55.dtsi
> @@ -422,8 +422,9 @@
>  			interrupt-names = "global",
>  					  "doorbell";
>  
> -			interconnects = <&system_noc MASTER_PCIE &mc_virt SLAVE_EBI_CH0>;
> -			interconnect-names = "pcie-mem";
> +			interconnects = <&system_noc MASTER_PCIE &mc_virt SLAVE_EBI_CH0>,
> +					<&mem_noc MASTER_AMPSS_M0 &system_noc SLAVE_PCIE_0>;
> +			interconnect-names = "pcie-mem", "cpu-pcie";
>  
>  			resets = <&gcc GCC_PCIE_BCR>;
>  			reset-names = "core";
> -- 
> 2.7.4
> 

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Re: [PATCH v9 3/4] arm: dts: qcom: sdx55: Add CPU PCIe interconnect path

[Krishna Chaitanya Chundru]

On 7/19/2023 10:11 AM, Manivannan Sadhasivam wrote:
> On Tue, Jul 18, 2023 at 08:50:44PM +0530, Krishna chaitanya chundru wrote:
>> Add cpu-pcie interconnect path to sdx65 platform.
> sdx55 and please mention "PCIe RC". Perhaps you should also add "missing"?
>
> - Mani

I will reactify it.

for "PCIe RC" you mean "PCIe EP" as this endpoint node

-KC


>
>> Signed-off-by: Krishna chaitanya chundru <quic_krichai@quicinc.com>
>> ---
>>   arch/arm/boot/dts/qcom/qcom-sdx55.dtsi | 5 +++--
>>   1 file changed, 3 insertions(+), 2 deletions(-)
>>
>> diff --git a/arch/arm/boot/dts/qcom/qcom-sdx55.dtsi b/arch/arm/boot/dts/qcom/qcom-sdx55.dtsi
>> index df3cd9c..a7c0c26 100644
>> --- a/arch/arm/boot/dts/qcom/qcom-sdx55.dtsi
>> +++ b/arch/arm/boot/dts/qcom/qcom-sdx55.dtsi
>> @@ -422,8 +422,9 @@
>>   			interrupt-names = "global",
>>   					  "doorbell";
>>   
>> -			interconnects = <&system_noc MASTER_PCIE &mc_virt SLAVE_EBI_CH0>;
>> -			interconnect-names = "pcie-mem";
>> +			interconnects = <&system_noc MASTER_PCIE &mc_virt SLAVE_EBI_CH0>,
>> +					<&mem_noc MASTER_AMPSS_M0 &system_noc SLAVE_PCIE_0>;
>> +			interconnect-names = "pcie-mem", "cpu-pcie";
>>   
>>   			resets = <&gcc GCC_PCIE_BCR>;
>>   			reset-names = "core";
>> -- 
>> 2.7.4
>>

Re: [PATCH v9 3/4] arm: dts: qcom: sdx55: Add CPU PCIe interconnect path

[Manivannan Sadhasivam]

On Wed, Jul 19, 2023 at 12:03:11PM +0530, Krishna Chaitanya Chundru wrote:
> 
> On 7/19/2023 10:11 AM, Manivannan Sadhasivam wrote:
> > On Tue, Jul 18, 2023 at 08:50:44PM +0530, Krishna chaitanya chundru wrote:
> > > Add cpu-pcie interconnect path to sdx65 platform.
> > sdx55 and please mention "PCIe RC". Perhaps you should also add "missing"?
> > 
> > - Mani
> 
> I will reactify it.
> 
> for "PCIe RC" you mean "PCIe EP" as this endpoint node
> 

Oops, yeah it is PCIe EP only.

- Mani

> -KC
> 
> 
> > 
> > > Signed-off-by: Krishna chaitanya chundru <quic_krichai@quicinc.com>
> > > ---
> > >   arch/arm/boot/dts/qcom/qcom-sdx55.dtsi | 5 +++--
> > >   1 file changed, 3 insertions(+), 2 deletions(-)
> > > 
> > > diff --git a/arch/arm/boot/dts/qcom/qcom-sdx55.dtsi b/arch/arm/boot/dts/qcom/qcom-sdx55.dtsi
> > > index df3cd9c..a7c0c26 100644
> > > --- a/arch/arm/boot/dts/qcom/qcom-sdx55.dtsi
> > > +++ b/arch/arm/boot/dts/qcom/qcom-sdx55.dtsi
> > > @@ -422,8 +422,9 @@
> > >   			interrupt-names = "global",
> > >   					  "doorbell";
> > > -			interconnects = <&system_noc MASTER_PCIE &mc_virt SLAVE_EBI_CH0>;
> > > -			interconnect-names = "pcie-mem";
> > > +			interconnects = <&system_noc MASTER_PCIE &mc_virt SLAVE_EBI_CH0>,
> > > +					<&mem_noc MASTER_AMPSS_M0 &system_noc SLAVE_PCIE_0>;
> > > +			interconnect-names = "pcie-mem", "cpu-pcie";
> > >   			resets = <&gcc GCC_PCIE_BCR>;
> > >   			reset-names = "core";
> > > -- 
> > > 2.7.4
> > > 

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