From: Conor Dooley <conor@kernel.org>
To: Xingyu Wu <xingyu.wu@starfivetech.com>
Cc: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org,
Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>,
Philipp Zabel <p.zabel@pengutronix.de>,
Emil Renner Berthing <emil.renner.berthing@canonical.com>,
Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Hal Feng <hal.feng@starfivetech.com>,
linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org
Subject: Re: [PATCH v8 0/9] Add STG/ISP/VOUT clock and reset drivers for StarFive JH7110
Date: Thu, 20 Jul 2023 17:32:36 +0100 [thread overview]
Message-ID: <20230720-enjoyment-gestation-adb8baa9aaf1@spud> (raw)
In-Reply-To: <20230713113902.56519-1-xingyu.wu@starfivetech.com>
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On Thu, Jul 13, 2023 at 07:38:53PM +0800, Xingyu Wu wrote:
> This patch serises are base on the basic JH7110 SYSCRG/AONCRG
> drivers and add new partial clock drivers and reset supports
> about System-Top-Group(STG), Image-Signal-Process(ISP)
> and Video-Output(VOUT) for the StarFive JH7110 RISC-V SoC. These
> clocks and resets could be used by DMA, VIN and Display modules.
>
> Patches 1 and 2 are about the System-Top-Group clock and reset
> generator(STGCRG) part. The first patch adds docunmentation to
> describe STG bindings, and the second patch adds clock driver to
> support STG clocks and resets as auxiliary device for JH7110.
>
> Patches 3 and 4 are about the Image-Signal-Process clock and reset
> gennerator(ISPCRG) part. The first patch adds docunmentation to
> describe ISP bindings, and the second patch adds clock driver to
> support ISP clocks and resets as auxiliary device for JH7110.
> And ISP clocks should power on and enable the SYSCRG clocks first
> before registering.
>
> Patches 5 and 6 are about the Video-Output clock and reset
> generator(VOUTCRG) part. The first patch adds docunmentation to
> describe VOUT bindings, and the second patch adds clock driver to
> support VOUT clocks and resets as auxiliary device for JH7110.
> And VOUT clocks also should power on and enable the SYSCRG clocks
> first before registering.
>
> Patch 7 adds struct members to support STG/ISP/VOUT resets.
> Patch 8 adds external clocks which ISP and VOUT clock driver need.
> Patch 9 adds device node about STGCRG, ISPCRG and VOUTCRG to JH7110 dts.
b4 did not detect this correctly, but I picked these 2 up too.
They should be in next tomorrow.
Please let your co-workers know that they should resend anything that I
didn't sent a thanks email for today, as it failed to apply (eg DMA,
eMMC).
Thanks,
Conor.
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next prev parent reply other threads:[~2023-07-20 16:32 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-07-13 11:38 [PATCH v8 0/9] Add STG/ISP/VOUT clock and reset drivers for StarFive JH7110 Xingyu Wu
2023-07-13 11:38 ` [PATCH v8 1/9] dt-bindings: clock: Add StarFive JH7110 System-Top-Group clock and reset generator Xingyu Wu
2023-07-13 11:38 ` [PATCH v8 2/9] clk: starfive: Add StarFive JH7110 System-Top-Group clock driver Xingyu Wu
2023-07-13 11:38 ` [PATCH v8 3/9] dt-bindings: clock: Add StarFive JH7110 Image-Signal-Process clock and reset generator Xingyu Wu
2023-07-13 11:38 ` [PATCH v8 4/9] clk: starfive: Add StarFive JH7110 Image-Signal-Process clock driver Xingyu Wu
2023-07-13 11:38 ` [PATCH v8 5/9] dt-bindings: clock: Add StarFive JH7110 Video-Output clock and reset generator Xingyu Wu
2023-07-13 11:38 ` [PATCH v8 6/9] clk: starfive: Add StarFive JH7110 Video-Output clock driver Xingyu Wu
2023-07-13 11:39 ` [PATCH v8 7/9] reset: starfive: jh7110: Add StarFive STG/ISP/VOUT resets support Xingyu Wu
2023-07-13 11:39 ` [PATCH v8 8/9] riscv: dts: starfive: jh7110: Add DVP and HDMI TX pixel external clocks Xingyu Wu
2023-07-13 11:39 ` [PATCH v8 9/9] riscv: dts: starfive: jh7110: Add STGCRG/ISPCRG/VOUTCRG nodes Xingyu Wu
2023-07-20 16:32 ` Conor Dooley [this message]
2023-07-21 6:41 ` [PATCH v8 0/9] Add STG/ISP/VOUT clock and reset drivers for StarFive JH7110 Xingyu Wu
2023-07-21 9:32 ` Conor Dooley
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