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[59.124.168.89]) by smtp.gmail.com with ESMTPSA id j18-20020aa78d12000000b00679fef56287sm1197529pfe.147.2023.07.20.06.51.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 20 Jul 2023 06:51:58 -0700 (PDT) From: Eric Lin To: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, palmer@dabbelt.com, paul.walmsley@sifive.com, will@kernel.org, mark.rutland@arm.com, tglx@linutronix.de, peterz@infradead.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Cc: zong.li@sifive.com, greentime.hu@sifive.com, vincent.chen@sifive.com, Eric Lin , Nick Hu Subject: [PATCH v2 1/3] dt-bindings: riscv: sifive: Add SiFive Private L2 cache controller Date: Thu, 20 Jul 2023 21:51:19 +0800 Message-Id: <20230720135125.21240-2-eric.lin@sifive.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230720135125.21240-1-eric.lin@sifive.com> References: <20230720135125.21240-1-eric.lin@sifive.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This add YAML DT binding documentation for SiFive Private L2 cache controller Signed-off-by: Eric Lin Reviewed-by: Zong Li Reviewed-by: Nick Hu --- .../bindings/cache/sifive,pl2cache.yaml | 62 +++++++++++++++++++ 1 file changed, 62 insertions(+) create mode 100644 Documentation/devicetree/bindings/cache/sifive,pl2cache.yaml diff --git a/Documentation/devicetree/bindings/cache/sifive,pl2cache.yaml b/Documentation/devicetree/bindings/cache/sifive,pl2cache.yaml new file mode 100644 index 000000000000..ee8356c5eeee --- /dev/null +++ b/Documentation/devicetree/bindings/cache/sifive,pl2cache.yaml @@ -0,0 +1,62 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +# Copyright (C) 2023 SiFive, Inc. +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: SiFive Private L2 Cache Controller + +maintainers: + - Greentime Hu + - Eric Lin + +description: + The SiFive Private L2 Cache Controller is per core and + communicates with both the upstream L1 caches and + downstream L3 cache or memory, enabling a high-performance + cache subsystem. + +allOf: + - $ref: /schemas/cache-controller.yaml# + +properties: + compatible: + items: + - const: sifive,pl2cache1 + - const: cache + + cache-block-size: true + cache-level: true + cache-sets: true + cache-size: true + cache-unified: true + + reg: + maxItems: 1 + + next-level-cache: true + +required: + - compatible + - cache-block-size + - cache-level + - cache-sets + - cache-size + - cache-unified + - reg + +additionalProperties: false + +examples: + - | + cache-controller@10104000 { + compatible = "sifive,pl2cache1","cache"; + cache-block-size = <64>; + cache-level = <2>; + cache-sets = <512>; + cache-size = <262144>; + cache-unified; + reg = <0x10104000 0x4000>; + next-level-cache = <&L4>; + }; -- 2.40.1